PANASONIC MN673276

Total
pages
CODE No.
81
Total pages of
separate sheets
Confidential
(Preliminary)
SPECIFICATIONS
PART No.:
MN673276
The products and specifications are subject to change without any notice.
Please ask for the latest Specifications to guarantee the satisfaction of
your product requirements.
SYSTEM LSI DIVISION
SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED BY
DATE PREPARED
June 28, 2002
DATE ESTABLISHED
APPLIED BY
CHECKED BY
PREPARED BY
Page
1
Confidential
(Preliminary)
MN673276
SPECIFICATIONS
Total
pages
Page
2
Request for your special attention and precautions in using
the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese
Government if any of the products or technologies described in this material and controlled under
the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan.
(2) The technical information described in this material is limited to showing representative
characteristics and applied circuit examples of the products. It does not constitute the warranting
of industrial property, the granting of relative rights, or the granting of any license.
(3) The products described in this material are intended to be used for standard applications or general
electronic equipment (such as office equipment, communications equipment, measuring
instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
• Special applications (such as for airplanes, aerospace, automobiles, traffic control
equipment, combustion equipment, life support systems and safety devices) in which
exceptional quality and reliability are required, or if the failure or malfunction of the
products may directly jeopardize life or harm the human body.
• Any applications other than the standard applications intended.
(4) The products and product specifications described in this material are subject to change without
notice for reasons of modification and/or improvement. At the final stage of your design,
purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in
advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the guaranteed values, in particular those of
maximum rating, the range of operating power supply voltage and heat radiation characteristics.
Otherwise, we will not be liable for any defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, redundant design is recommended,
so that such equipment may not violate relevant laws or regulations because of the function of our
products.
(6) When using products for which dry packing is required, observe the conditions (including shelf
life and after-unpacking standby time) agreed upon when specification sheets are individually
exchanged.
! This document is based on an equivalent Japanese document that was prepared on Apr. 25, 2002.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
1.
Total
pages
Page
3
Table of Contents
ESTABLISHED
1.
Table of Contents
2.
Product Type
3.
Function Overview
4.
Features
5.
Block Diagram
6.
Function Descriptions
7.
Register Setting
8.
Pin Descriptions
9.
Pin Assignment
10.
Timing Chart
11.
Application Examples
12.
CCD Drive/Synchronization Mode
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
2.
Total
pages
Page
4
Product Type
LSI with A/D and D/A converters for digital signal processing (Y, C, ALC, AWB, and AGC) of
cameras.
3.
Function Overview
This is an LSI for monitoring cameras and PC inputs. In addition to its standard function, i.e.
luminance and chroma signal processing, this LSI features ALC, AWB, and AGC, which have
conventionally been left to a microprocessor, and an analog CDS/AGC circuit, which has
conventionally been added externally. These features are integrated with SSG, CG, and I2C into
a single chip.
4.
Features
(1) Input:
(2) Output:
Analog signal (A/D input)
Analog output
Y signal
C signal
Composite output
RGB output
(3) Operating supply voltage:
3.3 V ± 0.3 V (IO, DAC, analog CDS/AGC)
2.0 V ± 0.2 V (internal logic, ADC)
(4) Operating frequency range: 9.5 MHz to 28.7 MHz
(5) Form to supply:
LQFP100-P-1414
(6) Major functions
Built-in 10-bit A/D converter
•
Built-in 10-bit D/A converter (1 ch)
•
Built-in 8-bit D/A converter (2 ch)
•
Built-in analog CDS/AGC
•
Built-in CG and SSG
•
510 H and 768 H (NTSC/PAL system)
•
Monochrome CCD signal processing is available.
•
CCD defect compensation circuit (including a color defect corrective function)
•
Max. digital AGC gain: 18 dB
•
Left/Right reversal function (controlled by external pins)
•
Adjustable gamma (0.3 to 1)
•
Supports external synchronization in HD/VD, VD2, SYNC, and LL modes.
•
Built-in I2C bus
•
ELC/AGC
•
2-mode white balance (Manual/ATW) with an ATW locking function
•
OB auto corrective function (analog/digital)
•
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
V-Dr
V1～V4
R, H1, H2
MN673276
DS1, DS2
CDS/AGC
SSG
ＴＧ
10ｂｉｔ
ＡＤＣ
ALC
AGC
AWB
Cprocess
Yprocess
RGB
CONV
ENC
SDA
SCL
G/Y/Composit
B/C/UV
R
SPECIFICATIONS
(Preliminary)
LQFP100-P-1414
Ｉ２Ｃ
I/F
１０ｂｉｔＤＡＣ
８ｂｉｔ
ＤＡＣ
2ｃｈ
REG
5.
ＣＣＤ
510H NTSC/PAL
768H NTSC/PAL
Confidential
MN673276
Total
pages
Page
5
Block Diagram
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
Page
6
CDS/AGC/16-bit ADC Block Diagram
Inside of the LSI
DCCLIP_CONT
CPOB
CPOB
OB_CONTROL
OB_CONTROL
VFSIG
DS1
CCD OUT
VDACOB
VREFL
AGC_Buffer
S/H
CPOB
CDS_Buffer
VCA
To ADC
S/H
AMP
CDS_Buffer
VSSIG
DS2
Reset
DAC
VDACGAIN
Clamp voltage
Video
POWD
Feedthrough
CPOB
To ALC control
0dB_AMP
CDS_CLAMP_CONTROL
CDS_CLAMP_CONTROL
DS1
DS2
(1) The CCD output signals are input to VFSIG and VSSIG of the DSP, and sampled by DS1
and DS2. Then the signal components are output via the differential amplifier.
(Properly set the phases of DS1 and DS2 in the registers WEC2 and C3.)
(2) After amplification in the AGC amplifier, the OB level is added to the signals, and the
signals are input to ADC.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
6.
Total
pages
Page
7
Function Descriptions
(Functions of each block)
•
CDS/AGC
Conducts correlation double sampling on signals output from the CCD to sample signal
components. This block also has an analog AGC circuit to perform AGC in an analog fashion.
•
ADC
Converts CCD signals subjected to CDS into 10-bit digital signals.
•
PATGEN
Generates pattern signals with three-color bars. Both horizontal and vertical patterns are available.
This block emulates outputs from the four-complementary-color filters of the CCD. This is useful
for isolating problems in the analog sections from CCD to ADC from those in the LSI.
It can also be used as a blue background by temporarily stopping the video output from the CCD.
•
AGC (AGC, Pixel MIX, Mirror image, and OB clamp)
This is a digital AGC. It performs AGC in a digital fashion interlocked with ALC (Max. +18 dB).
In the mirror mode of the 510 H/768 H-pixel CCD, video signals can be reversed by controlling
the RAM. This block also corrects OB. The digital mode is for processing in the LSI, and the
analog mode is to control the clamp voltage of the IC for CDS/AGC.
•
ALC
Performs full-screen center-weighted averaging metering according to luminance signal inputs,
compares the result to a target optimum exposure value, and controls the electronic shutter of the
CCD to electronically control the amount of light.
During ELC, the AGC circuit is also used for smooth control because the accumulation time of the
electronic shutter is discrete. This block also performs a 3-field averaging flicker control.
•
Y system
After generating a luminance signal using outputs from the complementary color filter CCD in LPF,
this block generates horizontal and vertical aperture signals, and performs coring, low luminance
suppression, gamma correction, and blanking. Two outline corrective levels are selectable in the
external pin APGAIN.
This block has a CCD defect compensation circuit. Gamma can be continuously adjusted from 0.3
to 1. Ready for monochrome CCD, bypassing the LPF for luminance signals is available.
•
C system
This block performs white balance processing, carrier balance, color temperature correction, and
low/high luminance chroma suppression.
•
AWB
Generates auto white balance control signals. With low-illuminance scenes, the white balance
operation holds just before an optimum illuminance status.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
(Preliminary)
MN673276
SPECIFICATIONS
Total
pages
Page
•
ENC
Modulates in accordance with the selection of NTSC/PAL. Integrates the clock systems into one
system by adopting a digital VCO system, which generates 4fSC from FCK. To create composite
video signals, Y signals are also mixed in a digital fashion by clock rate conversion. Digital mixing
is available for SYNC.
•
RGBconv
This is a matrix circuit to convert YUV signals comprising Y and C signals into RGB signals.
Note that the UV signal bands of all 3 channels are not the same as those of Y signals, unlike
3-CCD cameras, because the band of signals is reduced to approx. 800 kHz in the relatively early
stages of the C signals.
•
DAC
Converts digital outputs into analog ones. There are three channels, one for composite, Y, and G
signals. It also has a 10-bit accuracy for digital mixing of SYNC. The other two channels are 8-bit
DAC for chroma, R, and B signals.
•
PWM
Has a 4-ch PWM output that can independently control analog circuits around the LSI.
For example, this block can be used for adjusting VREF of DAC.
•
CG
Generates high-speed pulses for CCD (H1, H2, R, DS1, and DS2).
The power supply for this logic block is separated from that of other logic blocks in the LSI to
protect it from noise.
•
SSG
Generates low-speed pulses for CCD and other pulses for signal processing. Also supports external
synchronization. (VBS Gen locking is not available.)
•
I2C
When the power is turned on, this block reads an external EEPROM and sets the registers in the LSI.
Because this does not support multi-master, an external device should not be a master when the
power is turned on.
Read/write in the registers of the LSI from external devices are available (partly restricted).
ESTABLISHED
REVISED
8
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
Total
pages
Page
9
7. Register Descriptions
ADR
**H
00H
Data Configuration Standard Adjustable
R/W
Setting
Range
7 6 5 4 3 2 1 0
80H
W
−＊＊＊＊＊＊＊
Data Descriptions
I2C/SCL frequency switching @i2c
(57h: 400 kHz Others: 100 kHz)
Read mode switching as a master @i2c
(0: Random read 1: Sequential read)
OB reference data @obclp
(Reference data for digital clamping)
01H
02H
H aperture coring @hvap
Color/Monochrome switching @ylpf (0: Monochrome
1: Color)
(Not assigned)
03H
AGC threshold @hvap
(When aperture gain decreases due to increase of AGC
gain)
OB sample select @obclp
(Horizontal phase setting: 0 is prohibited)
1T DSEL@obclp (0: 4T width 1: 8T wide-ready)
OB clamp ON/OFF switching @obclp
(0: ON 1: OFF (digital clamping ON/OFF))
HAP coring when AGC gain increases @hvap
NRST phase switching @RRAMCNT
ON/OFF of AP gain decreasing when AGC gain
increases @hvap (0: OFF 1: ON)
AP gain when AGC gain increases @hvap
(0: 1/2 1: 1/4)
ON/OFF of AP coring up when AGC gain increases @
hvap (0: OFF 1: ON)
AP gain decrease threshold hysteresis @hvap
(Valid only when AGC gain increases)
(Not assigned) @i2c
GATEWE @i2c
(0: Normal 1: Gated clock mode)
READ @i2c
(0: Normal 1: Forcefully shifts to the master mode)
(Not assigned)
04H
05H
06H
07H
08H
09H
0AH
0BH
Edge coloring suppression: Suppression width switching
@apcsup (00: 2 01: 3 10: 4 11: 5)
Edge coloring suppression: Change amount switching
@apcsup (00: 16 10: 8 11: 4)
Edge coloring suppression: Max. suppression amount
switching @apcsup
(00: -25 dB 01: -3 dB 10: -6 dB 11: -12 dB)
High illuminance color suppression: Suppression width
switching @apg (00: 3 01: 4 10: 5 11: 1)
Luminance signal DC setting @yadj
Chroma coring @cgain
ESTABLISHED
REVISED
W
＊−−−−−−−
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
−−−−−−−＊
0CH
01H
W
W
＊＊＊＊＊＊＊−
＊＊＊＊＊＊＊＊
FFH
W
−−＊＊＊＊＊＊
84H
W
−＊−−−−−−
＊−−−−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−−＊
W
W
0CH
46H
05H
W
W
W
−−−−−−＊−
W
−−−−−＊−−
W
＊＊＊＊＊−−−
W
−−−−−−−＊
−−−−−−＊−
02H
W
−−−−−＊−−
＊＊＊＊＊−−−
−−−−−−＊＊
W
E1H
W
−−−−＊＊−−
W
−−＊＊−−−−
W
＊＊−−−−−−
W
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
10H
06H
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
ADR
0CH
0DH
0EH
0FH
10H
BPF characteristic switching @prelp
(0: (1+Z-2) 3 (1+Z-4) 1: (1+Z-2) 3
FCK 05 phase switching 1 @wbmpy
FCK 05 phase switching 2 @wbmpy
FCK 05 phase switching 3 @cgmlp
FCK 05 phase switching 4 @rbmtx
AWB gain fixing SW @wbmpy
(0: Normal 1: Fixed WB gain)
(Not assigned)
Base clip (B-Y) @cgain
Base clip (R-Y) @cgain
＊＊−−−−−−
−−−−＊＊＊＊
＊＊＊＊−−−−
00H
W
W
C gamma setup @cgset
B carrier balance @cgain
(to be adjusted according to the video)
R carrier balance @cgain
(to be adjusted according to the video)
R-Y matrix gain @rbmtx
(Not assigned)
＊＊＊＊＊＊＊＊
−−−−＊＊＊＊
00H
00H
W
W
B-Y matrix gain @rbmtx
(Not assigned)
13H
CCD defect correction: Black detection level LSB @mdf
(OFF at FFH, Address 35H for MSB)
R-Y gain @cgain
19H
Flicker correction ON/OFF switching @fgain
(00: ON 01: Y OFF 10: C OFF 11: YC OFF)
(Not assigned)
B-Y gain @cgain
YC phase adjustment @ycdsel
UV output control: FH2 phase adjustment @ycdsel
UV output control: FC05 phase adjustment @ycdsel
UV output control: UV phase adjustment @ycdsel
UV output control: C/UV output switching @ycdsel
(0: C 1: UV)
Y gain @yadj (1x at 80H)
AGC-interlocked aperture suppression factor @aagc
(00: 1 01: 1/2 10: 1/4 11: 3/8)
AGC-interlocked color suppression factor @aagc
(00: 1 01: 1/2 10: 1/4 11: 3/8)
ESTABLISHED
REVISED
W
＊＊＊＊−−−−
12H
18H
10
W
W
W
W
W
−−−−−−＊−
−−−−−＊−−
−−−−＊−−−
−−−＊−−−−
−−＊−−−−−
CCD defect correction: White detection level LSB @mdf
(OFF at FFH, Address 35H for MSB)
16H
17H
Page
Data Configuration Standard Adjustable
R/W
Setting
Range
7 6 5 4 3 2 1 0
00H
−−−−−−−＊
W
Data Descriptions
11H
14H
15H
Total
pages
−＊＊＊＊＊＊＊
＊−−−−−−−
＊＊＊＊＊＊＊＊
02H
W
FFH
W
−＊＊＊＊＊＊＊
＊−−−−−−−
＊＊＊＊＊＊＊＊
22H
W
FFH
W
＊＊＊＊＊＊＊＊
−−−−−−＊＊
9DH
00H
W
W
86H
O5H
W
＊＊＊＊＊＊−−
＊＊＊＊＊＊＊＊
−−−−＊＊＊＊
−−−＊−−−−
−−＊−−−−−
−＊−−−−−−
＊−−−−−−−
W
W
W
W
W
＊＊＊＊＊＊＊＊
80H
W
−−−−−−＊＊
00H
W
−−−−＊＊−−
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
ADR
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
Negative/Positive switching @yadj (0: Normal 1:
Negative)
Normal input/ramp waveform input switching @yadj
(0: Normal input 1: Ramp waveform input)
(Not assigned)
Color defect correction setting @ckizu
(00: Correction OFF 10: 2-pixel continuous 11:
1-pixel forced)
(Not assigned)
23H
24H
25H
26H
27H
28H
29H
R factor @rgb1 (Factor 0.5 at 80H)
B factor @rgb1 (Factor 0.5 at 80H)
R gain @rgb2 (1x at 80H)
B gain @rgb2 (1x at 80H)
G gain @rgb2 (1x at 40H)
R offset @rgb2
B offset @rgb2
2AH
2BH
G offset @rgb2
Insufficient blackening correction start level @yadj
(The pedestal sinks at this AGC gain value or less)
Insufficient blackening correction low clip value
(Clip value: Register value - 64)
Insufficient blackening correction gain setting
(000: 1/16 001: 1/8 010: 1/4 011: 1/2 100: 1
101: 2)
Insufficient blackening correction ON/OFF (0: OFF
ON)
(Not assigned)
PWM0
PWM1
2CH
2DH
2EH
2FH
ESTABLISHED
REVISED
11
W
−−−−−−＊−
Color gain decrease aperture offset @apcsup
(Off at 7FH)
Edge color suppression: VAP suppression ON/OFF
switching @apcsup
(0: OFF 1: ON)
AWB saturation level @sat (OFF at FFH)
AGC-interlocked aperture suppression offset @aagc
(OFF at FFH)
AGC-interlocked color suppression offset @aagc (OFF
at FFH)
RGBCNV U gain @rgb1 (1x at 80H)
RGBCNV V gain @rgb1 (1x at 80H)
FC05 phase switching @rgb1
UV phase adjustment
Page
Data Configuration Standard Adjustable
R/W
Setting
Range
7 6 5 4 3 2 1 0
00H
W
−−−−−−−＊
Data Descriptions
22H
Total
pages
1:
＊＊＊＊＊＊−−
−−−−−−＊＊
00H
W
＊＊＊＊＊＊−−
−＊＊＊＊＊＊＊
7FH
W
W
＊−−−−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
FFH
FFH
W
W
＊＊＊＊＊＊＊＊
FFH
W
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
80H
80H
W
W
−−−−−−−＊
−−−−−−＊−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
00H
W
W
4CH
1DH
80H
80H
6DH
00H
00H
W
W
W
W
W
W
W
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
00H
00H
W
W
−＊＊＊＊＊＊＊
00H
W
−−−−−＊＊＊
00H
W
W
−−−−＊−−−
＊＊＊＊−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
00H
00H
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
Data Descriptions
30H
Digital OB control coring setting
Digital OB control hysteresis setting
31H
32H
(Not assigned)
Internal AD/External AD switching @obclp (0: Normal
1: External AD)
Test/Normal switching @ (0: Normal 1: Color bar)
(Not assigned)
AD power down ON/OFF
(0: OFF 1: ON (HCLR = Power down for “H” period)
(Not assigned)
D clamp/A clamp switching (0: D clamp 1: A clamp)
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
OB auto correction reference value @obclp (OB
reference value)
(Not assigned)
Number of OB sampling times switching @obclp
(00: 256 01: 128A 10: 128B 11: 256 (Same as
"00"))
Reversing video left to right @RRAMCNT (0: Normal
1: Reversed left to right)
CCD defect correction: White detection level MSB
@mdf (Address 11H for LSB)
CCD defect correction: Black detection level MSB
@mdf (Address 13H for LSB)
(Not assigned)
Offset decrement @ladd
(Offset: 64 (40H) for 10-bit data)
Aperture low illuminance suppression offset @apg
00H: OFF
High illuminance color suppression off set @apg
FFH: OFF
Low illuminance color suppression offset @apg
00H: OFF
Aperture low illuminance suppression factor @apg
(00: 1 01: 1/2 10: 1/4 11: 3/8)
High illuminance color suppression factor @apg
(00: 1 01: 1/2 10: 1/4 11: 3/8 100: 0)
Low illuminance color suppression factor @apg
(00: 1 01: 1/2 10: 1/4 11: 3/8)
(Not assigned)
VAP coring @hvap
VAP coring when AGC gain increases @ hvap
HAP gain @hvap (Adjustable from 0x to 4x)
VAP gain @hvap (Adjustable from 0x to 4x)
Test switching when mounted @yadj
(0: Normal 1: Test)
Aperture decrease amount switching @hvap
(0: Decreasing by 100% 1: Decreasing by 50%)
ESTABLISHED
REVISED
Total
pages
Page
12
Data Configuration Standard Adjustable
R/W
Setting
Range
7 6 5 4 3 2 1 0
19H
W
−−−−−＊＊＊
W
＊＊＊＊＊−−−
00H
＊＊＊＊＊＊＊＊
10H
W
−−−−−−−＊
W
−−−−−−＊−
W
−−−−＊＊−−
−−−＊−−−−
W
−＊＊−−−−−
＊−−−−−−−
＊＊＊＊＊＊＊＊
40H
W
−−−−−−＊＊
−−−−＊＊−−
00H
W
W
−−−＊−−−−
−−−−−−＊＊
0FH
W
W
−−−−＊＊−−
＊＊＊＊−−−−
＊＊＊＊＊＊＊＊
80H
W
＊＊＊＊＊＊＊＊
00H
W
＊＊＊＊＊＊＊＊
90H
W
＊＊＊＊＊＊＊＊
00H
W
−−−−−−＊＊
03H
W
−−−＊＊＊−−
W
−＊＊−−−−−
W
＊−−−−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−−＊
−−−−−−＊−
0CH
0CH
40H
40H
00H
W
W
W
W
W
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
ADR
Data Descriptions
40H
ALC full-screen averaging in H direction start
@alclp
ALC full-screen averaging in H direction end
@alclp
ALC full-screen averaging in V direction start
@alclp
ALC full-screen averaging in V direction end
Lower 8B @alclp
ALC full-screen averaging in V direction end
MSB @alclp
ALC full-time 3 V control ON/OFF selecting
(0: Normal 1: Full-time 3 V control)
Setting a particular period after powering on
@alclp
ON/OFF setting in a particular period after
powering on @alclp (0: ON 1: OFF)
Center weighting in H direction start @alcar
Center weighting in H direction end @alcar
Center weighting in V direction start @alcar
Center weighting in V direction end Lower 8 bits
@alcar (Address 4DH for MSB)
Number of sub output lines in the low-speed
shutter mode @hactr
Number of sub output lines in the mid-speed
shutter mode @hactr
Switching sub output system (0: Fixed change rate
1: Adjustable)
Shutter high/mid speed threshold (HSSO/2
setting) @hactr
Shutter mid/high speed threshold (HSSO/2
setting) @hactr
ELC (normal) response speed switching (in fixed
change rate mode) @hactr (0: 1/4 1: 1/8 2:
1/16 3: 1/32)
HSSMAX MSB for sub calculation when
outputting H rate (Address 4EH for lower 8 bits)
HSSMAXH MSB for sub calculation when
outputting 1/16H (Address 4FH for lower 8 bits)
Center weighting in V direction end MSB @alcar
(Address 49H for lower 8 bits)
HSSMAX for 1H control sub output calculation
@hactr (For PAL, HSSO/2 setting)
HSSMAXH for 1/16H control sub calculation
@hactr (For PAL, HSSO/2 setting)
41H
42H
43H
44H
45
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
ESTABLISHED
REVISED
Data
Standard Setting
Configuration
76543210 NTSC
PAL
510/768
510/768
13H/14H 13H/14H
********
Page
13
Adjustable
R/W
Range
W
********
89H/C8H
89H/C8H
W
********
0CH
13H
W
********
FCH
2FH
W
-------*
00H
01H
W
W
------*-*******
40H
40H
W
W
*------********
********
********
********
27H/3CH
4EH/78H
53H
A3H
27H/3CH
4EH/78H
61H
C0H
W
W
W
W
----****
28H
28H
W
W
-***----
W
*------********
CAH
65H
W
********
4BH
25H
W
------**
05H
01H
W
W
-----*--
W
----*--W
---*---********
06H
9CH
W
********
DDH
96H
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
ADR
Data Descriptions
50H
AGC change amount in HSM @hactr
Number of sub output lines in the initial area of
1/16H rate
ELC (HSM) response speed switching @hactr
(0: 1/2 1: 1/4 2: 1/8 3: 1/16 4: 1/32)
ELC speed switching in the high-speed mode after
powering on
ON/OFF in high-speed mode after powering on
(0: ON 1: OFF)
51H
Data
Standard Setting
Configuration
76543210
NTSC
PAL
510/768 510/768
62H
62H
---*****
***---------***
0AH
01H
Page
14
Adjustable
R/W
Range
W
W
W
W
--***---
W
-*------
W
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
62H
(Not assigned)
Setting of max. number of sub output lines MSB
@hssun (Address 55H for lower 8 bits)
Register setting YAVE ON/OFF @alcct
(0: Normal 1: YAVE of the register value)
Register setting YAVE @alcct
(Not assigned)
Setting of max. number of sub output lines
Lower 8B@hssun
Gain setting when AGC is off @agcun
AGC response speed switching ON/OFF
(ALCNEAR control) @agcun
(0: Speed switching 1: Speed fixed)
AGC response speed setting (0: 1x 1: 2x)
AGC ON/OFF selecting (0: ON 1: OFF)
AGC mode switching (0: Digital AGC 1:Analog
AGC)
AGC max. setting @agcun
Analog AGC offset @agcun
Digital AGC offset @agcun
(Not assigned)
Flicker gain selecting @fgain
Gain setting when flicker correction in low
illuminance scene is off
Flicker OFF threshold in low illuminance scene
@fgain
ALC HSM threshold: Higher than the target value
@alcct
ALC HSM threshold: Lower than the target value
@alcct
ALC target value (in BLCON state) @alcct
ALC target value (in BLCOFF state) @alcct
Convergence coring offset setting @alcct
Coring setting when AGC is ON
ESTABLISHED
REVISED
*------------**
01H
02H
W
W
-----*-********
00H
00H
W
********
D4H
50H
W
********
-------*
00H
09H
00H
09H
W
W
W
W
W
------*-----*-----*--********
********
********
80H
40H
20H
80H
40H
20H
W
W
W
-------*
*******-
FFH
FFH
W
W
********
0AH
0AH
W
********
76H
76H
W
********
14H
14H
W
********
********
----****
****----
4CH
26H
63H
4CH
26H
63H
W
W
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
ADR
Data Descriptions
63H
Threshold of 1 V/3 V control switching in the
normal state @alcct
Coring ON/OFF when AGC is ON
(0: OFF 1: ON (1 V only))
Convergence coring setting (0: 1/64 1: 1/128
2: 1/256 3: 1/256)
Threshold of sub output rate switching
(ALCNEAR) @alcct
Coring when BLC is ON
IRIS 1 V/3 V control switching
(0: ON 1: OFF)
ULI Threshold higher than the target value @alcct
ULI Threshold lower than the target value @alcct
Area A weighting coefficient in the BLCOFF
state @alcav (08H: x 1)
Area A weighting coefficient in the BLCON state
@alcav
IRIS change amount switching threshold
(IRISNEAR) @alcct
HSM 3 V/1 V control switching
(0: Switching (1/3 V) 1: Fixed (1 V only))
ON/OFF switching of high-speed mode after
powering on (0: ON 1: OFF)
HSM ON/OFF switching
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
Area B weighting coefficient in the BLCOFF state
@alcav (20H: x 4)
Area B weighting coefficient in the BLCON state
@alcav (20H: x 4)
Area C weighting coefficient in the BLCOFF state
@alcav (10H: x 2)
Area C weighting coefficient in the BLCON state
@alcav (10H: x 2)
IRIS coring value setting @alcct
SUB output when ALCELC = H @hssun
IRIS offset in BLCOFF state (ALCDC) @hssun
IRIS offset in BLCON state (ALCDC) @hssun
LSB of sub 1/16H rate output start position
@hssun
LSB of sub output setting when ALCELC = L @
ESTABLISHED
REVISED
Data
Standard Setting
Configuration
76543210 NTSC
PAL
510/768
510/768
6AH
2AH
---*****
--*-----
15
Adjustable
R/W
Range
W
W
W
**--------*****
Page
CCH
CCH
W
W
W
-**----*------********
********
********
98H
20H
08H
98H
20H
08H
W
W
W
********
08H
08H
W
---*****
0BH
0BH
W
W
--*-----
W
-*------
W
*--------******
20H
20H
W
--******
20H
20H
W
--******
10H
10H
W
--******
10H
10H
W
---*****
********
********
********
********
00H
40H
00H
10H
F7H
00H
40H
00H
10H
24H
W
W
W
W
W
********
00H
00H
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
Data
Configuration
76543210
ADR
Data Descriptions
74H
ALC ON/OFF switching @hssun (0: ON 1: OFF)
MSB of sub 1/16H rate output start position
MSB of sub output setting when ALCELC = L
(Not assigned)
ELC_ONLY mode (0: ON 1: OFF (Set LSB to 1
first.))
IRIS upper limit setting @hssun
Screen-averaged value (Calculated value read)
H-rate shutter value HSSO LSB (Calculated value
read)
1/16 shutter value HSSOS (Calculated value read)
H-rate shutter value HSSO MSB
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
Digital AGC gain (Calculated value read)
Analog AGC gain (Calculated value read)
AGC gain (before adding offset)
(Calculated value read)
OB tracking speed switching threshold @obclp
OB tracking speed switching @obclp
(0: 8x speed 1: 16x speed)
Analog OB control offset @obclp
LSI CODE @agcreg (LSI development code
(register read only))
LSI Version @agcreg (LSI development version
(register read only))
ESTABLISHED
REVISED
-------*
-----**---**----*-----*-----********
********
********
Standard Setting
NTSC
510/768
00H
PAL
510/768
02H
Page
Adjustable
Range
16
R/W
W
W
W
W
01H
01H
W
R
R
R
R
----****
--**---********
********
********
R
R
R
---*****
--*-----
34H
34H
W
W
********
********
00H
00H
03H
W
R
01H
R
********
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
Data descriptions
80H
Full-screen averaging in H direction start position @awblp
81H
Full-screen averaging in H direction end position LSB
@awblp
Full-screen averaging in H direction end MSB @awblp
Full-screen averaging in V direction end MSB @awblp
Full-screen averaging 1 V/3 V selecting (V3OFF) @awblp
(0: 3 V 1: 1 V)
HCLR/TESTHD, VD/TESTVD selecting @awblp
(0: HD, VD 1: TESTHD, TESTVD)
Horizontal addition divisor switching @awblp (0: 1/128
1: 1/256)
ATWLOCK register switching @wbgai
(00: Pin control 01: Normal 11: ATWLOCK)
Full-screen averaging in V direction start position @awblp
Full-screen averaging in V direction end position LSB
@awblp
AWB response speed switching (for power-on mode)
@awblp (0: 1/16 V 1: 1/8 V 2: 1/4 V 3: 1/2 V
4: 1/1 V)
AWB response speed switching (for normal mode)
@awblp (0: 1/16 V 1: 1/8 V 2: 1/4 V 3: 1/2 V
4: 1/1 V)
Default when power-on mode is off @awblp
Power-on mode ON/OFF switching @awblp
(0: POWR used 1: Default used)
Drive pulse setting for AWB gain calculation (F4A, F2A)
@awblp
AWB delay adjustment @wbave (0: 0T (without delay) 1:
1T added)
POWR selecting (V3 control) @wbave
(0: V3 control (V3 invalid when POWR is "H") 1: V3
through)
Long-time storage mode setting @wbave
(0: Long-time storage mode ON 1: OFF)
AWB gain clip CG lower limit MSB @wbgai
AWB gain clip CG upper limit MSB @wbgai
AWB gain clip CMg lower limit MSB @wbgai
AWB gain clip CMg upper limit MSB @wbgai
AWB OFF gain setting R-Y MSB @wbgai
AWB OFF gain setting B-Y MSB @wbgai
AWB ON/OFF switching @wbgai (0: ON 1: OFF)
(Not assigned)
AWB gain clip CG lower limit LSB @wbgai (0F6H)
AWB gain clip CG upper limit LSB @wbgai (10BH)
AWB gain clip CMg lower limit LSB @wbgai (0F3H)
AWB gain clip CMg upper limit LSB @wbgai (10FH)
AWB OFF gain setting R-Y LSB @wbgai5 (0D9H)
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
ESTABLISHED
REVISED
Total
pages
Page
Reset
setting
17
Data configuration
7 6 5 4 3 2 1 0
＊＊＊＊＊＊＊＊
Standard
setting
1CH
＊＊＊＊＊＊＊＊
1AH
W
−−−−−−＊＊
−−−−−＊−−
−−−−＊−−−
43H
W
W
W
R/W
W
−−−＊−−−−
W
−−＊−−−−−
W
＊＊−−−−−−
W
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
0DH
FDH
W
W
−−−−−＊＊＊
24H
W
−−＊＊＊−−−
W
−＊−−−−−−
＊−−−−−−−
W
W
−−−＊＊＊＊＊
10H
W
−−＊−−−−−
W
−＊−−−−−−
W
W
＊−−−−−−−
−−−−−−−＊
−−−−−−＊−
−−−−−＊−−
−−−−＊−−−
−−−＊−−−−
−−＊−−−−−
−＊−−−−−−
＊−−−−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
3AH
W
W
W
W
W
W
W
80H
40H
40H
80H
D9H
W
W
W
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
Total
pages
Page
8DH
AWB OFF gain setting B-Y LSB @wbgai (12CH)
Data Configuration Standard
Setting
7 6 5 4 3 2 1 0
2CH
＊＊＊＊＊＊＊＊
8EH
8FH
(Not assigned)
(Not assigned)
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
00H
00H
90H
91H
(Not assigned)
AWB response speed switching ON/OFF SW @wbgai
(0: OFF 1: ON)
Switching AWB convergence speed in normal mode
@wblpf (0: 1 or 4 convergence 1: 1 or 8 convergence)
(Not assigned)
＊＊＊＊＊＊＊＊
−−−−−−−＊
00H
01H
ADR
92H
93H
94H
95H
96H
97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
Data Descriptions
AWB gain coring hysteresis setting @wblpf
ATWLOCK register switching @wblpf
(00: Pin control 01: Normal 11: ATWLOCK)
(Not assigned)
AWB gain coring hysteresis setting @wblpf
(Hysteresis valid at this value or less)
Power-on mode ON/OFF SW @wblpf (0: ON
Default when power-on mode is off @wblpf
(Not assigned)
1: OFF)
AWB gain initial value 1 (CG) @wblpf
(40H x 8 = 200H)
AWB gain initial value 2 (YM) @wblpf
(40H x 8 = 200H)
AWB gain initial value 3 (CM) @wblpf
(40H x 8 = 200H)
AWB gain initial value 4 (YG) @wblpf
(40H x 8 = 200H)
AWB response speed switching threshold 1 @wblpf
(± 2 for power-on)
AWB response speed switching threshold 2 @wblpf
(± 4 for power-on)
AWB response speed switching threshold 3 @wblpf
(± 8 for power-on)
AWB response speed switching threshold A @wblpf
(± 1 or ± 4 or ± 8 for normal mode)
AWB YM average LSB @wbave (READ data)
AWB CG average LSB @wbave (READ data)
AWB YG average LSB @wbave (READ data)
AWB CM average LSB @wbave (READ data)
ESTABLISHED
REVISED
−−−−−−＊−
＊＊＊＊＊＊−−
−−−＊＊＊＊＊
−＊＊−−−−−
＊−−−−−−−
−−−＊＊＊＊＊
Reset
Setting
18
R/W
W
W
W
22H
W
W
W
W
02H
W
−−＊−−−−−
−＊−−−−−−
＊−−−−−−−
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
10H
W
＊＊＊＊＊＊＊＊
20H
W
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
1FH
W
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
W
W
R
R
R
R
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
Data Descriptions
A0H
AWB YM average MSB @wblpf (READ data)
AWB CG average MSB @ (READ data)
AWB YG average MSB @ (READ data)
AWB CM average MSB @ (READ data)
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
LSB of calculated AWB YM gain @wblpf (READ data)
LSB of calculated AWB CG gain @wblpf (READ data)
LSB of calculated AWB YG gain @wblpf (READ data)
(Not assigned)
(Not assigned)
(Not assigned)
(Not assigned)
(Not assigned)
(Not assigned)
(Not assigned)
LSB of calculated AWB CM gain @wblpf (READ data)
MSB of calculated AWB YM gain @wblpf (READ data)
MSB of calculated AWB CG gain @wblpf (READ data)
MSB of calculated AWB YG gain @wblpf (READ data)
MSB of calculated AWB CM gain @wblpf (READ data)
ADH
AEH
(Not assigned)
AWB test mode (TM8)
(0h: YMave 1h: CGave 2h: YGave 3h: CMave
4h: WBYMGAIN 5h: WBYGGAIN 6h: YMgain)
A/D test mode (7h: CGain 8h: YGain 9h: CMgain)
(Not assigned)
AFH
ALC test mode (TM9) @alcav
(0h: Yave 1h: ALCcnt 2h: HSScnt 3h: AGCcnt
4h: MSCB 5h: Fgain 6h: HSSOUT 7h: HSSOS
8h: HSSO Ah: AGCOC Bh: DAGC Ch: ANAGC
(0: Normal 1 1: Test))
ALC test input
(Not assigned)
ESTABLISHED
REVISED
Total
pages
Page
Data Configuration Standard
Setting
7 6 5 4 3 2 1 0
−−−−−−＊＊
−−−−＊＊−−
−−＊＊−−−−
＊＊−−−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
00H
＊＊＊＊＊＊＊＊
00H
＊＊＊＊＊＊＊＊
00H
＊＊＊＊＊＊＊＊
00H
＊＊＊＊＊＊＊＊
00H
＊＊＊＊＊＊＊＊
00H
＊＊＊＊＊＊＊＊
00H
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−＊＊
−−−−＊＊−−
−−＊＊−−−−
＊＊−−−−−−
00H
＊＊＊＊＊＊＊＊
00H
−−−−＊＊＊＊
−−−＊−−−−
＊＊＊−−−−−
−−−−＊＊＊＊
−−−＊−−−−
＊＊＊−−−−−
Reset
Setting
19
R/W
R
R
R
R
R
R
R
R
R
R
R
R
W
W
00H
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
Total
pages
(Preliminary)
•
Page
20
Standard setting of the AWB metering area
The delay between the MN673276 input VIN to the AWB input DATAIN (9:0) is 23T, and a total of
28.5 (29T) including delays of input PAD (1T), inside AWB (1T), CDS (1T), and A/D (2.5T).
The AWB metering area is set taking into account this video signal delay.
In regard to the H direction, the video signal delay is calculated based on the falling edge of HCLR.
According to the calculation result, a metering area is set so that horizontal 480-pixel data is sampled
for 510H CCD, or 720-pixel data for 768H CCD. In regard to the V direction, a metering area is set so
that 230-line data is sampled for NTSC, or 280-line data for PAL, based on the falling edge of VD.
The list below shows standard mode-by-mode settings of the AWB metering area.
The modes are:
Start of full-screen averaging in the H direction (Hstart), End of full-screen averaging in the H
direction (Hend)
Start of full-screen averaging in the V direction (Vstart), End of full-screen averaging in the V
direction (Vend)
CCD
510H
MN39110
/210
CCDSEL(2:0)
NT/PAL
Hstart
Hend
Vstart
Vend
CCDSEL(2:0)=0h
NTSC
PAL
Hstart= 53(35h)
Hstart= 53(35h)
Hend=539(21Bh)
Hend=539(21Bh)
Vstart= 13(0Dh)
Vstart= 19(13h)
Vend=243(F3h)
Vend=299(12Bh)
CCDSEL(2:0)=2h
NTSC
PAL
Hstart= 53(35h)
Hstart= 53(35h)
Hend=779(30Bh)
Hend=779(30Bh)
Vstart= 12(0Ch)
Vstart= 18(12h)
Vend=242(F2h)
Vend=298(12Ah)
CCDSEL(2:0)=3h
NTSC
PAL
Hstart= 53(35h)
Hstart= 53(35h)
Hend=539(21Bh)
Hend=539(21Bh)
Vstart= 13(0Dh)
Vstart= 19(12h)
Vend=243(F3h)
Vend=299(12Bh)
CCDSEL(2:0)=4h
NTSC
PAL
Hstart= 53(35h)
Hstart= 53(35h)
Hend=779(30Bh)
Hend=779(30Bh)
Vstart= 12(0Ch)
Vstart= 19(13h)
Vend=242(F2h)
Vend=299(12Bh)
CCDSEL(2:0)=1h
768H
MN39143
/243
510H
MN39117
/217
768H
MN37140
/39241
* For PAL, the register address 82 (Addition data for full-screen averaging in the V direction 1/2 selecting:
AVPAL) should be set to "H".
Correlation between CCDSEL (2:0) and CCD type
CCDSEL(2:0)=0h 510 pixels MN39110 (NTSC)
―――
CCDSEL(2:0)=1h
CCDSEL(2:0)=2h 768 pixels MN39143 (NTSC)
CCDSEL(2:0)=3h 510 pixels MN39117 (NTSC)
CCDSEL(2:0)=4h 768 pixels MN37140 (NTSC)
ESTABLISHED
REVISED
1H=606T
――
1H=910T
1H=606T
1H=910T
510 pixels MN39210 (PAL)
―――
768 pixels MN39243 (PAL)
510 pixels MN39217 (PAL)
768 pixels MN39241 (PAL)
1H=618T
――
1H=910T
1H=606T
1H=910T
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H
C1H
C2H
C3H
C4H
C5H
C6H
Data Descriptions
Breakpoint 1 of broken line γ @gamma
Breakpoint 2 of broken line γ @gamma
Slope α1 @gamma (determined value)
Slope α2 @gamma (Slope: 1/4)
Slope α3 @gamma (Slope: 1/4)
Y intercept β1 @gamma (determined value)
Y intercept β2 @gamma
Y intercept β3 @gamma
Broken line γ ON/OFF @gamma (0: OFF 1: ON)
Negative γ control @gamma (0: Through 1: Gamma)
Gamma switching @gamma (0: 0.3 1: MN67352
equivalent)
γ characteristic switching @gamma
(80H: 0.5x C0H: γ = 0.45 00H: OFF)
Broken line start level @gamma
Edge detection threshold @prelp
Signal phase switching for AWB @prelp
HAP LPF ON/OFF switching @hvap (0: OFF 1: ON)
VAP LPF characteristic switching @hvap (0: (1+Z-1)2
1: (1+Z-1)2(1+Z-2))
VAP LPF ON/OFF switching @hvap (0: OFF 1: ON)
Gain for level adjustment @fgain (0 to 1x)
(Not assigned)
High-speed pulse phase setting 0 (H1, H2)
High-speed pulse phase setting 1 (R)
High-speed pulse phase setting 2 (DS1)
High-speed pulse phase setting 3 (DS2)
High-speed pulse phase setting 4
ENC block Y clock switching
(0: Crystal oscillation 1: LC oscillation)
CBLK, CSYNC phase adjustment
(-8T to +7T (Standard: 0T))
TG output enable signal (0: Internal TG 1: External TG)
Normal/Flicker-less/ ELC switching
(00: Normal 10: Flicker-less 11: ELC)
CH1, 2 pulse reversing
SUB pulse reversing
V1 pulse reversing
V2 pulse reversing
V3 pulse reversing
V4 pulse reversing
HSSOS setting register
HSSO setting register LSB
ESTABLISHED
REVISED
Total
pages
Data Configuration
7 6 5 4 3 2 1 0
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−−＊
−−−−−−＊−
−−−−−＊−−
Page
Standard Reset
Setting Setting
72H
FFH
B3H
2BH
40H
00H
8DH
C6H
05H
21
R/W
W
W
W
W
W
W
W
W
W
W
W
＊＊＊＊＊＊＊＊
FFH
W
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−＊＊
−−−−−−−＊
−−−−−−＊−
72H
88H
02H
00H
W
W
W
W
W
−−−−−＊−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−＊＊
−−−−−＊−−
W
FFH
W
02H
02H
02H
02H
44H
W
W
W
W
W
W
−＊＊＊＊−−−
W
＊−−−−−−−
−−−−−−＊＊
W
W
−−−−−＊−−
−−−−＊−−−
−−−＊−−−−
−−＊−−−−−
−＊−−−−−−
＊−−−−−−−
−−−−＊＊＊＊
＊＊＊＊−−−−
00H
00H
W
W
W
W
W
W
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
Data Descriptions
C7H
HSSO setting register MSB
FIN invalid signal
HSSOS, HSSO register setting switching
(0: Internal connection (to ALC block) 1: Register)
FHRST delay switching (−15T to +16T (Standard: 0T))
LLDET mode switching
VD selecting signal (0: CSYNC 1: VD)
Processing when VCO is unnecessary (0: With VCO 1:
Without VCO)
Fine adjustment of H phase in the synchronization mode
SYNC
Fine adjustment of H phase in the synchronization mode
HDVD
CPOB rising edge phase setting (CPOB start setting
value (0T to 31T))
TM3 mode output control switching
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
CPOB falling edge phase setting (CPOB stop setting
value (0T to 31T))
CPOB rising edge phase setting (CPOB2 start setting
value (0T to 31T))
CPOB falling edge phase setting (CPOB2 stop setting
value (0T to 31T))
CPOB/HCLR/FVD/CPOB2 output switching
(00: CPOB 01: HCLR 10: FVD 11: CPOB2)
PBLK/CBLK/WHD output switching
(00: PBLK 01: CBLK 10: WHD)
PWM3/FCKO/F2CKO output switching
(100: PWM3 01: FCKO 10: FCKO2)
ESTABLISHED
REVISED
Total
pages
Page
Data Configuration Standard
Setting
7 6 5 4 3 2 1 0
80H
−−＊＊＊＊＊＊
−＊−−−−−−
＊−−−−−−−
Reset
Setting
22
R/W
W
W
W
−−−＊＊＊＊＊
−−＊−−−−−
−＊−−−−−−
＊−−−−−−−
10H
W
W
W
W
＊＊＊＊＊＊＊＊
80H
W
＊＊＊＊＊＊＊＊
80H
W
−−−＊＊＊＊＊
06H
W
W
−−＊−−−−−
−−−＊＊＊＊＊
0AH
W
−−−＊＊＊＊＊
06H
W
−−−＊＊＊＊＊
0AH
W
−−−−−−＊＊
00H
W
−−−−＊＊−−
W
−−＊＊−−−−
＊＊−−−−−−
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
Data Descriptions
(R-Y)/(B-Y) switching after DD
(1: Rch = (B-Y) 0: Rch = (R-Y))
Rch/Bch phase switching after DD
(1: Rch +1T 0: Bch +1T)
YC/RGB switching (1: RGB 0: YC)
10-bit DAC output chroma SW
(1: Y only 0: Y+C)
10-bit DAC output SYNC SW
(1: SYNC OFF 0: SYNC ON)
YC/Y, UV switching (1: Y, UV 0: YC)
Y data interpolation SW after DD
(00: LPF OFF (00 or 01 or 11))
C data interpolation SW after DD
(00: LPF OFF (00 or 01 or 11))
Y-line delay adjustment after DD
(0 to 7: -1T to +6T)
(R-Y) burst level for NTSC
(use at NTSC || ( PAL && LSW=L ))
(B-Y) burst level for NTSC
(use at NTSC || ( PAL && LSW=L ))
(R-Y) burst level for PAL
(use at PAL && LSW=H)
(B-Y) burst level for PAL
(use at PAL && LSW=H)
Rch/Bch high clip level
(use at RGBmode Only)
Gch high clip level (+300 hex)
Gch low clip level (ref. = BLK level)
Pedestal (ref. = BLK level)
SYNC level LSB (ref. = BLK level)
BLK level LSB (ref. = 00 hex)
SYNC level MSB (ref. = BLK level)
BLK level MSB (ref. = 00 hex)
VCO normal increment LSB
(init value for 768 pixels/H NTSC)
VCO normal increment MSB
(init value for 768 pixels/H NTSC)
LSB of corrective increment for each H of VCO
(init value for 768 pixels/H NTSC)
ESTABLISHED
REVISED
Total
pages
Page
Data Configuration Standard
Setting
7 6 5 4 3 2 1 0
02H
−−−−−−−＊
Reset
Setting
23
R/W
W
−−−−−−＊−
W
−−−−−＊−−
−−−−＊−−−
W
W
−−−＊−−−−
W
−−＊−−−−−
−−−−−−＊＊
W
W
15H
−−−−＊＊−−
W
−＊＊＊−−−−
W
＊＊＊＊＊＊＊＊
00H
W
＊＊＊＊＊＊＊＊
D6H
W
＊＊＊＊＊＊＊＊
2AH
W
＊＊＊＊＊＊＊＊
D6H
W
＊＊＊＊＊＊＊＊
FFH
W
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−＊＊＊＊＊
−−−＊＊＊＊＊
−−−−−−−＊
−−−−−−＊−
＊＊＊＊＊＊＊＊
FFH
2AH
2AH
FFH
29H
02H
W
W
W
W
W
W
W
00H
W
＊＊＊＊＊＊＊＊
80H
W
＊＊＊＊＊＊＊＊
00H
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
Data Descriptions
E0H
MSB of increment for each H of VCO
(init value for 768 pixels/H NTSC)
LSB of increment for each V of VCO
(init value for 768 pixels/H NTSC)
MSB of increment for each V of VCO
(init value for 768 pixels/H NTSC)
Gain adjustment for 10-bit DAC
(0 to 255: GAIN = (x/64))
YGGAIN 3200K center value LSB @wbcc
(3200K YGGAIN reference value)
YMGAIN 3200K center value LSB @wbcc
(3200K YMGAIN reference value)
YGGAIN 3200K center value MSB @wbcc
YMGAIN 3200K center value MSB @wbcc
(Not assigned)
R-Y corrective gain (low color temperature) @wbcc (1x
at 40H)
R-Y corrective gain (high color temperature) @wbcc (1x
at 40H)
B-Y corrective gain (low color temperature) @wbcc (1x
at 40H)
B-Y corrective gain (high color temperature) @wbcc (1x
at 40H)
Center hysteresis part 1 @wbcc (Hysteresis valid at less
than this value)
Center hysteresis part 2 @wbcc (Threshold of valid
hysteresis)
Corrective gain limit @wbcc (Limit of the maximum
color corrective gain)
WBYGGAIN LSB @WBCC (READ data to be set in
Address E4 on condition of 3200K)
WBYMGAIN LSB @WBCC (READ data to be set in
Address E5 on condition of 3200K)
WBYGGAIN MSB @WBCC (READ data)
WBYMGAIN MSB @WBCC (READ data)
(To be set in Address E6 on condition of 3200K)
(Not assigned)
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
ESTABLISHED
REVISED
Total
pages
Page
Data Configuration Standard
Setting
7 6 5 4 3 2 1 0
80H
＊＊＊＊＊＊＊＊
Reset
Setting
24
R/W
W
＊＊＊＊＊＊＊＊
00H
W
＊＊＊＊＊＊＊＊
80H
W
＊＊＊＊＊＊＊＊
B3H
W
＊＊＊＊＊＊＊＊
00H
W
＊＊＊＊＊＊＊＊
00H
W
−−−−−−＊＊
−−−−＊＊−−
＊＊＊＊−−−−
＊＊＊＊＊＊＊＊
0AH
W
W
40H
W
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
40H
W
＊＊＊＊＊＊＊＊
40H
W
−−−−＊＊＊＊
31H
W
W
＊＊＊＊−−−−
＊＊＊＊＊＊＊＊
FFH
W
＊＊＊＊＊＊＊＊
W
＊＊＊＊＊＊＊＊
W
−−−−−−＊＊
−−−−＊＊−−
W
W
＊＊＊＊−−−−
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
ADR
Data Descriptions
EXTMOD
FLC
NTPL
CCDSEL0
CCDSEL1
CCDSEL2
LLDET
ALCELC
F0H
When the data input PAD is
occupied by another test in the
test mode, signals can be sent
into the circuit by using these
registers.
F1H
A/D sampling timing adjustment
A/D clock phase adjustment (Adjustable from 0 to phase
reverse)
ATWLOCK
When the data input PAD is
APGAIN
occupied by another test in the
BLCSW
test mode, signals can be sent
REV
into the circuit by using these
(Not assigned)
registers.
Ramp waveform start position @rampgen
Ramp waveform gain adjustment @rampgen (1x at 80H)
Ramp waveform max. value LSB @rampgen
Ramp waveform max. value MSB @rampgen
Color bar start position @patgen
Color bar width @patgen
Color bar H/V switching @patgen (0: Horizontal 1:
Vertical)
Color bar phase adjustment @patgen
(Not assigned)
CDS/AGC/AD cell test mode 1 ADCKREG
0: Normal 1: CDS/AGC power down
CDS/AGC/AD cell test mode 3, mode 2
00: Normal 01: CDS/AGC, AD isolation mode
10: AGC DAC output (VAGCOUT pin)
11: OB DAC output (VAGCOUT pin)
(Not assigned)
(Not assigned)
I2C high-speed R/W ON/OFF switching (in test mode)
(0: I2C normal operation 1: I2C high-speed R/W (in
test mode))
BLCSW/DS1 switching (0: BLCSW input 1: DS1
output)
REV/DS2 switching (Valid for other than TM3 and
TM29) (0: REV input 1: DS2 output)
(Not assigned)
NHRST phase switching @plsgen
PWM2@pwm
PWM3@pwm
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
ESTABLISHED
REVISED
Total
pages
Page
Data Configuration Standard
7 6 5 4 3 2 1 0 Setting
00H
−−−−−−−＊
−−−−−−＊−
−−−−−＊−−
−−−−＊−−−
−−−＊−−−−
−−＊−−−−−
−＊−−−−−−
＊−−−−−−−
04H
−−−−＊＊＊＊
−＊＊＊−−−−
−−−−−−−＊
−−−−−−＊−
−−−−−＊−−
−−−−＊−−−
＊＊＊＊−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−−＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
−−−−−−−＊
00H
00H
80H
FFH
01H
7EH
80H
00H
Reset
Setting
25
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
−−−−−−＊−
−−−−＊＊−−
−−−＊−−−−
W
−＊＊−−−−−
W
＊−−−−−−−
−−−−＊＊＊＊
−−−＊−−−−
W
10H
W
−−＊−−−−−
W
−＊−−−−−−
W
＊−−−−−−−
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
＊＊＊＊＊＊＊＊
46H
00H
00H
W
W
W
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
Total
pages
(Preliminary)
EEPROM
Data Descriptions
address
FEH
RGB signal/YC signal switching
* To be used for TM19 and TM28
1: R → RGBTO, YCTSEL(TM19, TM28)
1: G → RGBTO, YCTSEL(TM19, TM28)
1: B → RGBTO, YCTSEL(TM19, TM28)
1: YC → ALC →YCTSEL(TM28), RGBTO=0
1: YC → AWB →YCTSEL(TM28), RGBTO=0
1: YC → ENC →YCTSEL(TM28), RGBTO=0
1: YOUT → TCTSEL(TM28), RGBTO=0
1: COUT → YCTSEL(TM28), RGBTO=0
(Not assigned)
FFH
Slave address register @i2c (Slave address setting of
this LSI (Write only))
(Not assigned)
Data Configuration
7 6 5 4 3 2 1 0
Page
26
Standard Adjustable R/W
Setting
Range
00H
W
W
W
W
W
W
W
W
−−−−−−−＊
−−−−−−＊−
−−−−−＊−−
−−−−＊−−−
−−−＊−−−−
−−＊−−−−−
−＊−−−−−−
＊−−−−−−−
−＊＊＊＊＊＊＊
2AH
W
＊−−−−−−−
[Supplementary remarks]
Registers of the ENC block should be set as shown below according to the CCD mode because "***fH"
and the number of pixels vary with the mode.
VCO register setting
５１０ＮＴＳＣ:MN39110]６０６ｆ
[５１０ＮＴＳＣ
６０６ｆH
５１０ＮＴＳＣ
６０６ｆ
ＶＣＯＣ [１５:０] =Ｃ０３６H
ＶＣＯＨ [１５:０] =Ｃ０８ＥH
ＶＣＯＶ [１５:０] =Ｃ０８ＥH
[５１０ＰＡＬ
５１０ＰＡＬ:MN39210]６１８ｆ
６１８ｆH
５１０ＰＡＬ
６１８ｆ
ＶＣＯＣ [１５:０] =ＥＢ１５H
ＶＣＯＨ [１５:０] =ＥＢ５４H
ＶＣＯＶ [１５:０] =ＥＣ６１H
[５１０ＰＡＬ
５１０ＰＡＬ:MN39217]
６０５ｆH
５１０ＰＡＬ
６０５ｆ
ＶＣＯＣ［１５:０］＝Ｆ００１H
ＶＣＯＨ［１５:０］＝ＥＥ９４H
ＶＣＯＶ［１５:０］＝ＥＦＡ１H
［７６８ＮＴＳＣ］９１０ｆH
［７６８ＮＴＳＣ］９１０ｆ
ＶＣＯＣ [１５:０] =８０００H
ＶＣＯＨ [１５:０] =８０００H
ＶＣＯＶ [１５:０] =８０００H
［７６８ＰＡＬ］９０８ｆH
［７６８ＰＡＬ］９０８ｆ
ＶＣＯＣ［１５:０］=Ａ０００H
ＶＣＯＨ［１５:０］=Ａ１Ａ３H
ＶＣＯＶ［１５:０］=Ａ２Ｂ０H
According to the above settings, the registers of the addresses (DD, DE, DF, E0, E1, and E2) should be
set as follows:
*510H
*510H
*510H
*768H
*768H
ESTABLISHED
NTSC(39110) NTSC=”L”,
PAL (39210) NTPL=”H”,
PAL (39213) NTPL=”H”,
NTSC
NTPL=”L”,
PAL
NTPL=”H”,
REVISED
DD=36h,
DD=15h,
DD=BDh,
DD=00h,
DD=00h,
DE=C0h,
DE=EBh,
DE=EFh,
DE=80h,
DE=A0h,
DF=8Eh,
DF=54h,
DF=94h,
DF=00h,
DF=A3h,
E0=C0h,
E0=EBh,
E0=EEh,
E0=80h,
E0=A1h,
E1=8Eh,
E1=61h,
E1=A1h,
E1=00h,
E1=B0h,
E2=C0h
E2=ECh
E2=EFh
E2=80h
E2=A2h
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
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MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
7.1
Page
27
Supplementary descriptions of the CG/SSG registers
Register C0
Register C1
Register C2
Register C3
Register C4
∗∗∗∗∗∗∗∗
∗∗∗∗∗∗∗∗
∗∗∗∗∗∗∗∗
∗∗∗∗∗∗∗∗
- - - - - - ∗∗
CGSW0
CGSW1
CGSW2
CGSW3
CGSW4
High-speed pulse phase setting
High-speed pulse phase setting
High-speed pulse phase setting
High-speed pulse phase setting
High-speed pulse phase setting
7
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
6
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
*
*
5
*
*
*
*
*
*
*
*
*
*
*
*
L
H
*
*
*
*
CGSW0
4
3
*
*
*
*
*
*
*
*
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
*
*
*
*
*
*
*
*
*
*
*
*
2
*
*
*
*
L
H
L
H
L
H
L
H
*
*
*
*
*
*
1
L
L
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
L
H
L
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
7
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
L
H
H
6
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
L
H
5
*
*
*
*
*
*
*
*
*
*
*
*
L
H
*
*
*
*
CGSW1
4
3
*
*
*
*
*
*
*
*
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
*
*
*
*
*
*
*
*
*
*
*
*
2
*
*
*
*
L
H
L
H
L
H
L
H
*
*
*
*
*
*
1
L
L
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
L
H
L
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
ESTABLISHED
REVISED
Setting operation
Operation
H1, H2
-1/2T DLY
Coarse
-1/4T DLY
adjustment
0T DLY
1/4 DLY
0DLY
Fine
1DLY
adjustment
2DLY
3DLY
4DLY
5DLY
6DLY
7DLY
FCK(H1, H2) Through
Reverse
H1, H2
Through
Output
Reverse
R
Through
Output
Reverse
Adjusting signal
Adjusting signal
R
FCK(R)
R
Setting operation
Operation
-1/2 T DLY
Coarse
-1/4 T DLY
adjustment
0T DLY
1/4 DLY
0DLY
Fine
1DLY
adjustment
2DLY
3DLY
4DLY
5DLY
6DLY
7DLY
Through
Reverse
1/4FCK
Pulse width
20 ns
15 ns
10 ns
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
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MN673276
Confidential
SPECIFICATIONS
(Preliminary)
7
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
H
6
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
5
*
*
*
*
*
*
*
*
*
*
*
*
L
H
*
*
*
CGSW2
4
3
*
*
*
*
*
*
*
*
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
*
*
*
*
*
*
*
*
*
*
2
*
*
*
*
L
H
L
H
L
H
L
H
*
*
*
*
*
1
L
L
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
0
L
H
L
H
*
*
*
*
*
*
*
*
*
*
*
*
*
7
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
6
*
*
*
*
*
*
*
*
*
*
*
*
*
*
L
H
*
*
5
*
*
*
*
*
*
*
*
*
*
*
*
L
H
*
*
*
*
CGSW3
4
3
*
*
*
*
*
*
*
*
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
*
*
*
*
*
*
*
*
*
*
*
*
2
*
*
*
*
L
H
L
H
L
H
L
H
*
*
*
*
*
*
1
L
L
H
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
L
H
L
H
*
*
*
*
*
*
*
*
*
*
*
*
*
*
7
*
*
*
*
6
*
*
*
*
5
*
*
*
*
CGSW4
4
3
*
*
*
*
*
*
*
*
2
*
*
*
*
1
*
*
L
H
0
L
H
*
*
Adjusting signal
DS1
FCK(DS1)
DS1, DS2
Adjusting signal
DS2
FCK(DS2)
DS2
DS1, DS2
Adjusting signal
DS1
DS2
Total
pages
Page
28
Setting operation
Operation
-1/2 T DLY
Coarse
-1/4 T DLY
adjustment
0T DLY
1/4 DLY
0CELL DLY
Fine
1CELL DLY
adjustment
2CELL DLY
3CELL DLY
4CELL DLY
5CELL DLY
6CELL DLY
7CELL DLY
Through
Reverse
1/4FCK
Pulse width
1/4FCK-5 ns
1/4FCK-10 ns
Setting operation
Operation
-1/2 T DLY
Coarse
-1/4 T DLY
adjustment
0T DLY
1/4 DLY
0CELL DLY
Fine
1CELL DLY
adjustment
2CELL DLY
3CELL DLY
4CELL DLY
5CELL DLY
6CELL DLY
7CELL DLY
Reverse
Through
Through
DS2=DS1
Through
Output
Reverse
Setting operation
Operation
0 ns DLY
2.6 ns DLY
0 ns DLY
2.6 ns DLY
These registers allow the phase adjustment for H1, H2, R, DS1 and DS2. However, some CCDs
require initial settings.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
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Confidential
SPECIFICATIONS
(Preliminary)
Total
pages
Page
29
Coarse adjustment
2FCK
FC K
H C LR
・M510・=MHE 5,M E 5 V ,V G A = H
C G S W 0(1 :0)= 0 h
H1
C G S W 0(1 :0)= 1 h
C G S W 0(1 :0)= 2 h
C G S W 0(1 :0)= 3 h
・M768,M510B,M768B
・S H 5 ,S O 5 ,S O 7 =
= HH
C G S W 0(1 :0)= 0 h
H1
C G S W 0(1 :0)= 1 h
C G S W 0(1 :0)= 2 h
C G S W 0(1 :0)= 3 h
C G S W 1(1 :0)= 0 h
R
C G S W 1(1 :0)= 1 h
C G S W 1(1 :0)= 2 h
C G S W 1(1 :0)= 3 h
C G S W 2(1 :0)= 0 h
D S1
C G S W 2(1 :0)= 1 h
C G S W 2(1 :0)= 2 h
C G S W 2(1 :0)= 3 h
C G S W 3(1 :0)= 0 h
D S2
C G S W 3(1 :0)= 1 h
C G S W 3(1 :0)= 2 h
C G S W 3(1 :0)= 3 h
* H2 has a waveform with a reversed polarization of H1.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
Page
30
Fine adjustment
・
Fine adjustm
adjustment
ent TYP
TYP condition
condition
・Fine
26.0 ns
20.3 ns
17.5 ns
CGSW *(4:2)=0h
CGSW *(4:2)=1h
CGSW *(4:2)=2h
CGSW *(4:2)=3h
CGSW *(4:2)=4h
CGSW *(4:2)=5h
CGSW *(4:2)=6h
CGSW *(4:2)=7h
3.8 ns 3.8 ns 3.8 ns 3.8 ns 3.8 ns 3.8 ns 3.8 ns
7.6 ns
11.4 ns
15.2 ns
19.0 ns
22.8 ns
26.6 ns
0
2
L
L
L
L
H
H
H
H
SW
1
L
L
H
H
L
L
H
H
0
L
H
L
H
L
H
L
H
1
2
3
4
6
7
DLY time [ns]
Select DLY
0unit
1unit
2unit
3unit
4unit
5unit
6unit
7unit
5
DELAY CELL
DELAY CELL
DELAY CELL
DELAY CELL
DELAY CELL
DELAY CELL
DELAY CELL
DELAY CELL
M IN
0
1.9
3.8
5.7
7.6
9.5
11.4
13.3
TYP
0
3.8
7.6
11.4
15.2
19.0
22.8
26.6
M AX
0
7.6
15.2
22.8
30.4
38.0
45.6
53.2
3.8-ns DLY
is used
for for
one one
unit.unit.
3.8-ns
DLYcell
cell
is used
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
Total
pages
Page
31
Width adjustment
2FCK
FCK
HCLR
CGSW1(7:6)=0h
CGSW1(7:6)=1h
20ns
20
ns
CGSW1(7:6)=2h
15ns
15
ns
R
CGSW1(7:6)=3h
10ns
10
ns
CGSW2(7:6)=0h,1h
DS1
CGSW2(7:6)=2h
5ns
5 ns
CGSW2(7:6)=3h
10ns
10
ns
CGSW2(7:6)=0h,1h
DS2
CGSW2(7:6)=2h
55ns
ns
CGSW2(7:6)=3h
10ns
10
ns
CPOB phase switching
Register CB
Register CC
Register CD
Register CE
ESTABLISHED
REVISED
---*****
---*****
---*****
---*****
CPST
CPSP
CPST2
CPST2
CPOB start set value
CPOB stop set value
CPOB2 start set value
CPOB2 stop set value
(0T-31T)
(0T-31T)
(0T-31T)
(0T-31T)
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
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Total
pages
Page
32
External/internal TG switch
Register C4 *------- TGOE
TG output enable signal
Setting
0
1
Description
Internal TG connected
External TG used
By setting this register to “1”, H1, H2 and R of the internal TG can be stopped when using the
externally connected TG.
Flicker setting
Register C5 ------** MODE1, 2 Normal/flickerless/electronic aperture switching
MODE
Description
1
0
2
＊
Normal: (NTSC) 1/60 s, (PAL) 1/50 s
1
0
Flickerless: (NTSC) 1/100 s, (PAL) 1/120 s
1
1
Electronic aperture: 1/60s (1/50s) to 1/100000s max.
Register C5 -----*-- CHREV
Register C5 ----*--- SUBREV
Register C5 ---*---- V1REV
Register C5 --*----- V2REV
Register C5 -*------ V3REV
Register C5 *------- V4REV
Setting
0
1
CH1 and CH2 pulse reversing process
SUB pulse reversing process
V1 pulse reversing process
V2 pulse reversing process
V3 pulse reversing process
V4 pulse reversing process
Description
Normal state (normal)
Pulse reversed
If it’s required to reverse some pulses depending on the CCD used, then set this register. By
setting this register to “1”, the polarity of the pulses are reversed.
Register C6 - - - - - ***
Register C6 ****- - - Register C7 - - ******
RHSSOS Register for setting HSSOS
RHSSO Register for setting HSSO (lower bits)
RHSSO Register for setting HSSO (upper bits)
Setting the register HSSEL to “H” in testing allows this register to set HSSOS or HSSO.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
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Confidential
SPECIFICATIONS
(Preliminary)
・ HSSEL
Page
33
HSSOS, HSSO register setting switching
Register C7 * ------- HSSEL
Setting
0
Total
pages
HSSOS, HSSO register setting switching
Description
Internal connection (normal)
1
Register setting (testing)
Setting this register to “1” allows HSSOS and HSSO to be set from the register.
・ FD
FHRST delay time switching
Register C8 ---***** FD
FHRST delay time switching
Setting
00
1F
Description
FHRST delay time (MIN)
FHRST delay time (MAX)
This register can set FHRST in accordance with the delay time on the main line. The standard delay
time is set to 10h.
・ LLSEL
LLDET system switching
Register C8 --*----- LLSEL
Setting
0
LLDET system switching
Description
Conventional system
1
Simplified system
Setting this register to “1” can generate pulses with a simple processing not with the conventional
complex pre-processing. (Test circuit to study the system).
・ VDSEL
VD select signal
Register C8 -*------ VDSEL
VD select signal
Setting
Description
0
Outputs CSYNC
1
Outputs VD
The CSYNC/VD output pin normally outputs CSYNC. Setting this register to “1” outputs to VD.
・ INT
Processing when VCO is not required
Register C8 *------- INT Processing when VCO is not required
Setting
Description
0
With VCO
1
Without VCO
Setting this register to “1” forces the crystal oscillation mode to be operated irrespective of the
availability of the external synchronization.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
Register C9
Register CA
******** HP
******** HP2
Total
pages
34
H phase fine adjustment when SYNC is synchronized
H phase fine adjustment when HDVD is synchronized
Setting
Description
00
H phase adjustment for HDVD/SYNC synchronized (MIN)
H phase adjustment for HDVD/SYNC synchronized (MAX)
FF
Page
The external SYNC signal is separated by the SYNC separation circuit. Since this causes a delay,
correction is carried out before the signal is applied to the phase comparator. For adjustments,
80h is defined as standard.
・ External Pin LLDET LL synchronized switching input
Setting
Description
0
LL synchronization OFF
1
LL synchronization ON
By setting this register, the drive signal corresponding to each mode is output. The MODE shown
here is the CCD select signal output to be used by TG.
・ External Pin NP
Setting
0
NTSC system
1
PAL system
NTSC/PAL switching pin
Description
This pin allows the color TV system, NTSC or PAL, to be switched.
・ External Pin REV/DS2 left-right reverse switching pin
(Register switching, REV as default)
Setting
Description
0
Normal
1
Reversed
This pin allows the picture to be reversed left-right. However, this pin can be switched, using the
F2 register, to the function of monitoring the DS2 output by the internal register. The REV input
is default setting.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
・ External pin CCDSEL0 – 2
Setting
NP
CCDSEL
2 1 0
0 0 0
0
1
0
1
0
1
―――
0
1
0
0
M768
1
0
1
1
1
0
0
1
0
1
Description
510 pixels MN39110 series, MN39116 (NTSC)
510 pixels MN39210 series, MN39216 (PAL)
0
0
35
CCD switching pin
MODE
M510
Page
M510B
M768B
768 pixels MN39143 (NTSC) 1/3 type
768 pixels MN39243 (PAL) 1/3 type
510 pixels (NTSC)
510 pixels (PAL)
768 pixels (NTSC)
768 pixels (PAL)
By setting this register, the drive signal corresponding to each mode is output.
The MODE shown here is the CCD select signal output to be used by TG.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
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MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
Internal connection
Internal connection
Internal connection
- - - - ****
********
-------*
HSSO0-3
HSSOS0-7
HSSOS8-9
Page
36
Electronic shutter setting (SUB pulse)
Electronic shutter setting (SUB pulse)
Electronic shutter setting (SUB pulse)
WHD
SUB
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
A
TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP
SUB
position
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Data setting
HSH(8:0) HSL3 HSL2 HSL1 HSL0
606fh
＊
0
0
0
0 TA 38T
0
0
0
1 TB 38T
＊
＊
0
0
1
0 TC 38T
＊
0
0
1
1 TD 38T
＊
0
1
0
0 TE 38T
＊
0
1
0
1
TF 38T
＊
0
1
1
0 TG 38T
＊
0
1
1
1 TH 37T
1
0
0
0
TI 38T
＊
＊
1
0
0
1
TJ 38T
＊
1
0
1
0 TK 38T
＊
1
0
1
1 TL 38T
＊
1
1
0
0 TM 38T
1
1
0
1 TN 38T
＊
＊
1
1
1
0 TO 38T
＊
1
1
1
1
TP 37T
Timing
618fh 780fh
39T 49T
39T 49T
39T 49T
38T 48T
39T 49T
38T 49T
39T 49T
38T 48T
39T 49T
39T 49T
39T 49T
38T 48T
39T 49T
38T 49T
39T 49T
38T 48T
910fh
57T
57T
57T
57T
57T
57T
57T
56T
57T
57T
57T
57T
57T
57T
57T
56T
Remarks
908fh
57T VBLK period
57T
57T
56T
57T
57T
57T
56T
57T
57T
57T
56T
57T
57T
57T
56T
Electric charge accumulation time is as follows.
NTSC: (261 - HSH(8:0))H (where 0 < n ≤ 260）
For n=0, 262 or 263H
PAL:
ESTABLISHED
(311 - HSH(8:0))H (where 0 < n ≤ 310)
For n=0, 312 or 313H
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
8.
Total
pages
Page
37
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Pin name
CDSOUT
VOBDAT
AGCOUT
AGCVSS
VCLDAT
AGCVDD
CDSVDD
VFSIG
VSSIG
CDSVSS
11
REV/DS2
12
I/O
O
O
O
VSS
O
VDD
VDD
I
I
VSS
Description
CDS output (for control of ALC lens)
Output OB level stabilization pin
Grounded via C.
AGC output
Ground for AGC block
Input DC level stabilization pin
Grounded via C.
AGC block power supply 3.0 V
CDS block power supply 3.0 V
CDS IN
CDS IN
Ground for CDS block
Left-right reverse switching, H: reversed, L: normal / CDS sampling pulse output
(register switching, REV as default)
BLC switch, L: OFF, H: ON / CDS sampling pulse output (register switching,
BLCSW as default)
I
O Electric charge read pulse for V1
O Electric charge read pulse for V3
O Reset pulse output for the electronic shutter board
VDD Logic block power supply 1 2.0 V
VSS Ground for logic block, I/O block
VDD I/O block power supply 1 3.3 V
I/O Serial data
I/O Serial clock
I
13
14
15
16
17
18
19
20
BLCSW/DS1
CH1
CH2
SUB
VDD1
VSS1
VDDIO1
SDA
SCL
21
COIN
22
23
24
25
26
27
28
29
30
31
NTPL
CCDSEL0
CCDSEL1
CCDSEL2
TGVDD
TGIOVSS
RR
TGIOVDD
H2
H1
I
I
I
I
VDD
VSS
O
VDD
O
O
NTSC/PAL switch, L: NTSC, H: PAL
CCD select
CCD select
CCD select
TG logic block power supply 2.0 V
Ground for I/O block, logic block of TG
Reset pulse output
Power supply 3.3 V for I/O block of TG
φ H2 horizontal register transfer clock
φ H1 horizontal register transfer clock
32
33
34
35
36
OSCCNT
CXIN
CXOUT
OSCVDD
OSCVSS
O
I
O
VDD
VSS
LC oscillation control
Hi-Z in the LL mode or Low-Z, otherwise
Oscillation input
Oscillation output
Oscillation block power supply 3.3 V
Ground for oscillation block
ESTABLISHED
I
REVISED
Oscillation input (LC)
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Pin name
TEST0
TEST1
TEST2
TEST3
TEST4
I/O
I
I
I
I
I
Total
pages
Page
38
Description
Test mode setting (Normally, use at Low setting.)
Test mode setting (Normally, use at Low setting.)
Test mode setting (Normally, use at Low setting.)
Test mode setting (Normally, use at Low setting.)
Test mode setting (Normally, use at Low setting.)
V1
O φ V1 vertical register transfer clock
V2
O φ V2 vertical register transfer clock
V3
O φ V3 vertical register transfer clock
V4
O φ V4 vertical register transfer clock
VDDIO2
VDD I/O block power supply 2 3.3 V
VSS2
VSS Ground for logic block, I/O block
VDD2
VDD Logic block power supply 2 2.0 V
FWHD
O FWHD output
CPOB/HCLR
O CPOB/HCLR/FVD/CPOB2 output (register switching, CPOB as default)
/FVD/CPOB2
PBLK/CBLK
O PBLK/CBLK/WHD output (register switching, PBLK as default)
/WHD
CSYNC
O CSYNC output
EXTMOD
I
Monitor/vehicle mounting mode switch, L: monitor, H: vehicle mounting
FLC
I
Flickerless mode (gain correction), L: OFF, H: ON
External synchronization input pin, monitor mode: LP, vehicle mounting mode:
EXTIN0
I
CSYNC/HD
EXTIN1
I
External synchronization input pin, monitor mode: VD2, vehicle mounting mode: VD
LLDET
I
INT/LL switch, L: INT synchronization, H: LL synchronization
ALCELC
I
ALC/ELC switch, L: ELC, H: ALC
APGAIN
I
AP gain switch, L: sharp, H: soft (APGAIN = 0)
ATWLOCK
I
ATW lock, L: normal operation, H: lock
SCANT
I
Scanning test (Normally, use at Low setting.)
MINTEST
I
MINTEST (Normally, use at Low setting.)
VDDIO3
VDD I/O block power supply 3 3.3 V
VOUT2
Regulator output pin outputting 2.0 V
VSS3
VSS Ground for logic block, I/O block
VDD3
VDD Logic block power supply 3 2.0 V
RESET
I
Power-ON reset input
PWM0
O PWM output, ch 0
PWM1
O PWM output, ch 1
PWM2
O PWM output, ch 2
PWM3/FCK
O PWM output, ch 3/FCKO/F2CKO output (register switching, PWM as default)
O/F2CKO
PCO1
O Phase comparator output (for crystal oscillation)
PCO2
O Phase comparator output (for LC oscillation)
AREAPULS
O BLC frame pulse output
IRIS
O ALC DC control
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
Pin No.
Pin name
76
VCXO
77
FVR
Total
pages
Page
39
78
LPFI
79
80
81
82
83
84
85
86
87
88
89
90
91
RSIG
DAVDD2
DAVSS2
BSIG
COMP23
IREF23
VREF23
DAVDD1
DAVSS1
GSIG
COMP1
IREF1
VREF1
I/O
Description
O Analog SW output
I VCXO control voltage input (analog SW input, DC input for frequency adjustment for
INT or LL)
I VCXO control voltage input (analog SW input, monitor: V LPF, vehicle mounting: H
LPF)
O R output
VDD DA23 power supply 3.0 V
VSS Ground for DA23
O C/B output
I Pin for phase correction
Connects C across DAVDD2
I Resistor pin for setting bias current
I Reference voltage input pin
VDD DA1 power supply 3.0 V
VSS Ground for DA1
O Composite/Y/G output
I Pin for phase correction
Connects C across DAVDD1
I Resistance pin for setting bias current
I Reference voltage input pin
92
93
94
95
96
97
98
99
100
VREFH
VREFM
VREFL
TADIN
ADVSS
ADVDD
VREFLO
VREFHO
CDSDAT
I
I
I
I
VSS
VDD
O
O
O
ESTABLISHED
REVISED
AD reference power supply VRT input
AD reference power supply VRM input
AD reference power supply VRB input
AD Input
Ground for AD
AD power supply 2.0 V
AD reference power supply VRB output
AD reference power supply VRT output
OB & AGC control DAC output (VDACOB, VDACGAIN)
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
(Preliminary)
9.
Total
pages
Page
40
Pin Assignment
Please refer to the evaluation board circuit diagram.
Figure 2 Pin assignment
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
Total
pages
Page
41
10. Timing Chart
•
VD2 synchronization
Aprox . 3 µ s
V D2
C .SY NC
1.47 µ s
•
LL synchronization (power supply synchronization)
1V
EIA 60 H z D uty Approx. 50%
LP
CCIR 50 Hz D uty Approx. 50%
T he falling edge is reference edge.
C.SYN C
Phase is adjusted externally
•
V.SYNC
Phase is adjusted externally by
mono-multi type.
SYNC synchronization
GLSYNC
GLSYNC
C.SYNC
C.SYNC
HHLOCK
phase
LOCK位相
•
ＶリセットＩＮ
V
reset IN
HDVD synchronization
SYNC
SYNC
HD
HD
VD
VD
HH LOCK
phase
LOCK位相
ESTABLISHED
REVISED
9H(NTSC)
9H(NTSC)
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
SPECIFICATIONS
Total
pages
ESTABLISHED
42
EVEN
EVEN
34
34
Page
REVISED
20H(MECは21H)
20H
(21H for MEC)
VBLK
CBLK
BF
VD
VP
HS
519
EQ
525 0
VS
3H
9H
6
EQ
20H(MECは21H)+11μS
20H (21H for MEC) + 11µs
12
HS
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
524
523
522
521
520
519
518
517
516
515
514
513
SYNC
SSG部タイミングＶレート(NTSC)
SSG block timing V rate (NTSC)
39
38
37
36
35
34
33
32
31
30
ODD
EVEN
ODD
ODD
EVEN
(Preliminary)
ODD
Confidential
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
SPECIFICATIONS
Total
pages
ESTABLISHED
①③
43
45
②④
②④
45
Page
REVISED
25H
VBLK
CBLK
BF
VD
VP
HS
620
EQ
625 0
VS
2.5H
7.5H
25H+12.0 µs
5
EQ
10
HS
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
624
623
622
621
620
619
618
617
616
615
614
613
SYNC
SSG block timing V rate (PAL)
SSG部タイミングＶレート(PAL)
51
50
49
48
47
46
45
44
43
42
④
③
②
①
①∼④
①∼④
②④
①③
(Preliminary)
①③
Confidential
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
EBF
4.72
561T
4.72
1.57
45T
0T(606T)
591T
XT
4.72
22T
2.31
11.01
10.07
5.35
4.72
22T
2.31
51T
45T
11.01
10.07
90T
81T
75T
2.52
90T
81T
1T=1/9.5350 MHz
=104.8772 ns
258T
4.72
1.57
288T
4.72
1.57
288T
XT
325T
2.31
258T
303T
303T
325T
2.31
［µｓ］
[µs]
※ XTはシステムディレイを示す
* XT indicates a system delay.
(Preliminary)
VSER
561T
1.57
591T
NTSC 606 fH
fH=15.7343 kHz
SPECIFICATIONS
EQ
HSYNC
VD
HBLK
WHD
(H9)
FVSER
FEQ
FHSYNC
FVD
FBLK
FWHD
(FH9)
0T(606T)
SSG block timing H rate (NTSC 510H)
SSG部タイミングＨレート(NTSC 510H)
Confidential
MN673276
Total
pages
Page
44
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
EBF
4.66
573T
4.66
1.55
45T
0T(618T)
603T
XT
4.66
22T
2.28
12.12
9.94
5.59
4.66
22T
2.28
54T
45T
12.12
9.94
102T
81T
76T
2.28
81T
102T
1T=1/9.6563 MHz
=103.5599 ns
264T
4.66
1.55
294T
4.66
1.55
294T
XT
331T
2.28
264T
309T
309T
※ XTはシステムディレイを示す
331T
2.28
［µｓ］
[µs]
* XT indicates a system delay.
(Preliminary)
VSER
573T
1.55
603T
PAL 618 fH
fH=15.625 kHz
SPECIFICATIONS
EQ
HSYNC
VD
HBLK
WHD
(H9)
FVSER
FEQ
FHSYNC
FVD
FBLK
FWHD
(FH9)
0T(618T)
SSG
block timing H rate (PAL 510H)
SSG部タイミングＨレート(PAL
510H)
Confidential
MN673276
Total
pages
Page
45
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
EBF
4.66
562T
4.66
1.55
44T
4.66
100T
5.59
53T
44T
12.12
9.94
79T
22T
2.28
0T(303T)
591T
XT
2.28
4.66
22T
12.12
9.94
75T
2.28
79T
100T
1T=1/9.4688MHz
=105.6106ns
259T
4.66
1.55
288T
4.66
1.55
288T
XT
2.28
325T
259T
303T
303T
325T
2.28
[µs]
［μｓ］
※ XTはシステムディレイを示す
* XT indicates a system delay.
(Preliminary)
VSER
562T
1.55
591T
PAL 606fH
fH=15.625KHz
SPECIFICATIONS
EQ
HSYNC
VD
HBLK
WHD
(H9)
FVSER
FEQ
FHSYNC
FVD
FBLK
FWHD
(FH9)
0T(606T)
SSG
block timing H rate (MN39217 PAL
PAL510H)
510H)
SSG部タイミングＨレート(SONY
Confidential
MN673276
Total
pages
Page
46
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
EBF
4.68
843T
4.68
1.47
67T
4.68
135T
5.31
76T
67T
10.90
9.64
117T
33T
2.31
0T(910T)
889T
XT
2.31
4.68
33T
10.90
9.64
112T
2.51
117T
135T
1T=1/14.3182MHz
=69.8413ns
388T
4.68
1.47
434T
4.68
1.47
434T
XT
2.31
488T
388T
455T
455T
488T
2.31
[µs]
［μｓ］
※ XTはシステムディレイを示す
* XT indicates a system delay.
(Preliminary)
VSER
843T
1.47
889T
NTSC 910fH
fH=15.7343KHz
SPECIFICATIONS
EQ
HSYNC
VD
HBLK
WHD
(H9)
FVSER
FEQ
FHSYNC
FVD
FBLK
FWHD
(FH9)
0T(910T)
SSG
block timing H rate (NTSC 768H)
SSG部タイミングＨレート(NTSC
768H)
Confidential
MN673276
Total
pages
Page
47
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
EBF
4.72
841T
4.72
1.55
67T
5.64
2.33
33T
80T
67T
12.05
9.80
149T
117T
4.72
0T(908T)
886T
XT
2.33
33T
4.72
12.05
9.80
2.26
112T
117T
149T
1T=1/14.1875MHz
=70.4846ns
387T
4.72
1.55
432T
4.72
1.55
432T
XT
2.33
487T
387T
454T
454T
2.33
487T
[µs]
［μｓ］
*※XTXTはシステムディレイを示す
indicates a system delay.
(Preliminary)
VSER
841T
1.55
886T
PAL 908fH
fH=15.625KHz
SPECIFICATIONS
EQ
HSYNC
VD
HBLK
WHD
(H9)
FVSER
FEQ
FHSYNC
FVD
FBLK
FWHD
(FH9)
0T(908T)
SSG block timing H rate (PAL 768H)
SSG部タイミングＨレート(PAL
768H)
Confidential
MN673276
Total
pages
Page
48
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
Page
49
!
MN39110 series: High-speed pulse timing
○MN37110シリーズ 高速パルスタイミング
F2CK
FCK
23T
77T(89T)
HCLR
21T
75T(87T)
IHCLR
22.5T
77T(89T)
H1
H2
R
DS1
DS2
CCD
output
CCD出力
!
MN39110 series: H rate timing
○MN37110シリーズ Ｈレートタイミング
606T(618T)
0T
FWHD
96T
OB
(2 bits)
OB(2bit)
Dummy
(1 bit)
ﾀﾞﾐｰ(1bit)
OB(28bit)
空送り(3bit)
OB (28 bits)
Idle feed (3 bits)
CCD
output
CCD出力
H1
H2
10T
ﾀﾞﾐｰ(6bit)
Dummy
(6 bits)
有効512bit
Valid 512 bits
22.5T
77T(89T)
22.5T
77T(89T)
23T
77T(89T)
HCLR
CPOB
(Enlarged
view of section B)
（Ｂ部分拡大）
16T
CPSW(1:0)=0h
85T(96T)
0T
PBLK
50T
35T
V1
45T
V2
30T
V3
55T
40T
V4
47T
SUB
60T
65T
67T
77T(89T)
FH2
L fixed
Ｌ固定
FH4
Note) ・1=1/FCK(NTSC:104.88ns,PAL:103.56)。
" 1 = 1/FCK (NTSC: 104.8 ns, PAL: 103.56 ns)
（注）
" OT represents the rising edge of FWHD.
・0TはFWHDの立ち上がり。
" ( ) for PAL
" V1, V2, V3, V4 and SUB are reversed by the V driver and input to CCD.
・（）内はＰＡＬ時。
・Ｖ１、Ｖ２、Ｖ３、Ｖ４、ＳＵＢはＶドライバで反転されて
ＣＣＤに入力する。
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
30T
40T
35T
30T
40T
50T
2T
32T
22.5T
23T
42T
77T
77T
72T
77T(89T)
77T(89T)
22.5T
23T
55T
65T
60T
65T
60T
55T
50T
45T
40T
35T
77T(89T)
77T(89T)
Total
pages
V4*
V3*
50T
77T(89T)
22.5T
35T
77T(89T)
23T
0T
= 104.88 ns: NTSC, 103.56 ns: PAL
" 1T
・1T=104.88ns:NTSC,103.56ns:PAL
) for PAL
" (・（）内はＰＡＬ時
・＊はＶドライバで反転する。
" ∗ is reversed by the V driver.
0T
(Preliminary)
V2*
0T
(Enlarged view of section A)
（Ａ部分拡大）
SPECIFICATIONS
V1*
[ Field B ]
［Ｂフィールド］
V4*
V3*
V2*
V1*
[ Field A ]
［Ａフィールド］
CH2*
CH1*
H2
H1
HCLR
FWHD
!
MN39110 series: Timing in detail
○MN37110シリーズ 詳細タイミング
Confidential
MN673276
Page
50
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
ＨＣＬＲ
Ａ
1
2
3
4
HSSO(9:0)=1h時
When
HSSO (9:0) = 1h
5
6
Total
pages
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
は高速シャッタ動作期間
is
the high-speed shutter operating period.
OB
(Preliminary)
Ｈ１
Ｂ
490 492
491 OB
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
CCD出力
CCD
output
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
・ＳＵＢはシャッタ時のみ。
" SUB for shutter only
・＊はＶドライバで反転する。
" ∗ is reversed by the V driver.
513514515516517518519520521522523524525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
NTSC-A
field
ＮＴＳＣ−Ａフィールド
! MN39110
series: V rate timing
○MN37110シリーズ Ｖレートタイミング
Confidential
MN673276
Page
51
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
Ａ
2
3
6
7
HSSO(9:0)=1h時
When
HSSO (9:0) = 1h
4
5
Total
pages
ＨＣＬＲ
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
isは高速シャッタ動作期間
the high-speed shutter operating period.
OB
1
(Preliminary)
Ｈ１
Ｂ
489 491 OB
490 492
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
CCD出力
CCD
output
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
・ＳＵＢはシャッタ時のみ。
" SUB for shutter only
・＊はＶドライバで反転する。
" ∗ is reversed by the V driver.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289
ＮＴＳＣ−Ｂフィールド
NTSC-B
field
○MN37110シリーズ Ｖレートタイミング
! MN39110
series: V rate timing
Confidential
MN673276
Page
52
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
Ａ
1
2
3
4
When
HSSO (9:0) =1h
HSSO(9:0)=1h時
5
6
Total
pages
ＨＣＬＲ
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
は高速シャッタ動作期間
is
the high-speed shutter operating period.
OB
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
(Preliminary)
Ｈ１
Ｂ
580 582
581 OB
4 5 6 7 8
" ∗ is reversed by the V driver.
・ＳＵＢはシャッタ時のみ。
" SUB for shutter only
・＊はＶドライバで反転する。
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
CCD出力
CCD
output
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
613614615616617618619620621622623624625 1 2 3
ＰＡＬ−Ａフィールド
PAL-A
field
○MN37110シリーズ Ｖレートタイミング
! MN39110
series: V rate timing
Confidential
MN673276
Page
53
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
Ａ
2
3
4
5
When
HSSO (9:0) = 1h
HSSO(9:0)=1h時
6
7
Total
pages
ＨＣＬＲ
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
isは高速シャッタ動作期間
the high-speed shutter operating period.
OB
1
(Preliminary)
Ｈ１
Ｂ
579 581 OB
580 582
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
Output
出力
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
" SUB for shutter only
・ＳＵＢはシャッタ時のみ。
・＊はＶドライバで反転する。
" ∗ is reversed by the V driver.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340
PAL-B
field
ＰＡＬ−Ｂフィールド
! MN39110
series: V rate timing
○MN37110シリーズ Ｖレートタイミング
Confidential
MN673276
Page
54
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
616T
578T (10T)
47T
85T
123T
161T
199T
237T
275T
SUB
CH1
FWHD
313T
350T
388T
426T
464T
502T
540T
616T
578T (10T)
0T(606T)
47T
85T
123T
161T
199T
237T
275T
313T
350T
388T
426T
464T
502T
588T
627T
(9T)
47T
86T
125T
164T
202T
241T
279T
318T
356T
395T
434T
473T
511T
550T
588T
627T
(9T)
0T(618T)
47T
86T
125T
164T
202T
241T
279T
318T
356T
395T
434T
473T
511T
39T
38T
39T
39T
39T
38T
39T
38T
39T
38T
39T
39T
39T
38T
39T
38T
39T
38T
39T
39T
39T
38T
39T
38T
39T
38T
39T
39T
39T
38T
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
３１２または３１３
3
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
2
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
HSSOS(3:0)
1
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
32T
Max. shutter speed
2T
最高速シャッタスピード
1/108460 s
1/108460s
89T
9.22μs
9.22 µs
0T(618T)
In上記条件に加えて
addition to the condition mentioned above:
CH1パルスの直前の１水平走査期間のみN∼Pのパルスが指定された場合、Mの位置にパルスを発生さ
If pulses N through P are specified only in one horizontal scanning period immediately before the
せる。
CH1 pulse, a pulse is generated at position M.
HSSO(9:0)で指定された水平ﾀｲﾐﾝｸﾞまで有効期間内、VBLK内共毎Ｈ出力。
Output
every H both within the valid period and VBLK until the horizontal timing specified by HSSO(9:0).
HSSO(9:0)で指定されたAパルスに引き続く１水平操作期間内であり、且つそのラインがCH1が印可
Only
one pulse specified by HSSOS(3:0) in B through P is output if it falls in one horizontal operating period
immediately
following pulse A specified by HSSO(9:0) and the line falls in VBLK before CH1 is applied.
されるまでのVBLK内であればB∼Pの内のHSSOS(3:0)で指定される１パルスのみを出力する。
動作条件
Operating
condition
32T
(Preliminary)
ＰＡＬ：（３１１−ｎ）Ｈ
PAL:
(311 – n)H
（但し、０＜ｎ≦３１０）
(where
0 < n ≤ 310)
ｎ＝０では、
For
n = 0, 312 or 313
4
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
2T
Max. shutter speed
最高速シャッタスピード
1/110865 s
1/110865s
86T
86T
9.02
µs
9.02μs
0T(606T)
SPECIFICATIONS
（但し、０＜ｎ≦２６０）
NTSC:
(261 – n)H
ｎ＝０では、
(where
0 < n ≤ 260)
２６２または２６３
For
n = 0, 262 or 263
ＮＴＳＣ：（２６１−ｎ）Ｈ
Ifｎ＝HSSO(9:0)と定義すれ
defined as n = HSSO(9:0),
ば、電荷蓄積時間は、次式で
the
electric charge
定義される。
accumulation
time is defined
by the following equation:
HSSO(9:0)
20T
20T
2.07μs
2 .07 µs
3.99μs
3.99μs
3.99
µs 3.99
µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs
38T
N O P A B C D E F G H I J K L M N O P A B C D E F G H I J K L M
550T
0T(618T)
20T
20T
22.10μs
.10 µs
38T
38T
37T
38T
38T
38T
38T
38T
38T
38T
37T
38T
38T
38T
38T
38T
38T
38T
37T
38T
38T
38T
38T
38T
38T
38T
37T
38T
38T
38T
38T
3.99 µs3.99
µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99
µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.88μs
3.88 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99μs
3.99 µs 3.99
3.99μs
3.99μs
3.99μs
3.99μs
µs
N O P A B C D E F G H I J K L M N O P A B C D E F G H I J K L M
540T
0T(606T)
[ PAL mode: 1T=1/FCK=103.56 ns ]
［ＰＡＬモード:1T=1/FCK=103.56ns］
SUB
CH1
FWHD
[ NTSC mode: 1T=1/FCK=104.88 ns ]
［ＮＴＳＣモード:1T=1/FCK=104.88ns］
!
MN39110 series: Electronic aperture SUB pulse timing chart (high-speed mode)
○MN37110シリーズ 電子絞りＳＵＢパルス タイミング図（高速モード）
Confidential
MN673276
Total
pages
Page
55
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
Page
56
! MEC 1/3 type 768H CCD high-speed pulse timing
○MEC 1/3型 768H CCD 高速パルスタイミング
CLKCG
FCK
122T(138T)
HCLR
IHCLR
41T
120T(136T)
39T
40.5T
122T(138T)
H1
H2
R
DS1
DS2
CCD
output
CCD出力
(Enlarged view of section B)
（Ｂ部分拡大）
!
MEC1/3型
1/3 type 768H
768H CCD
H rate timing
○MEC
CCD Ｈレートタイミング
910T(908T)
0T
FWHD
CCD
output
CCD出力
138T(139T)
OB
bits)
OB(2(2 bit)
Valid
771 bit:N
bits: N
有効771
Dummy
bits)
ﾀﾞﾐｰ(6(6bit)
753 bit:P
bits: P
753
OB(43
bit)
OB (43
bits)
H1
H2
40.5T
122T(138T)
40.5T
122T(138T)
41T
122T(138T)
HCLR
CPOB
PBLK
21T
30T
CPSW(1:0)=0h
0T
128T(142T)
44T(46T)
V1
62T(68T)
V2
35T
V3
89T(101T)
80T(90T)
53T(57T)
V4
98T(112T)
80T(90T)
SUB
106T(120T)
122T(138T)
FH2
FH4
71T(79T)
L fixed
Ｌ固定
(Note)
" 1T=1/FCK
(69.8 ns: NTSC,
70.4 ns: PAL) ns:PAL)。
（注）
・1T=1/FCK(69.8
ns:NTSC,70.4
" 0T ・0TはFWHDの立ち上がり。
is the rising edge of FWHD.
・（）内はＰＡＬ時。
" ( ) for
PAL
・Ｖ１、Ｖ２、Ｖ３、Ｖ４、ＳＵＢはＶドライバで反転されて
" V1, V2,
V3, V4 and SUB are reversed by the V driver and input to CCD.
ＣＣＤに入力する。
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
112.5T(126.5T)
35T
53T(57T)
35T
62T(68T)
44T(46T)
53T(57T)
35T
62T(68T)
98T(112T)
80T(90T)
89T(101T)
71T(79T)
582T
578T
748T
748T
712T
53T(57T)
62T(68T)
44T(46T)
98T(112T)
80T(90T)
89T(101T)
98T(112T)
80T(90T)
89T(101T)
71T(79T)
Total
pages
V4*
V3*
V2*
44T(46T)
582T
578T
676T
642T
112.5T(126.5T)
112T(126T)
(Preliminary)
V1*
98T(112T)
80T(90T)
89T(101T)
606T
35T
35T
" 1T=1/FCK=69.8 ns:
NTSC, 70.4 ns:
PAL
・1T=1/FCK=69.8
ns:NTSC,70.4
ns:PAL
・（）はＰＡＬ時
" ( ) for PAL
・＊はＶドライバで反転する。
" ∗ is reversed by the V driver.
SPECIFICATIONS
[ [Bフィールド]
Field B ]
V4*
V3*
V2*
V1*
71T(79T)
112T(126T)
35T
[ [Aフィールド]
Field A ]
CH2*
CH1*
H2
H1
HCLR
FWHD
of section A)
! MEC
1/3 type
768H768H
CCDCCD
V rate
timing in detail (Enlarged view
（Ａ部分拡大）
○MEC
1/3型
Ｖレート詳細タイミング
Confidential
MN673276
Page
57
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
ＨＣＬＲ
8
Ｂ
Ａ
4
3
is the high-speed shutter
は高速シャッタ動作期間
operating period.
2
1
6
5
When
HSSO (9:0) = 1h
HSSO(9:0)=1h時
8
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Total
pages
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
7
(Preliminary)
Ｈ１
6
OB
5
Dummy
4
491 OB
3
490 492
2
"・SUB
for
shutter
ＳＵＢ
はシ
ャ ッ タonly
時のみ。
"・∗＊isはreversed
byでthe
Vすdriver.
Ｖドライバ
反転
る。
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
CCD
output
CCD出 力
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
513514515516517518519520521522 523524525 1
NTSC-A
Ｎ Ｔ Ｓ Ｃfield
−Ａフィールド
! MEC
1/3 type 768H CCD V rate timing
○ MEC 1/3型 768H CCD Ｖ レ ー ト タ イ ミ ン グ
Confidential
MN673276
Page
58
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
ＨＣＬＲ
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Ａ
3
2
is the high-speed shutter
は 高 速 シ period.
ャッタ動作期間
operating
1
Ｂ
OB
492
Dummy
491 OB
5
4
7
6
When
HSSO (9:0) = 1h
HSSO(9:0)=1h時
Total
pages
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
3
(Preliminary)
Ｈ１
2
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
CCD
output
CCD出 力
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
1
・＊はＶドライバで反転する。
250251252253254255256257258259 260261262263 264 265266267268269270271272273274275276 277278279280281282283284285 286287288289
NTSC-B
Ｎ Ｔ Ｓ Ｃfield
−Ｂフィールド
!○
MEC
1/3 type 768H CCD V rate timing
MEC 1/3型 768H CCD Ｖ レ ー ト タ イ ミ ン グ
" SUB for shutter only
" ∗ is reversed by the V driver.
・ＳＵＢはシャッタ時のみ。
Confidential
MN673276
Page
59
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
ＨＣＬＲ
6
7
8
は
高速シャ
ッタ動作期間
operating
period.
Ａ
OB
Ｂ
Dummy
581 OB
2
1
5
6
7
8
When
HSSO (9:0) = 1h
HSSO(9:0)=1h時
4
3
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Total
pages
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
5
(Preliminary)
Ｈ１
4
is the high-speed shutter
3
580 582
2
"Ｓ
SUB
shutter
・
Ｕ Ｂfor
はシ
ャ ッ タonly
時のみ。
"＊
∗ is
reversed
byでthe
Vすdriver.
・
はＶ
ドライバ
反転
る。
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
CCD
output
CCD出 力
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
613614615616617618619620621622623624625 1
PAL-A field
! MEC 1/3 type 768H CCD V rate timing
Confidential
MN673276
Page
60
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
ＨＣＬＲ
6
7
Ａ
OB
ﾀﾞﾐｰ
Dummy
1
2
3
4
7
8
When
HSSO (9:0) = 1h
HSSO(9:0)=1h時
5
6
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Total
pages
ＣＰＯＢ
ＰＢＬＫ
Ｈ２
5
is the high-speed shutter
は高速シャッタ動作期間
operating
period.
4
(Preliminary)
Ｈ１
Ｂ
580 582
581 OB
2 3
" SUB for shutter only
・ＳＵＢはシャッタ時のみ。
・＊はＶドライバで反転する。
" ∗ is reversed by the V driver.
SPECIFICATIONS
ＦＨ４
ＦＨ２
ＳＵＢ*
ＣＨ２*
ＣＨ１*
Ｖ４*
Ｖ３*
Ｖ２*
Ｖ１*
CCD
output
CCD出力
ＦＶＤ
ＦＷＨＤ
ＣＢＬＫ
613614615616617618619620621622623624625 1
ＰＡＬ−Ａフィールド
PAL-B
field
! MEC
type 768H
V rate timing
○MEC 1/31/3型
768HCCD
CCD Ｖレートタイミング
Confidential
MN673276
Page
61
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
3. 98 μs
57 T
N
820T
56 T
57 T
A
80T
SUB
CH1
FWHD
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
56 T
2
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
606T
145T
10.2 μ s
642T
Max. shutter speed
最高速シャッタスピード
1/98039 s
0T(908T)
Max. shutter speed
最高速シャッタスピード
1/90909 s
Operating
動 作condition
条件
1
L Output every H both within the valid period and VBLK until the horizontal timing specified by HSSO(9:0).
H Only one pulse specified by HSSOS(3:0) in B through P is output if it falls in one horizontal operating period
L immediately following pulse A specified by HSSO(9:0) and the line falls in VBLK before CH1 is applied.
H
L
H
L
H In addition to the condition mentioned above:
L If pulses H through P are specified only in one horizontal scanning period immediately before the
H CH1 pulse, a pulse is generated at position G.
L
H
L
H
L
H
2. 11 μs
30 T
G
431T
3. 98 μs
57 T
F
374T
3. 98 μs
57 T
E
317T
3. 91 μs
56 T
D
261T
3. 98 μs
57 T
C
204T
3. 98 μs
57 T
B
147T
3. 98 μs
57 T
A
90T
1. 81 μs
26 T
G
422T
3. 98 μs
57 T
F
365T
3. 98 μs
57 T
E
308T
3. 98 μs
57 T
D
251T
3. 98 μs
57 T
C
194T
3. 98 μs
57 T
B
137T
3. 98 μs
57 T
A
80T
642T
(Preliminary)
PAL: (311 – n)H
(where 0 < n ≤ 310)
For n = 0, 312 or 313
3
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
HSSOS(3:0)
3. 91 μs
56 T
P
942T
(34T)
3. 98 μs
57 T
O
885T
3. 98 μs
57 T
N
828T
3. 98 μs
57 T
M
771T
0T(908T)
3. 91 μs
56 T
P
606T
158T
11.0 μ s
0T(910T)
SPECIFICATIONS
NTSC: (261 – n)H
(where 0 < n ≤ 260)
For n = 0, 262 or 263
If defined as n = HSSO(9:0),
the electric charge
accumulation time is defined
by the following equation:
4
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
3. 91μ s
56 T
L
715T
3. 98 μs
57 T
K
658T
3. 98 μs
57 T
J
601T
3. 98 μs
57 T
I
544T
3. 91 μs
56 T
H
488T
3. 98 μs
57 T
G
431T
3. 98 μs
57 T
F
374T
3. 98 μs
57 T
E
317T
3. 91 μs
56 T
D
261T
3. 98 μs
57 T
C
204T
3. 98 μs
57 T
B
147T
3. 98 μs
57 T
A
90T
HSSO(9:0)
3. 91 μs
57 T
3. 98 μs
57 T
3. 98 μs
942T
(34T)
P
885T
O
N
828T
0T(908T)
3. 98 μs
57 T
O
934T
(24T)
0T(910T)
877T
3. 98 μs
57 T
N
820T
3. 98 μs
57 T
M
763T
3. 98 μs
57 T
L
706T
3. 98 μs
57 T
K
649T
3. 98 μs
57 T
J
592T
3. 98 μs
57 T
I
535T
3. 91 μs
56 T
H
479T
3. 98 μs
57 T
G
422T
3. 98 μs
57 T
F
365T
3. 98 μs
57 T
E
308T
3. 98 μs
57 T
D
251T
3. 98 μs
57 T
C
194T
3. 98 μs
57 T
B
137T
3. 91 μs 3. 98 μs
57 T
3. 98 μs
P
934T
(24T)
O
877T
0T(910T)
PAL
ns ]
［[ Ｐ
Ａ mode:
Ｌ モ ー1T=1/FCK=70.4
ド :1T=1/2FCK=70.4ns］
SUB
CH1
FWHD
NTSC
1T=1/FCK=69.8
ns ]
［[ Ｎ
Ｔ Ｓmode:
Ｃモー
ド :1T=1/FCK=69.8ns］
!
MEC 1/3 type 768H CCD: Electronic aperture SUB pulse timing chart (high-speed mode)
○ MEC 1/3型 768H CCD 電 子 絞 り Ｓ Ｕ Ｂ パ ル ス タ イ ミ ン グ 図 （ 高 速 モ ー ド ）
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11.
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63
Application Examples
11.1 System configuration examples
(1) Configuration A
(minimum configuration)
! Internal synchronization
! Composit output
Color
CCD
(2) Configuration B
! Internal
synchronization
! RGB output
EEPROM
75 Ω
driver
ＭＮ６７３２７６
～
V driver
Color
CCD
EEPROM
ＭＮ６７３２７６
V driver
EEPROM
75 Ω
driver
G
75 Ω
driver
B
EEPROM
LL pulse
ＭＮ６７３２７６
YC
mixing
V driver
Analog
SW
R
(4) Configuration D
! Internal synchronization
! Y output
(3) Configuration C
(Monitor camera)
! External
synchronization
! YC output
Color
CCD
75 Ω
driver
VCXO
75 Ω
driver
VD2
separation
B/W
CCD
ＭＮ６７３２７６
～
75 Ω
driver
V driver
VCO
11.2 Reset
It is recommended to use an exclusive reset IC to reset the system securely when the power is
turned ON/OFF.
3.3 V
MN673276
Reset circuit
Reset
75
ＭＮ１３８２１Ｊ
Design the rank of the reset IC taking the allowance
of the system into consideration.
ESTABLISHED
REVISED
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11.3 Power supply and grounding
The power supply pins are isolated from one another as listed below to prevent noise from being
induced inside the LSI.
When connecting a power supply on a board, it is recommended to isolate the blocks from one
another using LC filters as shown below.
The figure shows a diagram in which a 3.3 V power supply is used.
Name
VDDIO1-3
TGIOVDD
OSCVDD
DAVDD1-2
CDSVDD
AGCVDD
Power supply (3. 3 V)
Logic block (IO)
CG(IO)
Oscillation pin (IO)
DAC＋AnaSW
Analog CDS
Analog AGC
Name
VDD1-3
TGVDD
ADVDD
Power supply (2. 0 V)
Logic block (internal)
CG (internal)
ADC
Logic block
3.3 Ｖ
ＶＤＤＩＯ１～３
ＶＳＳ１～３
TG block
ＴＧＩＯＶＤＤ
Oscillation block
ＯＳＣＶＤＤ
ＯＳＣＶＳＳ
DAC block
ＤＡＶＤＤ１～２
ＤＡＶＳＳ１～２
CDS block
ＣＤＳＶＤＤ
ＣＤＳＶＳＳ
AGC block
ＡＧＣＶＤＤ
ＡＧＣＶＳＳ
* If a large power supply noise is generated in the TG block, a fixed pattern noise may be
generated in the CCD. Therefore, it is recommended to reserve an entire internal layer of a
multi-layer board for grounding.
ESTABLISHED
REVISED
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11.4 ADC reference voltage pin
MN673276
TADIN
95
Analog signal input (TADIN)
Reference voltage low level (VREFL)
VREFL 94
10-bit ADC
VREFM
VREFH
93
92
Reference voltage high level (VREFH)
VREFL
VREFH
Min.
Typ.
ADVSS
0.5
2.0
Max.
Unit
V
ADVDD
V
The dynamic range of the input signal is determined by VREFH – VREFL. It is recommended to
use it with a minimum of 1.5 V [P-P].
The direct current resistance across VREFH and VREFL is 240 Ω to 740 Ω. Design the power
supply so that its impedance is low enough not to cause voltage variations.
The maximum conversion speed of the A/D converter built in this LSI is 20 MSPS.
ESTABLISHED
REVISED
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GOUT
ROUT
BOUT
11.5 DAC reference voltage pin
VREF23
85
IREF23
84
COMP23
83
BSIG
82
DAVSS2
81
DAVDD2
80
RSIG
79
VREF1
91
IREF1
90
COMP1
89
GSIG
88
DAVSS1
87
DAVDD1
86
RIREF(R/B)
C
RL(B)
MN673276
RL(R)
RIREF(G)
C
RL(G)
R1
R2
R4
0.01 µF
R3
! Fit a capacitor of approx. 1 µF at COMP.
0.01 µF
! With RL = 120 Ω and RIREF = 4.7 kΩ, adjust R1/R2 and R3/R4 so that the desired amplitude
of the video signal is obtained with VREF = 1.23 V.
! 10-bit DAC (Gch, Y, composite)
The equation holds: VOUT = (9.84 x VREF/RIREF x RL x N/1023)
! 8-bit DAC (Rch/Bch, C)
The equation holds: VOUT = (7.96875 x VREF/RIREF x RL x N/255)
ESTABLISHED
REVISED
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11.6 Clock oscillation system
REVISED
ＰＷＭ
SYNC synchronization phase
Ｅ
Ｘ
Ｔ
Ｉ
Ｎ
１
Ｅ
Ｘ
Ｔ
Ｉ
Ｎ
０
Ｅ
Ｘ
Ｔ
Ｍ
Ｏ
Ｄ
ＣＸＩＮ
ＣＸＯＵＴ
Ｖ
ＣＡＳＷ２
Ｘ
Ｆ
Ｏ
Ｖ
Ｒ
Ｌ
Ｐ
Ｆ
Ｉ
Ｐ
Ｐ
Ｃ
Ｏ
Ｌ
Ｌ
Ｄ
Ｅ
Ｔ
External synchronization
mode judgement
ＣＯＩＮ
ＳＷ
ＯＳＣＣＮＴ
ＴＧＯＥ
WE C4h bit7
Ｒ
Ｈ２
Ｈ１
ＣＬＲ
ＤＳ２
ＤＳ１
ＦＣＫ２Ｏ
Oscillation
control
High-speed pulse generator
ＳＵＢ
Ｖ４
Ｖ３
Ｖ２
Ｖ１
ＣＨ２
ＣＨ１
ＮＴＰＬ
ＣＣＤＳＥＬ２
ＣＣＤＳＥＬ１
ＣＣＤＳＥＬ０
ＡＳＷ１
ＨＣＬＲ
ＣＰＯＢ
ＦＢＬＫ
ＦＶＤ
ＦＷＨＤ
2FCK for ENC
ＷＨＤ
2FCK
ＳＹＮＣ／ＶＳＹＮＣ／ＶＤ
ＣＢＬＫ／ＨＲＥＦ
ESTABLISHED
External
synchronization mode
prohibited (I2C)
Low-speed pulse generator
Internally
connected pulse
(1) Internal synchronization
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ESTABLISHED
REVISED
ＣＸＩＮ
ＣＸＯＵＴ
ＦＣＫ２Ｏ
ＣＯＩＮ
ＳＷ
ＡＳＷ２ Ｆ
Ｖ
Ｖ
Ｃ
Ｒ
Ｘ
Ｏ
Ｌ
Ｌ
Ｄ
Ｅ
Ｔ
Ｅ
Ｘ
Ｔ
Ｉ
Ｎ
１
ＮＴＰＬ
ＣＣＤＳＥＬ２
ＣＣＤＳＥＬ１
ＣＣＤＳＥＬ０
LP phase
adjustment
circuit
ＰWM
VD2
LP
SYNC synchronization phase
(Preliminary)
ＬＰＦ
ＬＰＦ
Ｌ
Ｐ ＰＰＣ ＰＰＣ
ＦＣ
Ｃ
ＩＯ
Ｏ
２
ＥＥ
ＸＸ
ＴＴ
ＭＩ
ＯＮ
Ｄ０
External synchronization mode
judgement
External
synchronization mode
prohibited (I2C)
Internally
connected pulse
SPECIFICATIONS
“Hi-Z” in LL mode
ＯＳＣＣＮＴ
“H” in LL mode
Ｒ
Ｈ２
Ｈ１
ＡＳＷ１
ＳＵＢ
Ｖ４
Ｖ３
Ｖ２
Ｖ１
ＣＨ２
ＣＨ１
2FCK for ENC
ＨＣＬＲ
ＣＰＯＢ
ＦＢＬＫ
ＦＶＤ
ＦＷＨＤ
2FCK
ＷＨＤ
Low-speed pulse generator
ＣＢＬＫ／ＨＲＥＦ
Oscillation
control
ＤＳ２
ＤＳ１
High-speed pulse generator
ＳＹＮＣ／ＶＳＹＮＣ／ＶＤ
ＣＬＲ
ＴＧＯＥ
WE C4h bit7
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(2) Monitor camera mode (LL and VD2 synchronization)
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(3) Vehicle mounting mode
REVISED
synchronization
mode
“Hi-Z” in external
ＣＯＩＮ
ＣＸＩＮ
ＣＸＯＵＴ
Ｖ ＡＳＷ２
Ｃ
Ｆ
Ｘ
Ｖ
Ｏ
Ｒ
Ｌ
Ｐ
Ｆ
Ｉ
ＬＰＦ
ＰＣ
Ｐ
Ｃ
Ｏ
Ｌ
Ｌ
Ｄ
Ｅ
Ｔ
Ｅ
Ｘ
Ｔ
Ｍ
Ｏ
Ｄ
ＥＥ
ＸＸ
ＴＴ
ＩＩ
ＮＮ
０１
ＶＤ
ＣＳＹＮＣ／ＨＤ
SYNC synchronization phase
External synchronization mode
judgement
ＯＳＣＣＮＴ
ＴＧＯＥ
WE C4h bit7
Ｒ
Ｈ２
Ｈ１
ＦＣＫ２Ｏ
ＳＷ
ＤＳ２
ＤＳ１
ＣＬＲ Oscillation
control
High-speed pulse generator
ＳＵＢ
Ｖ４
Ｖ３
Ｖ２
Ｖ１
ＣＨ２
ＣＨ１
ＡＳＷ１
ＨＣＬＲ
ＣＰＯＢ
ＦＢＬＫ
ＦＶＤ
ＦＷＨＤ
“H” in external
synchronization
mode
ＷＨＤ
2FCK for ENC
ＣＢＬＫ／ＨＲＥＦ
ＮＴＰＬ
ＣＣＤＳＥＬ２
ＣＣＤＳＥＬ１
ＣＣＤＳＥＬ０
2FC
ＳＹＮＣ／ＶＳＹＮＣ／ＶＤ
ESTABLISHED
External
synchronization mode
prohibited (I2C)
Low-speed pulse generator
Internally
connected pulse
For HD/VD synchronization or SYNC synchronization, the horizontal phase can be varied by the
internal register setting. Variation of the horizontal phase acts on both the composite output and RGB
output. The variable range is ±5 µs.
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11.7 External TG mode
ＣＣＤ
V driver
MN3112
DS1
DS2
R
H2
H1
External
TG
FCK2O
SUB
CXIN
FVD
FWHD
NC
V4
V3
VSS5
VDD5
V2
NC
V1
NC
SUB
NC
CH2
CH1
CXIN
CXOUT
FVD
FWHD
PWM0
To drive a CCD not supported by the MN673276, the external TG mode can be used. Set bit 7 of
the address C4 of the register to “H”.
The MN673276 supplies FCK2O, FWHD, and FVD to the external TG. The CCD is driven with
the CCD drive pulses except SUB of the external TG.
SUB of the MN673276 must be used. Otherwise, ELC will not operate.
ESTABLISHED
REVISED
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11.8 External synchronization and input pin
Since the logic of the external synchronization input pin to be pulled up or down (depending on the
mode) varies as follows, a pull-up/-down resistor is not built in. Set as shown in the table below.
The monitor/vehicle mounting mode is switched by the external pin (EXTMOD).
Mode
Vehicle mounting mode
Monitor mode
EXTMOD
1
0
Monitor mode
The external synchronization supports the VD2 synchronization and LL synchronization.
The priority is VD2, LL, and INT in order.
Mode
EXTIN0
EXTIN1
(1)
Input signal
LP
VD2
Pin setting
Pull-down
Pull-down
VD2 synchronization
When VD2 is input to the EXTIN1 pin, the VD2 synchronization automatically becomes active.
LL synchronization
The internal synchronization/LL synchronization are switched by the external pin
(LLDET).
When the LP pulse is input to the EXTIN0 pin with LLDET being “H”, the LL
synchronization becomes active.
This LSI does not have an LL-phase variation function as a DSP. An external phase
adjustment is necessary by a mono-multivibrator, etc.
(2)
Vehicle mounting mode
The external synchronization supports the SYNC synchronization and HD/VD synchronization.
The priority is SYNC, HD/VD, and INT in order.
Mode
EXTIN0
EXTIN1
Input signal
CSYNC/HD
VD2
Pin setting
Pull-up
Pull-down
(1) SYNC synchronization
When EXTSYNC is input to the EXTIN0 pin, the SYNC synchronization automatically
becomes active.
(2) HD/VD synchronization
When EXTHD is input to the EXTIN0 pin and EXTVD is input to the EXTIN1 pin, the
HD/VD synchronization becomes active.
ESTABLISHED
REVISED
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11.9 CCD drive circuit
(1) H1, H2 and R, 3.3 V drives
ＣＣＤ
For high-speed pulses, insert a
dumping resistor, etc. to meet the
CCD drive specifications.
V４
V3
V2
V1
SUB
CH2
CH1
V driver
MN3112
R
H2
H1
The position and width of the R can
be adjusted by the register. For
details, refer to the register map.
MN673276
(2) H1, H2 and R, 5 V drives
CCD
H driver
If the high-speed pulses (H1, H2 and R) of the CCD
requires to be driven by the amplitude of 5 V, use
74VHC04, etc. to convert the level.
V driver
MN3112
ESTABLISHED
REVISED
V4
V3
V2
V1
SUB
CH2
CH1
R
H2
H1
74VHC04
MN673276
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11.10 Mode setting pin
The mode setting pin is logically fixed to reduce the number of externally fitted components
supposing that this LSI is used for PC or vehicle mounting, or to realize a frequently used state.
Pin name
NYPL
FLC
EXTMOD
SCANT
Logic
L
H
H
L
Description
NTSC system
Flicker correction ON
Vehicle mounting mode (HD or VD/SYNC synchronization mode)
Normal operation
L: pull-down, H: pull-up
11.11 External control signal
Six types of input pins are provided to allow the functions of the LSI to be controlled externally.
These controls can also be switched by I2C.
Pin name
LLDET
ALCELC
ATWLOCK
APGAIN
BLCSW
REV
ESTABLISHED
REVISED
Description
Switching internal synchronization/LL synchronization
L: internal synchronization
H: LL synchronization
Switching mechanical iris fixed/ELC
L: ELC
H: mechanical iris fixed
Stopping ATW
L: normal
H: ATWLOCK
Switching aperture gain
L: sharp
H: soft (APGAIN=0)
Switching target value
L: normal
H: Switches target value
Executing left-right reverse
L: normal
H: reversed
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11.12 Output specifications
Supports the following analog outputs. No digital output is provided.
・ Composite output
・ YC separated outputs
・ RGB outputs
・ Y/UV outputs (U and V are alternately output every 1H as shown below.)
HD
Y1
Y2
Y3
Y4
U1
V2
U3
V4
11.13 Signal processing back-end circuit
Setting the register carries out the output mode switching.
(1) Composite output
The modulated color signal does not pass a BPF to reduce the number of components nor form a
typical sine wave. If a certain level of signal quality is required, then provide a BPF in the C block
using the YC output mode shown below.
IREF23
COMP23
BSIG
DAVSS1
DAVDD1
ＲSIG
VREF1
IREF1
COMP1
GSIG
DAVSS2
DAVDD2
MN673276
6 dB AMP
Note) If a D/A converter is not used, set COMP23 = Vdd and IREF23 = VREF23 = 0.
ESTABLISHED
REVISED
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(2) YC output
DAVDD2
DAVSS2
GSIG
COMP1
IREF1
VREF1
RSIG
DAVDD1
DAVSS1
BSIG
COMP23
IREF23
VREF23
MN673276
R1
6 dB AMP
R2
BP
The YC output can be adjusted (±5T) by the register WE17h.
Register 17 ---- **** YCDSEL YC phase adjustment
(3) RGB
DAVDD2
DAVSS2
GSIG
COMP1
IREF1
VREF1
RSIG
DAVDD1
DAVSS1
BSIG
COMP23
IREF23
VREF23
MN673276
6 dB AMP
75 Ω drive
6 dB AMP
75 Ω drive
6 dB AMP
75 Ω drive
Note) With regard to (1), (2), and (3) above, if the high-bright part of the video signal is clipped
due to the register setting or the dynamic range of the output amplifier, the density of each
line of the color signal may be inconsistent.
ESTABLISHED
REVISED
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11.14 External PWM output
Five PWM outputs are provided. They can be used for any purpose, including the adjustment of the
oscillation frequency.
Since the output voltages of the PWM outputs depend on VDD (digital power supply voltage), care
should be taken in the design of the power supply if accuracy is required for the output voltages.
MN673276
PWM3
PWM2
PWM1
PWM0
IRIS
Example of application)
PWM0
(Internal synchronization/frequency adjustment for SC block in the LL mode)
PWM1
(DAC1 gain)
PWM2
(DAC2 and DAC3 gains)
PWM3
Free
IRIS
ALCDC adjustment
11.15 Control block
Aperture control
The aperture is controlled by a combination of electronic shutter controls and digital AGC.
(1) High-speed mode
A high-speed mode is provided so that the target value is attained at power-ON.
Note that the high-speed mode is activated only for a certain period immediately after the
power is turned ON. (Register variable range: 1 s max.)
The response speed in the high-speed mode is switched by 1 V/3 V.
(2) Mechanical iris control
The MN673276 is not provided with a mechanical iris control function but is provided with
PWM output to adjust DC. An external circuit detecting the CDS output signal performs the
iris control.
(3) Flicker correction
A flicker correction function with a 3-V averaging method is provided. Refer to ADR15 in the
description of registers.
(4) Maximum ELC speed
Settable between 1/60 s and 1/100000 s. The maximum value can be varied by a register.
ESTABLISHED
REVISED
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(5) Backlight correction
To enable metering with a backlight taken into consideration, the target value switching, weighting
coefficient switching, and frame pulse output are available in an interlock with the backlight
correction SW (BLCSW).
[Specifications of a frame pulse]
When BLC is ON, a frame pulse (AREAPULS) is output which becomes “H” only for the central
area. This allows the ALC (Galvano lens) control to be performed only with the brightness
information obtained in the central area. This is beneficial in the backlight condition.
AREAPLUS
0
0
Area A
× coefficient
× coefficient
Area B
Area C
× coefficient
As the above frame pulse alone is not effective in the ELC mode or in the AGC area, the
weighting coefficient can be varied with BLC-ON. (x 0.5, x 0.6, x 1, etc.)
BLC
Target value
Weighting
Register
Area
OFF
Target value 1
ON
Target value 2
Weighting coefficient 1
Weighting coefficient 2
Weighting coefficient 3
67 h
6A h
6C h
Weighting coefficient 4
Weighting coefficient 5
Weighting coefficient 6
68 h
6B h
6D h
Acts on AGC/ELC control
ESTABLISHED
REVISED
Frame pulse
ALC DC
A
B
C
Not output (fixed
at H)
Set value 1
A
B
C
Output
Set value 2
Acts on ALC (Galvano lens) control
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11.16 White balance
The white balance is determined by the average of an entire screen’s data. By processing the
average data in 2’s complement, the deviance of the increase in AGC gain on white balancing is
reduced. By changing the bit expansion of the ATW block from 9 bits to 10 bits, the accuracy of
white balance is improved.
(Major functions)
・ There are two modes: ATW and MANUAL. The mode is set by a register.
・ In the ATW mode, a limiter value for high color temperature/low color temperature can be set.
・ In the ATW mode, a LOCK function is provided. Setting the external pin ATWLOCK fixes the
white balance. For example, when shining a light source on a piece of white paper and setting
ATWLOCK after the ATW takes the data, the white balance is set.
・ In the MANUAL mode, a value is set in the internal register.
・ In the ATW mode, a high-speed mode is provided so that white balance converges at the moment of
power-ON. Note that the high-speed mode is activated only for a certain period immediately after
the power is turned ON. (Register variable)
・ The response speed in the high-speed mode is the maximum speed (or less) settable by the
MN673276.
・ The ULI function provided stops ATW in the high-brightness mode.
Note) Suppose that the camera set (LSI) is shut down with ULI in operation after ATW is locked.
The next time the camera is turned ON, the colors may vary because the information of
white balance was not retained.
ALC (aperture control)/AWB (white balance) metering area
Settable values for the area are limited. Refer to the register map for details.
Start point of ALC area
X-width of ALC area
Start point of ALC
center-weighted
metering area
X-width of ALC
center-weighted
metering area
×1
×4
×2
Y-width of ALC area
Start point of AWB area
Y-width of ALC
center-weighted metering area
X-width of AWB area
Y-width of AWB area
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
Total
pages
(Preliminary)
Page
79
11.17 OB control
The OB control consists of an analog and a digital controls.
The analog control is the method in which the clamping voltage for the analog CDS/AGC is
controlled so that the OB level detected internally by this LSI remains constant.
The digital control is the method in which the signal level within the LSI is controlled so that the
OB level detected internally by this LSI remains constant.
Analog OB control
CCD
MN673276
CDS
AGC
OB cont
AD
10(b)
＋
Signal processor
−
offset
DAC
10(b)
OB
averaged
10(b)
A
B Comparator
Target value
Activation
level is
determined
by the
difference
between A
and B.
10-bit
up/down
counter
Digital OB contorol
CCD
CDS
AGC
8(b)
Clip
2s→bin
MN673276
OB cont
AD
10(B)
＋
Signal processor
−
DAC
OB
averaged
Fixed value
ESTABLISHED
REVISED
＋
−
10(2s) A
Comparator
10(b) B
Target value
Activation
level is
determined
by the
difference
between A
and B.
10-bit
up/down
counter
10(2s)
8(2s)
Clip
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
MN673276
Confidential
SPECIFICATIONS
(Preliminary)
Total
pages
Page
80
11.18 External interface
The I2C interface is used to connect the external control of the MN673276 with the EEPROM for
storage of the register value used for adjustment.
Pull-up resistor
4.7 kΩ-10 kΩ
MN673276
SCL
SDA
SCL
SDA
Ｘ２４Ｃ０２Ｓ８１
To adjusting jigs or external
control equipment (PCs, etc.)
EEPROM
・ The I2C control modes supported by the MN673276 are as follows.
At power-ON: Sequential read (random read) of all addresses (256 bytes) of the EEPROM
Others:
Random read and byte-order write
・ Concerning mode
DSP
EEPROM
Adjusting PC
At activation
MR, Master Receiver
ST, Slave Transmitter
×
While adjusting
SR, Slave Receiver
MT, Master Transmitter
×
SR, Slave Receiver
MT, Master Transmitter
While adjusting and
×
writing
At RST after
MR, Master Receiver
ST, Slave Transmitter
×
adjustment
・ The slave address of the EEPROM is 55h and that of the MN673276 is fixed at 2Ah. The
adjusting PC, etc. may change the slave address of the MN673276 after activation but it is not
retained in the EEPROM.
・ Since SCL is generated by the system clock with a fixed frequency dividing ratio, it is 100
kHz for 768 pixels. However, SCL will become slower when a 510-pixel CCD is used.
・ Before reading the data in the EEPROM when the power is turned ON, it is necessary to
execute the following initialization sequence to initialize the EEPROM.
SCL
1
2
8
9
SDA
Start condition
ESTABLISHED
REVISED
Dummy clock (9CLK)
Start condition
Stop condition
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
ESTABLISHED
REVISED
∬
12C (DATA)
(Preliminary)
Total
pages
The read-out time depends on the frequency of FCK.
SPECIFICATIONS
It is prohibited that jigs or external control equipment works as a master.
Image is output after reading all addresses.
Operation when the system is activated
Analog image output
DSP reads from the master EEPROM.
∬
After approx. 3 V
∬
Synchronizing VD
Reset IC output
Power supply voltage
∬
Confidential
MN673276
Page
81
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Confidential
MN673276
SPECIFICATIONS
Total
pages
(Preliminary)
Page
82
12. CCD Drive/Synchronization Mode
Internal pin setting
CCD supported
FCK
CCDSEL2
CCDSEL1
External
pin setting
CCDSEL0
NTPL
VCOC
DEh: DDh
VCOH
E0h: DFh
VCOC
E2h: E1h
AWB area setting
Internal
synchronization
HD and VD
synchronization
VD2 and LL
synchronization
510H
PAL
MN37210
618fH
0
0
0
1
510H
PAL
MN37213
606fH
0
1
1
1
768H
NTSC
MN37140
910fH
1
0
0
0
768H
PAL
MN37241
908fH
1
0
0
1
C036h
EB15h
EFBDh
8000h
A000h
C08Eh
EB54h
EE94h
8000h
A1A3h
C08Eh
EC61h
EFA1h
8000h
A2B0h
The setting values in the register WE80 to 84 for AWB and WE40 to 44 for
ALC depending on the mode.
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Composite
○
○
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○
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YC separation
○
○
○
○
○
RGB
○
○
○
○
○
YUV time-division
multiplex
○
○
○
○
○
Output
Synchronization
ALC area setting
510H
NTSC
MN37110
606fH
0
0
0
0
All corresponding color filters for the CCD support complementary colors, as well as black and
white elements.
ESTABLISHED
REVISED
SYSTEM LSI DIVISION, SEMICONDUCTOR COMPANY
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.