SANYO LV25450PNW

Ordering number : ENA1668
Bi-CMOS LSI
LV25450PNW
For Automotive Applications
DSP Tuner Front End
Overview
The LV25450PNW is a tuner front end IC that supports the Sanyo SDRS500 car radio DSP.
The LV25450PNW supports worldwide radio standards including the FM bands used in US, Europe, East-Europe, and
Japan as well as the LW, MW, SW, and FM weather bands. It adopts an image canceling mixer for the FM mixer and
incorporates a fast PLL locking function. The LV25450PNW also supports automatic alignment using CCB bus control. It
requires external EEPROM.
The LV25450PNW can implement a DSP tuner at low cost with a minimal number of external components.
Functions
• AM,/FM-FE, IF, and PLL circuits
•
•
CCB is a registered trademark of SANYO Electric Co., Ltd.
CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO
Semiconductor for this format.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
31010 SY 20081121-S00006 No.A1668-1/40
LV25450PNW
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
CCB bus maximum input voltage
CCB bus maximum output
Symbol
Conditions
Ratings
Unit
VCC 8V
OSC_VCC (3), IFAGC_VCC (27),
IFAGCOUT-Drive_VCC (35), FE_VCC (61)
9.0
V
VCC 5V
XTAL_VCC (16), Digital_VCC (25),
Analog_VCC (41)
6.0
V
VIN max
VO
Pin 21, 22, 23
-0.3 to +5.0
V
Pin 24
-0.3 to +6.5
V
voltage
Allowable power dissipation
Pd max
Ta ≤ 85°C *
850
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-50 to +150
°C
* : Using the circuit board for the SANYO tuner module (specified board : 55mm × 39mm × 1.3mm, glass epoxy)
Recommended Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage
Operating supply voltage range
Symbol
Conditions
Ratings
Unit
8.0
V
5
V
VCC 8Vop
7.5 to 8.5
V
VCC 5Vop
4.5 to 5.5
V
VCC 8V
OSC_VCC (3), IFAGC_VCC (27),
IFAGCOUT-Drive_VCC (35), FE_VCC (61)
VCC 5V
XTAL_VCC (16), Digital_VCC (25),
Analog_VCC (41)
CCB bus high-level input voltage
VIH
CE, DI, CL
2.5 to 5.0
V
CCB bus low-level input voltage
VIL
CE, DI, CL
0 to 0.8
V
CCB bus high-level input current
IIH
CE, DI, CL ; VI5.5V
10 or less
μA
IIL
CE, DI, CL ; VI0V
CCB bus low-level input current
DO low-level output voltage
VOL
DO high-level output voltage
VOH
Connected to an LC75045.
10 or less
μA
0.38 or less
V
2.1 or more
V
Reception Frequencies
Parameter
FM reception frequencies
FM weather band reception
Symbol
fFM
Conditions
JPN, US, EU, E-EU
fFM-WB
Frequency ratings
Unit
65 to 108.1
MHz
162.4 to 162.55
MHz
kHz
frequencies
AM reception frequencies
fAMLW
LW
144 to 288
fAMMW
MW
520 to 1710
kHz
fAMSW
SW
2.94 to 22.0
MHz
No.A1668-2/40
LV25450PNW
Power on/Power off Timing and the Power on Reset
Recommended Operating Ratings at Ta = 25°C, GND = 0V
Parameter
Symbol
Ratings
Conditions
min
typ
Operating supply voltage
Vcop H
Pin 3, 27, 35, 54, 55, 61
Vcop L
Pin 16, 25, 41
4.5
5.5
V
Internal logic voltage
VREG3
Pin 26
2.7
3.3
V
VREG4
Pin 15
3.7
4.3
V
10
100
ms
Pin 26 : Design reference value
VREG3
2.2
V
Pin 15 : Design reference value
V
Power application time
(8.0 V → 5.0 V)
Internal register retention voltage
7.5
Unit
max
T7
Vhmin3
Vhmin4
8.5
V
VREG4
2.2
Internal register reset voltage
Voff
Pin 16, 25, 41 : Design reference value
0
0.2
Internal register reset power
tPOR
Pin 16, 25, 41 : Design reference value
0.05
3
ms
10
100
ms
V
supply rise time
Power application time
(5.0 V → 8.0 V)
T14
Power-on Sequence and Power-on Reset
(1) Power on image and power on reset
Recommended Operating Ratings at Ta = 25°C, GND = 0V
Parameter
Symbol
Ratings
Conditions
min
typ
Operating supply voltage
Vcop H
Pins 3, 27, 35, and 61
Vcop L
Pins16, 25, and 41
4.5
5.5
V
Internal logic voltage
VREG3
Pin 26
2.7
3.3
V
Internal register retention voltage
7.5
Unit
max
8.5
V
VREG4
Pin 15
3.7
4.3
V
Vhmin3
Pin 26 : Design reference value
2.2
VREG3
V
Pin 15 : Design reference value
V
2.2
VREG4
Internal register reset voltage
Vhmin4
Voff
Pins 16, 25, and 41 : Design reference value
0
0.2
Internal register reset power
tPOR
Pins 16, 25, and 41 : Design reference value
0.05
3
V
ms
supply rise time
Note 1 : When reading out data from pin D0 connection (e.g., E2PROM) with the voltage at the pin 23 below 2.2V, be sure to read the data after transmitting
the control data and pin D0 being set “open” because the state of internal register cannot be specified.
Note 2 : It is necessary to set data when power is first applied or there is a momentary power interruption.
VCC_8Vop
VCC_5Vop
VREG4
VREG3
Voff
Vhmin3
Vhmin4
tPOR
Image of Supply Voltage
No.A1668-3/40
LV25450PNW
(2) Power on/off sequence
The power on and power off sequences for the IC must follow the order shown below.
• Power on sequence
tPUP85
8V system power
5V system power
Period when power is
applied to each pin
• Power off sequence
8V system power
tPDN58
5V system power
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
Power on period (8V → 5V)
tPUP85
0
100
ms
Power off period (5V → 8V)
tPDN58
0
100
ms
Never apply power to the IC until all the supply voltages reach the predetermined values.
For pin D0, refer to the above section (1), Note 1, and Note 2.
Regarding voltage applied to each power pin, 8V system must always be higher than 5V system (8V system > 5V).
As long as this relationship is maintained and the power supply rise/fall time is within 100ms, there is no problem if the low voltage side power is started up first.
No.A1668-4/40
LV25450PNW
AC Characteristics
Operating Characteristics at Ta = 25°C, VCC = 8.0V, VDD = 5.0V, unless otherwise specified. Ratings for publications
* : These measurements are made using the Yamaichi Electronics IC51-0644-807 IC socket. An IHF bandpass filter is
used as the audio filter.
FM Characteristics - FM Front End Mixer Input (No dummy)
IN1
IN2
IN3-1
IN3-2
CCB Command
min
3
15
13
25
25
43.2
54
64.8
mA
3
15
13
25
25
20.8
26
31.2
mA
VREG3V
No input, FM mode
I3+I27+I355+I54+I55+I61
No input, FM mode
I16+I25+I41
The pin 26 voltage
3
15
13
25
25
2.7
3
3.3
V
VREG4V
The pin 15 voltage
3
15
13
25
25
3.6
4
4.4
V
IANTD-F
The pin 64 output current
(Pin 64 load = 100Ω +Pin_Diode × 2
when 6.0V is applied to pin 2
0
15
13
25
25
4.5
7.5
11
mA
FXTAL
D2-7, 6, 5 = [100]
3
15
13
25
25
Crystal oscillator level
VXTAL
3
15
13
25
25
15
Crystal oscillator
VXTAL OSC
3
15
13
25
25
115
165
buffer level
OUT2
D2-7, 6, 5 = [100] (reference value)
D32-08 = 0, D2-10, 9, 8 = [100]
D2-7, 6, 5 = [100] (reference value)
D32-08 = 0, D2-10, 9, 8 = [100]
S-meter DC output
VSMFM-1
15
13
25 25B
0.65
0.95
1.25
V
15
13
25 25B
0.95
1.25
1.55
V
15
13
25 25B
2.10
2.15
2.20
V
15
13
25 25B
3.1
3.4
3.7
V
15
13
25 25B
3.7
4
4.3
V
15
13
25
25
16
19
22
dB
15
13
25
25
4.5
7.5
10.5
dB
15
13
25
25
15
13
25
25
-4.5
-2.5
-0.5
dB
15
13
25
25
23.5
25.5
27.5
dB
15
13
25
25
107
Pin 2
Conditions
Pin 50
Symbol
Pin 34
Parameter
Pin 28
Applied voltage
typ
max
unit
DC Characteristics
Current drain-8V FM
ICCO-8V FM
Current drain-5V FM
ICCO-5V FM
Regulator bias 3V
Regulator bias 4V
FM antenna dump
output current
0
6
AC Characteristics
Crystal oscillator
4.5
MHz
frequency
* : Adjust the
shifter-bits with a
VSMFM-2
50dBμV input so
that Vsm is set to
2.15V.
VSMFM-3
VSMFM-4
VSMFM-5
Total gain from mixer
GMXDIV
to DIV IF amplifier
DIV IF amplifier gain
GDIVIF
1dB compression
1DB POINT DIF
point driver IF
Narrow IF AGC grain
GIFAGCNF1
(FM)
Narrow IF AGC grain
GIFAGCNF2
(FM)
1dB complession
point FM-Narrow
1DB POINT NF
10dBμV, the pin 34 DC output, no
3
modulation
30dBμV, the pin 34 DC output, no
3
modulation
50dBμV, the pin 34 DC output, no
3
modulation
70dBμV, the pin 34 DC output, no
3
modulation
90dBμV, the pin 34 DC output, no
3
modulation
FM_MIX_IN, DIV_OUT_IF (pin 32)
1.5
Ratio of the input to output signal
levels
98.1MHz mod = off, 70dBμV-Input
IF_N_IN1 (pin 46),
3
DIV_OUT_IF (pin 32)
Ratio of the input to output signal
levels
10.7MHz mod = off, 88dBμV-Input
IF_N_IN1 (pin 46),
3
DIV_OUT_IF (pin 32)
Ratio of the input to output signal
levels 10.7MHz mod = off
FM_ANALOG_IN (pin 46),
0
10.7OUTN (pin 30) Ratio of the input
to output signal levels
10.7MHz mod = off 100dBμV-Input
D32-27 to 25 = 011
FM_ANALOG_IN (pin 46),
3
10.7OUTN (pin 30) Ratio of the input
to output signal levels
10.7MHz mod = off 80dBμV-Input
D32-27 to 25 = 011
FM_ANALOG_IN (pin 46),
0
10.7OUTN (pin 30)
10.7MHz mod = off
D32-27 to 2] = 011
mVrms
mVrms
111
dB
dBμV
Continued on next page.
No.A1668-5/40
LV25450PNW
Continued from preceding page.
FM wide AGC on
WAGC ON-F1
sensitivity F1
FM wide AGC on
WAGC ON-F2
sensitivity F2
FM narrow AGC on
NAGC ON-F1
sensitivity F1
FM narrow AGC on
NAGC ON-F2
sensitivity F2
Practical sensitivity
S/N-31
Signal-to-noise ratio
S/N-90
98.1MHz reference, the amount
rejected at +21.4MHz
Trm-Bit D2-18=[0]:ON
APF-ADJ D32-19 to 16=[1010]:10
83MHz reference, the amount
rejected at -21.4MHz
D1-28 to 26 = [010]
Trm-Bit D2-18=[1]:OFF
APF-ADJ D32-19 to 16=[1000]:8
fr = 102.1MHz
FM-Wide AGC-Bit
D32-3 to 0 = [0000] : minimum
fr = 102.1MHz
FM-Wide AGC-Bit
D32-3 to 0 = [1111] : maximum
fr = 98.1MHz
FM-Narrow AGC-Bit
D32-7 to 4 = [0000] : minimum
fr = 98.1MHz
FM-Narrow AGC-Bit
D32-7 to 4 = [1111] : maximum
Connected to an LA1787 (MPX, left
channel output) *HCC OFF
98.1MHz, 31dBμV, fm = 1kHz,
22.5kHz-mod 62/63pin input
Connected to an LA1787 (MPX, left
channel output)
98.1MHz, 90dBμV, fm = 1kHz,
22.5kHz-mod 62/63pin input
1.5
15
21
25
58
30
dB
1.5
22
13
27
25
25
dB
Pin 2
Pin 50
IN3-2
IR JPN
ratio (JPN)
IN3-1
Image cancellation
IN2
IR US
ratio (US)
Conditions
IN1
Image cancellation
Symbol
Pin 34
Parameter
CCB Command
Pin 28
Applied voltage
min
typ
max
unit
0
3
15
13
25
13
78
85
92
dBμV
0
3
15
13
25
15
92
99
106
dBμV
0
3
15
13
25
16
70
77
84
dBμV
0
3
15
13
25
18
86
93
100
dBμV
3
15
13
25
25
30
0
15
13
25
25
54
Applied voltage
CCB Command
dB
57
dB
Conditions
IN1
IN2
IN3-1
IN3-2
No input, AM mode
I3+I27+I35+I54+I55+I61
No input, AM mode
I16+I25+I41
When pin 50 is connected to ground
The ANT-D (pin 52) output current
3
33
15
26
26
36
3
33
15
26
26
33
15
26
FM_N_IN1 (pin 46)
IF_OUT (pin 44), after CF matching,
10.7MHz mod = off 74dBμV = Input
AM_ANALOG_IN (pin 39),
10.7OUTN (pin 30) Ratio of the input
to output signal levels
10.7MHz mod = off 100dBμV-Input
D32-27 to 25 = [011]
AM_ANALOG_IN (pin 39),
10.7OUTN (pin 30) Ratio of the input
to output signal levels
10.7MHz mod = off 80dBμV-Input
D32-27 to 25 = [011]
AM_ANALOG_IN (pin 39),
10.7OUTN (pin 30)
10.7MHz mod = off
D32-27 to 25 = [011]
0
33
15
0
33
3
0
Pin 2
Pin 50
Symbol
Pin 34
Parameter
Pin 28
AM Characteristics : AM, AM-ANT inputs
min
typ
max
unit
46
56
mA
15
19
23
mA
26
3.5
6
9
mA
26
26
5.2
6.2
7.2
dB
15
26
26
-4.5
-2.5
-0.5
dB
33
15
26
26
23.5
25.5
27.5
dB
33
15
26
26
107
DC Characteristics
Current drain-8V AM
ICCO-8V AM
Current drain-5V AM
ICCO-5V AM
AM antenna dump
IANTD-A
output current
AC Characteristics
First AM amplifier
GAMP1
gain
Narrow IF AGC grain
GIFAGCNA1
(AM)
Narrow IF AGC grain
GIFAGCNA2
(AM)
1dB compression
point AM - narrow
1DB POINT NA
3
0
dBμV
Continued on next page.
No.A1668-6/40
LV25450PNW
Continued from preceding page.
0
33
15
WAGC ON-A2
sensitivity A2
0
33
15
AM narrow AGC on
NAGC ON-A1
sensitivity A1
0
33
AM narrow AGC on
NAGC ON-A2
sensitivity A2
0
Total AM gain
AMGAIN
Practical sensitivity
S/N-33
AM-THD
THD-74
Signal-to-noise ratio
S/N-74
typ
max
unit
26
27
78.5
83.5
88.5
dBμV
26
29
92
97
102
dBμV
15
26
30
60
65
70
dBμV
33
15
26
32
75
80
85
dBμV
3
33
15
26
26
36
41
46
dB
3
33
15
26
26
20
33
15
26
26
33
15
26
26
Pin 2
IN3-2
AM-ANT-IN = 1.4MHz, mod = off
The input level such that the ANT_D
(pin 52) level becomes 0.5V.
AM wide AGC-Bit
D32-3 to 0 = [0000]
AM-ANT-IN = 1.4MHz, mod = off
The input level such that the ANT_D
(pin 52) level becomes 0.5V.
AM wide AGC-Bit
D32-3 to 0 = [1101]
AM-ANT-IN = 1MHz, mod = off
The input level such that the ANT_D
(pin 52) level becomes 0.5V.
AM narrow AGC-Bit
D32-7 to 4 = [0000]
AM-ANT-IN = 1MHz, mod = off
The input level such that the ANT_D
(pin 52) level becomes 0.5V.
AM narrow AGC-Bit
D32-7 to 4 = [1111]
1MHz, 60dBμV, mod = off, the ration
of the AM_ANT input and the
10.7OUTN (pin 30) output levels
With an LA1787 connected
With a 1MHz, 33dBμV, fm = 1kHz,
30% modulation ANT input and the
IF AGC voltage = 3V add.
With an LA1787 connected
With a 1MHz, 74dBμV, fm = 1kHz,
80% modulation ANT input and the
IF AGC voltage adjusted so that the
IFAGCOUT level is 100dBμV.
With an LA1787 connected
With a 1MHz, 74dBμV, fm = 1kHz,
30% modulation ANT input and the
IF AGC voltage adjusted so that the
IFAGCOUT level is 100dBμV.
IN3-1
IN2
AM wide AGC on
Pin 50
IN1
WAGC ON-A1
sensitivity A1
min
dB
0.7
1.0
%
Adjusted
AM wide-AGC on
Pin 34
Conditions
Symbol
52.5
56
dB
Adjusted
Parameter
CCB Command
Pin 28
Applied voltage
Package Dimensions
unit : mm (typ)
3190A
12.0
0.5
10.0
48
33
64
12.0
32
10.0
49
17
1
16
0.5
0.18
0.15
0.1
1.7max
(1.5)
(1.25)
SANYO : SQFP64(10X10)
No.A1668-7/40
LV25450PNW
Test data pattern
Delay-Adj
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
2176
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
1
0
2169
1
33 MW1000k fref = 10k (USA)
0
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
1
0
1
1
0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
23400
0
ALC_OFF
----
----
----
----
----
----
OFFSET_SW
0
1
0
0
1
0
0
0
0
0
0
0
1
X'tal-Adj
XLVL2
0
X'tal-Level
XLVL1
0
TEST2
XLVL0
1
TEST1
X_SW_2
0
TEST0
X_SW_1
0
DZ1
X_SW_0
1
DLC
----
0
DZ0
----
0
----
----
1
----
----
0
TWO_DOFF
----
1
UL1
A7
0
UL0
A6
0
ULD
A5
1
Control data 4
----
A4
Control data 3
A3
Control data 2
A2
13 FM reception mode settings
Control data 1
A1
Data contents
CCB address
A0
IN2
PLL IN2 data
----
0
0
FMFIL
0
0
WB
AMFIL
DELAY_ADJ2
DELAY_ADJ1
DELAY_ADJ0
0
0
R3
1
1
R2
0
1
R1
0
1
R0
P12
0
1
DVS
P11
0
0
AM/FM
P9
P10
0
0
P15
P8
0
1
P14
P7
0
0
P13
P6
0
0
P0
0
1
A7
1
0
A6
0
1
A5
1
0
A4
0
0
A3
0
0
A2
0
22 FM_JP83M fref = 100kHz,
Delay = 1
A1
15 FM_US98.1M fref = 100kHz
Data contents
A0
PLL
Counter
value
IN1
P5
OSC_DIV
Control data 4
P4
OSC_D2
Control data 3
OSC_D1
Control data 2
P3
Control data 1
P2
CCB address
P1
PLL IN1 data
0
0
1
1
0
1
0
0
1
0
0
0
0
4
4
(Trm=OFF)
15 MW reception mode settings
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
4
4
21 FM reception mode settings
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
4
4
(Trm=ON)
A6
A7
RFDAC0
RFDAC1
RFDAC2
RFDAC3
RFDAC4
RFDAC5
RFDAC6
RFDAC7
RFDAC8
TUNEROFF
ANTDAC0
ANTDAC1
ANTDAC2
ANTDAC3
ANTDAC4
ANTDAC5
ANTDAC6
ANTDAC7
ANTDAC8
REG_ADJ0
REG_ADJ1
XS0
XS1
DAC9_SW2
DAC9_SW
IQMIX_GAIN
IQ_SW
FMAGC_ON
AMAGC_ON
IFAGC_OFF
DTESTSW
Sub-Address
RF-DAC
ANT-DAC
1 Bit-Check-0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
2 Bit-Check-1
1
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
3 Bit-Check-2
1
0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
2
2
5 Bit-Check-4
1
0
0
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
4
4
6 Bit-Check-7
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
7
7
7 Bit-Check-8
1
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
8
8
8 Bit-Check-15
1
0
0
1
0
1
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
15
15
9 Bit-Check-16
1
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
16
16
10 Bit-Check-31
1
0
0
1
0
1
1
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
31
31
11 Bit-Check-32
1
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
32
32
12 Bit-Check-63
1
0
0
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
63
63
13 Bit-Check-64
1
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
64
64
14 Bit-Check-127
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
127
127
15 Bit-Check-128
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
128
128
16 Bit-Check-255
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
255
255
17 Bit-Check-256
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
256
256
18 Bit-Check-511
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
511
511
25 Standard FM (Upper)
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
256
256
26 Standard FM
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
27 Standard FM (Lower)
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
256
256
30 Tuner-OFF(FM)
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
256
256
Sub-Address
IFAGC-Amp Gain
FM-S-meter Shifter
Keyed-AGC
AM-RFAGC Hard
Narrow-AGC
Wide-AGC
----
FMFETOFF
ADJ_N2
ADJ_N1
ADJ_N0
S_METER4
S_METER3
Control data 4
S_METER2
S_METER1
S_METER0
APF_ADJ3/RFAGC_S3
APF_ADJ2/RFAGC_S2
APF_ADJ1/RFAGC_S1
APF_ADJ0/RFAGC_S0
KEY_AGC3/RFAGC_H3
Control data 3
KEY_AGC2/RFAGC_H2
KEY_AGC1/RFAGC_H1
VREG4V_OFF
KEY_AGC0/RFAGC_H0
----
----
EVA2 (Xtal)
N_AGC3
Control data 2
N_AGC2
N_AGC1
N_AGC0
W_AGC3
W_AGC2
W_AGC1
W_AGC0
A7
Control data 1
A6
A5
A4
A3
A2
A1
Data contents
CCB address
A0
IN3-2
PLL IN3-2 data
AM-RFAGC Soft
Data contents
W_KEYED
IN3-1
A5
Control data 4
A4
Control data 3
A3
Control data 2
A2
Control data 1
A1
CCB address
A0
PLL IN3-1 data
13 FM (W-AGC-Bit = 0)
1
0
0
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
0
7
0
7
7
15
3
15 FM (W-AGC-Bit = 15)
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
15
7
0
7
7
15
3
16 FM (N-AGC-Bit = 0)
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
7
0
0
7
7
15
3
18 FM (N-AGC-Bit = 15)
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
7
15
0
7
7
15
3
25 Standard FM-2
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
7
7
0
7
7
15
3
25B Standard FM-2
Vsm-Shifter After the
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
0
*
*
*
*
*
1
1
0
0
0
0
1
7
7
0
7
7 Adjust-
3
ment
adjusting
26 Standard AM-2
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
7
7
0
6
12
15
27 AM (W-AGC-Bit = 0)
1
0
0
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
0
7
0
6
12
15
3
3
29 AM (W-AGC-Bit = 13)
1
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
13
7
0
6
12
15
3
30 AM (N-AGC-Bit = 0)
1
0
0
1
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
7
0
0
6
12
15
3
32 AM (A-AGC-Bit = 15)
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
1
7
15
0
6
12
15
3
58 Standard FM-2 Trm=ON
APF-Adj=10
1
0
0
1
0
1
1
0
1
1
1
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
1
1
0
1
1
0
0
0
0
1
7
7
1
7
5
15
3
Items marked with an asterisk are Vsm adjustment items. The bit values after adjustment must be retained.
No.A1668-8/40
LV25450PNW
Power dissipation test board
Material
Conditions
Board size
: Glass epoxy resin
: Double-sided circuit board, without chassis
: 55mm × 39mm × 1.3mm
* Ratings for LV25450PNW power dissipation is measured using the above circuit board.
No.A1668-9/40
LV25450PNW
Pin Functions
Pin No.
Pin Name
1
FE_GND
2
3
Pin No.
Pin Name
33
IFAGCOUT-Drive GND
FM-RF-AGC
34
VSM_DC
Local-OSC-VCC 8V
35
IFAGCOUT-Drive VCC
4
Local-OSC (B)
36
VREG2.7V
5
Local-OSC (C)
37
Analog_GND
6
Local-OSC_GND
38
AM ANALOG IN Bypass
7
VT (LPF)
39
AM ANALOG IN
8
FET_GND
40
(non-connection)
9
PLL-LPF_AM
41
Analog_VCC 5V
10
FM_FET_OUT
42
AM_N-AGC pick-up
11
AM_FET_OUT
43
Address-SW
12
AM_CP OUT
44
AM 1stIF_AMP_OUT
13
FM_CP OUT
45
VREG4.9V
14
Digital_GND
46
IF-IN-N1 (CF = 180k)
15
VREG 4V
47
IF-IN-N_Bypass
16
Xtal-VCC 5V
48
(non-connection)
17
XTAL-IN
49
AM-W-AGC
18
XTAL-OUT
50
AM-RF-AGC
19
Xtal-GND
51
AM RF-AGC (Bypass)
20
XTAL_OSC_OUT2
52
AM-ANT-D
21
CE
53
FM N-AGC-IN
22
DI
54
MIX-OUT
23
CL
55
MIX-OUT
24
DO
56
ANT-DAC
25
Digital_VCC 5V
57
RF-DAC
26
VREG 3V
58
(non-connection)
27
IFAGCAMP_VCC 8V
59
AM-MIX-IN2 (Bypass)
28
AGC_DAC_S (fromDSP)
60
AM-MIX-IN1
29
IFAGCAMP_GND
61
FE VCC_8V
30
IFAGC-OUT (10.7MHz) N
62
FM-MIX-IN1
31
IFAGC-OUT (10.7MHz) P
63
FM-MIX-IN2
32
DIV_IF-OUT
64
FM-ANT-D
No.A1668-10/40
LV25450PNW
Functions
AM/FM front-end AGC block
FM Image rejection Mixer (IQ-MIX)
Gain switching : 1 bit
FM IQ-MIX phase adjust (For the Japanese FM band)
Injection switching
1 bit
for East Band Receive
AM Double balance Mixer
Pin diode drive AGC output (AM/FM)
Wide AGC sensitivity setting (AM/FM)
4 bit DAC
Narrow AGC sensitivity setting (AM/FM)
4 bit DAC
Keyed AGC adjust (FM)
4 bit DAC
AM RF AGC
4 bit DAC
Local oscillator
133MHz to 262MHz
Local osc divider (FM/AM)
Division by 1, 2, or 3
Local osc divider (AM)
Division by 20, 16, 12, or 8
ANT/RF DAC (FM)
9 bit DAC × 2
AM 1st IF AMP block
1st-IF amplifier 10.7M
IF-Lim-Amp/S-meter block
S-meter shifter
5 bit DAC
IF Limiter Amplifier 6 stage
for FM-S-meter
S-meter (DC for keyed AGC) (FM)
IF-AGC-Amp/IF-Amp for Diversity block
IF AGC Amplifier (control Voltage from DSP)
IF output Driver for DSP
10.7MHz IF
IFAGC-Amp Gain Adjust.
IF-Amplifier for Diversity (Fixed Gain)
10.7MHz IF
IF-Output Driver for DIV-IF
10.7MHz IF
PLL
Fast lock PLL
Filter SW
Charge-Pomp switching
other
Tuner off
1 bit SW
2.7V Regurator adjust
2 bit DAC
No.A1668-11/40
LV25450PNW
LV25450PNW Level Diagrams
-3.5
0
ANT in dBμV
ANT
ANTD
5.0
43.6
65.0
120.0
1.5
40.1
61.5
116.5
1.5
40.1
61.5
68.1
FET : FET Application
FM (FET) Gain Down
Near practical sensitivity
IFAGC-ON
RFAGC-ON
Strong input signal
-3
CF
(180k)
34.9
73.5
94.9
101.5
13.5
IQ
Mixer
37.9
76.5
97.9
104.5
22.9
FET
Amp
24.4
63.0
84.4
91.0
25.5
IFAGC Amp
60.4
99.0
99.0
99.0
55.4
Total
Gain
FM Level Diagram
120
ANTin = 120dBμV
100
Level [dBμV]
80
ANTin = 65dBμV
60
ANTin = 45.6dBμV
40
20
ANTin = 5dBμV
0
ANT in dBμV
ANT
ANTD
FET
Amp
IQ
Mixer
CF
(180k)
IFAGC Amp
Block
AM
Near practical sensitivity
IFAGC-ON
RFAGC-ON
Strong input signal
Full Gain
-16.5
0
21.5
10.5
ANT IN
ANT Dummy
ANTD
RF amp
Mixer
24
56.3
80
120
7.5
39.8
63.5
103.5
7.5
39.8
63.5
63.5
29
61.3
85
85
39.5
71.8
95.5
95.5
6.2
1st-IF
Amp
42.2
74.5
98.2
98.2
-3.5
CF
(180k)
36
68.3
92
92
-1
Xtal filter
(6k)
41.2
73.5
97.2
97.2
25.5
IFAGC
Amp
66.7
99
99
99
AM Level Diagram
120
ANTin = 120dBμV
Signal level [dBμV]
100
80
ANTin = 65dBμV
60
ANTin = 45.6dBμV
40
20
ANTin = 5dBμV
0
ANT IN
ANT Dummy
ANTD
RF amp
Mixer
CF
(180k)
1st-IF
Amp
Xtal filter
(6k)
IFAGC
Amp
Block
No.A1668-12/40
5V
L
P
F
L
P
F
Coil
tuning circuit
8V
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IN 1
IN 2
63
61
18
Xtal 4.5MHz
17
XTAL
OSC
19
20
Xtal-OSC
level adj
Xtal-OSC
freq. adj
R-CTR
NMOS Tr
ECL1
1/1,1/2
1/3
ECL2
1/4,1/6
1/8,1/10
POWER ON
RESET
4V REG
60
21
AM Mixer/
FM IQ-Mixer
62
RF DAC
57
Narrow AGC
RF AGC
ANT-D
FM AGC
ANT DAC
58
22
23
Computer
Control
Bus
IN 3-1
IN 3-2
55
24
25
FM
APF adj
AM RFAGC Amp
sens
5V
26
3V REG
27
8V
9BIT-DAC
temperature
characteristics
compensatioin
slope switching
IQ-Mixer
gain-adj
IF gain variation
FM
correction
keyed-AGC (narrow
output)
S-Meter
Shifter
AM/FM
N-AGC
54
AM RFAGC
compalate
Keyed
AGC
Wide AGC
56
MIX
COIL
AM/FM
W-AGC
TUNER adjustment
59
BPF
AM antenna
circuit
8V
AM RF
amplifier circuit
charge
pump
phase
det
P-CTR
swallow
counter
PLL
VCO
64
FM RF
tuning circuit
FM RF
amplifier circuit
52
28
29
49
30
IFDriver
31
32
Analog Diver
IF
IF AGC
AMP Buffer
FM
AMP
AM
AMP
IF AGC AMP
S-METER
(main/sub)
Limitter
AMP
Singal Meter
AM
1st AMP
Wide AGC
Narrow AGC
50
ANT-D
51
RF AGC
AM AGC
53
2.7V
REG
4.9V
REG
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
8V
Xtal Filter_16kHz
5V
CF10.7MHz_180k
LV25450PNW
Block Diagram
No.A1668-13/40
LV25450PNW
Pin Description
2
FM-RF-AGC
Description
Equivalent Circuit
Front-end block GND
FM RF AGC voltage output
VCC
500Ω
FE.GND
500Ω
Pin Function
1
500Ω
Pin No.
500Ω
2
12kΩ
30kΩ
3
Local-OSC-VCC 8V
4
Local-OSC (B)
5
Local-OSC (C)
Local oscillator system power supply
Oscillator pins
VCC_3pin
5
4.5V
4
DC-Offset
Circuit
6
Local-OSC-GND
7
VT (LPF)
Local oscillator system GND
7
1
8
FET_GND
2
1
2
100Ω
Active filter FET GND in the PLL
circuit block
9
PLL-LPF_AM
9
1
FM_FET_OUT
10
2
100Ω
1
2
1
10
2
1
2
5.5kΩ
Continued on next page.
No.A1668-14/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
11
AM_FET_OUT
Description
Equivalent Circuit
11
1
12
2
1
2
100Ω
AM_CP OUT
12
1
13
2
1
2
200Ω
FM_CP OUT
13
1
14
Digital_GND
15
VREG 4V
2
1
2
200Ω
Digital system GND
Dedicated swallow counter 4V
VCC
regulator voltage smoothing
VCC (25pin)
PLL
VDD
DAC
15
5kΩ
16
Xtal-VCC 5V
35kΩ
Dedicated crystal oscillator power
supply
17
XTAL-IN
Connect a 4.5MHz crystal resonator
18
VCC (PIN16)
ES6
between pins 17 and 18.
1.5kΩ
XTAL-OUT
35pF
Connect a 10pF capacitor between
1.5kΩ
1.5kΩ
333Ω
1kΩ
500Ω
1.5kΩ
AMP
pin 17 and GND, and a 150pF
AMP
capacitor between pin 18 and GND.
5kΩ 500Ω
1.5kΩ 1.5kΩ
500Ω
17
333Ω
AMP
5kΩ
333Ω
18
20
1kΩ
20kΩ
ALC
to PLL
8pF 4pF 2pF
19
Xtal-GND
Dedicated crystal oscillator GND
Continued on next page.
No.A1668-15/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
Description
20
XTAL_OSC_OUT2
Pin 20: clock signal output for 2-tuner
21
CE
Equivalent Circuit
Serial data input (DE) to the
3V
LV25450PNW.
Force the output to the high level
during serial data output (DO).
P-MOS
P-MOS
21
1kΩ
N-MOS
N-MOS
VSS (PIN14)
22
DI
Input for the serial data transferred to
3V
the LV25450PNW from the controller.
P-MOS
P-MOS
22
1kΩ
N-MOS
N-MOS
VSS (PIN14)
23
CL
Clock used for synchronization when
3V
serial data is input to the
LV25450PNW (DI) or when serial
data is output (DO).
P-MOS
P-MOS
23
1kΩ
N-MOS
N-MOS
VSS (PIN14)
Continued on next page.
No.A1668-16/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
24
DO
Description
Equivalent Circuit
Output for data transferred to the
controller by the LV25450PNW
24
500Ω
VSS (PIN12)
500Ω
VSS (PIN14)
25
Digital_VCC 5V
26
VREG3V
Digital system power supply
3V regulator output for PLL power
supply
VCC
VCC (25pin)
PLL
VDD
DAC
26
5kΩ
27
IFAGCAMP_VCC 8V
28
AGC_DAC_S
41.7kΩ
IF (10.7MHz) signal system power
supply
IF AGC control bias is supplied from
the LC7504x (for the analog system).
4.1kΩ
1kΩ
8kΩ
28
4.1kΩ
1kΩ
8kΩ
29
IFAGCAMP_GND
IF (10.7MHz) signal system GND
Continued on next page.
No.A1668-17/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
30
IFAGC-OUT
Narrowband IF (10.7MHz) signal
Description
(10.7MHz) N
differetial output to the LC7504x for
Equivalent Circuit
VCC (33pin)
analog use.
250Ω
50Ω
30
50Ω
250Ω
31
IFAGC-OUT
Narrowband IF (10.7MHz) signal
(10.7MHz) P
differential output to the LC7504x for
VCC (33pin)
analog use.
250Ω
50Ω
31
50Ω
250Ω
32
DIV_IF-OUT
Driver 10.7MHz signal buffer output
VCC (61pin)
200Ω
32
14.5Ω
200Ω 10kΩ
33
IFAGCOUT-Drive GND
34
VSM_DC
Dedicated IFAGC output driver GND
Current driver S-meter output
AC components are removed with an
VCC (41pin)
external capacitor.
300Ω
34
VCC (61pin)
1kΩ
10kΩ
Continued on next page.
No.A1668-18/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
Description
35
IFAGCOUT-Drive VCC
Dedicated IFAGC output driver VCC
36
VREG2.7V
2.7V internal regulator output
(smoothing)
Equivalent Circuit
VCC (PIN61)
1kΩ
36
333Ω
30kΩ
37
38
39
Analog_GND
Analog system GND
AM ANALOG IN Bypass Pin 39 : AM analog signal input to the
AM ANALOG IN
AM IFAGC amplifier. (AM 10.7MHz IF
signal)
Pin 38 : Connected to ground with an
external bypass capacitor.
335Ω
38
3.4V
2.3kΩ
9kΩ
9kΩ
335Ω
39
10kΩ
40
N.C.
41
Analog_VCC 5V
Analog system power supply
42
AM Narrow-AGC
AM narrow AGC detection input
Pick-Up
42
500Ω
500Ω
10kΩ
43
Address_SW
When two tuners are used, one (for
substitute) of the two ICs’pin 43 is
connected to ground, need changes
the sddress.
43
1kΩ
Continued on next page.
No.A1668-19/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
44
AM 1stIF_AMP_OUT
Description
Equivalent Circuit
First AM IF amplifier output
VCC (PIN61)
333kΩ
44
50Ω
45
VREG4.9V
4.9V internal regulator output
(smoothing)
335Ω
45
34Ω
1kΩ
50kΩ
46
IF-IN-N1
47
IF-IN-N_Bypass
15kΩ
First AM IF amplifier input
Driver 10.7MHz signal buffer input
46
FM limiter amplifier input
500Ω 500Ω
500Ω 500Ω
335Ω
335Ω
20pF 20pF
300Ω
550Ω
47
270Ω
300Ω
V
500Ω
500Ω
48
N.C.
49
AM-W-AGC
AM wide AGC pickup
49
1kΩ
10kΩ
1kΩ
Continued on next page.
No.A1668-20/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
50
AM-RF-AGC
Description
Equivalent Circuit
RF AGC rectifying capacitor
VCC (61pin)
Determines the distortion for
low-frequency modulation.
Increasing the size of C50 :
Distortion → Improves
15kΩ
Response → Becomes slower
1kΩ
50
Reducing the size of C50 and C 51 :
Distortion → Degrades
Response → Becomes faster
750Ω
100Ω
51
AM-RF-AGC
(Bypass)
500Ω
Reducing the size of C51 :
Distortion → Degrades
Response → Becomes faster
1kΩ
51
50kΩ
500Ω
52
AM-ANT-D
Provides the PIN diode drive current.
VCC_8V
This is the antenna dumping current
output.
52
200Ω
500Ω
53
FM N-AGC-IN
FM narrow AGC input
53
2.5kΩ
1kΩ
10kΩ
2.2V
54
MIX-OUT
Mixer output
54
(common to FM and AM)
55
MIX-OUT
55
FM MIX
AM MIX
Continued on next page.
No.A1668-21/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
Description
56
ANT-DAC
Antenna tuning circuit adjustment D/A
Equivalent Circuit
converter output
1kΩ
(9-bit D/A converter)
1kΩ
56
1kΩ
1kΩ
1kΩ
57
RF-DAC
RF tuning circuit adjustment D/A
converter output
1kΩ
(9-bit D/A converter)
1kΩ
57
1kΩ
1kΩ
1kΩ
58
N.C.
59
AM MIX-IN2
(Bypass)
60
AM mixer input
VCC (PIN61)
Input impedance : 10kΩ
AM MIX-IN1
60
2.5kΩ
10kΩ
110Ω
59
61
FE VCC 8V
Front-end block power supply
62
FM MIX-IN1
FM mixer input
63
FM MIX-IN2
10kΩ
12kΩ
FM MIX
FM wide AGC pickup
Input impedance : 10kΩ
110Ω
AGC AMP
62
500Ω
500Ω
63
10kΩ
10kΩ
3.6V
Continued on next page.
No.A1668-22/40
LV25450PNW
Continued from preceding page.
Pin No.
Pin Function
64
FM ANT D
Description
Equivalent Circuit
Pin 64 : The antenna driving current
VCC
flows when the RF AGC voltage
reaches (VCC - Vbe).
75kΩ
300Ω
64
300Ω
No.A1668-23/40
LV25450PNW
Serial Bus Data Timing
≈
: Chip enable
: Clock
: Data input
: Data output (pin information only)
VIH
tCH
VIH
VIL
VIH
VIH
≈ ≈ ≈
CL
VIH
DI
VIL
tSU
VIH
tEL
tES
VIL
tHD
≈
tCL
VIL
≈
CE
VIH
tEH
≈ ≈
CE
CL
DI
DO
≈ ≈
≈ ≈
tLC
Internal data
latch
Old
New
≈
〈〈 When CL is stopped at the L level 〉〉
VIH
tCL
VIH
VIL
VIH
≈ ≈
VIH
DI
tSU
tHD
VIL
tEL
tES
VIH
tEH
tLC
≈ ≈
VIL
VIH
Internal data
latch
≈ ≈
CL
VIL
≈ ≈ ≈
tCH
≈ ≈
CE
Old
New
〈〈 When CL is stopped at the H level 〉〉
Parameter
Symbol
Pin
Conditions
min
typ
max
unit
Data setup time
tSU
DI, CL
0.45
μs
Data hold time
tHD
DI, CL
0.45
μs
Clock L-level time
tCL
CL
0.45
μs
Clock H-level time
tCH
CL
0.45
μs
CE wait time
tEL
CE, CL
0.45
μs
CE setup time
tES
CE, CL
0.45
μs
CE hold time
tEH
CE, CL
0.45
Data latch change time
tLC
Data input high-level voltage
VIH
CL, DI, CE
Data input low-level voltage
VIL
CL, DI, CE
μs
0.45
μs
2.5
5.0
V
0
0.8
V
No.A1668-24/40
LV25450PNW
Serial Data I/O Procedures
The LV25450PNW uses the SANYO audio IC serial bus format. Data is input and output using a CCB (Computer
Control Bus). The LV25450PNW adopts an 8-bit address version of the CCB format.
I/O mode
[1]
Address
B0
B1
B2
B3
A0
A1
A2
Contents
A3
IN1
0
0
0
1
0
1
0
0
• Control data input mode. PLL setup
IN1B
0
1
0
1
0
1
0
0
• 32 bits of data are input
IN2
1
0
0
1
0
1
0
0
• Control data input mode. PLL setup
IN2B
1
1
0
1
0
1
0
0
• 32 bits of data are input
IN3
1
0
0
1
0
1
1
0
• The tuner block is set up in control data input (serial data input) mode.
IN3B
0
0
0
1
0
1
1
0
• 32 bits of data are input - There is a sub-address
• IN1B is the 2-tuner mode address (when pin 43 is tied to ground)
[2]
• IN2B is the 2-tuner mode address (when pin 43 is tied to ground)
[3]
• IN3B is the 2-tuner mode address (when pin 43 is tied to ground)
≈
I/O mode determined
≈
CE
B0
DI
B1
B2
B3
A0
A1
A2
≈ ≈
CL
A3
First Data IN1/2
i) Serial data inputs (IN1/IN2/IN3) tSU, tHD, tES, tEL, tEH > 0.45μs tLC < 0.45μs
tEL
tES
tEH
CE
CL
tSU
DT
B0
tHD
B1 B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
*
CTS GT0 GT1
tLC
Internal data
(*1) Since the DO pin is an N-channel open drain circuit, the times for the data to change will differ depending on the
value of the pull-up resistor and printed circuit board capacitance.
(*2) The DO pin is normally left open.
No.A1668-25/40
LV25450PNW
DVS
AM/FM
Program-CTR Stop
Program-CTR Normal
0
FM
operation
1
AM
0
1
IN1 setting
AM oscillator divisor control
OSD D2 OSD D1
Divisor
0
0
Divisor by 10
1
0
Divisor by 8
0
1
Divisor by 6
1
1
Divisor by 4
A A A A B B B B IN
3 2 1 0 3 2 1 0
0 0 1 0 1 0 0 0
Address Code
D1-12
D1-11
D1-10
D1-09
D1-08
D1-07
D1-06
D1-05
D1-04
D1-03
D1-02
D1-01
D1-00
P14
P13
P12
P11
P10
P09
P08
P07
P06
P05
P04
P03
P02
P01
P00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L H H L H L
(5)
(4) (3)
LSB
D1-13
P15
R1
(6)
D1-14
R2
(7)
OSC D1
D1-21
R3
(8)
D1-15
D1-22
L
OSC D2
D1-23
WB
OSC_DIV
L
D1-16
D1-24
DELAY_ADJ0
L
D1-17
D1-25
DELAY_ADJ1
L
AM/FM
D1-26
L
D1-18
D1-27
0
DELAY_ADJ2
L
R0
D1-28
FMFIL
L
DVS
D1-29
AMFIL
L
D1-19
D1-30
L
D1-20
D1-31
MSB
L
(2)
(1)
AM/FM/WB oscillator divide control
OSD DIV
Divisor
WB
Divide by 2
0
0
Divide by 3
0
1
Divide by 1
1
0
Divide by 1
1
1
*WB : Select 1 for weather band reception
Reference frequency setting
100kHz
0000
50kHz
0001
25kHz
0010
25kHz
0011
12.5kHz
0100
6.25kHz
0101
3.125kHz
0110
3.125kHz
0111
10kHz
1000
9kHz
1001
5kHz
1010
1kHz
1011
3kHz
1100
30kHz
1101
Illegal value
1110
Illegal value
1111
PLL filter switching
Filter state
AM/FM AMFIL
Normal
DELAY_ADJ2
0
0
0
0
1
1
1
1
DELAY_ADJ1 DELAY_ADJ0 Adjustment amount
0
0
Small
0
1
↓
1
0
↓
1
1
↓
0
0
↓
0
1
↓
1
0
↓
1
1
Large
OFF
ON
1
ON
OFF
Programmable counter divisor setting (from 272 to 65535)
0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 Divide by 272
:
:
0000
0001
1111
010
Divide by 500
:
1110
100
Divide by 1000
:
1101
000
Divide by 2000
:
0101
010
Divide by 21845
:
1010
101
Divide by 43690
:
1111
111
Divide by 65535
:
0000
0011
:
0000
FM-IQMIX phase_Adjust
FMFIL
0
0111
:
0101
0101
:
1010
1010
:
1111
1111
No.A1668-26/40
LV25450PNW
IN2 setting
A A A A B B B B IN
DO pin control data
3 2 1 0 3 2 1 0
Lo-OSC DC OFFset giving function
ULD
DO pin
D2-18
OFFset giving switch SW
0
Low when not locked.
0
1
Open
1
OFFset giving ON
OFFset giving OFF
0 0 1 0 1 0 0 1
Address Code
D2-30
D2-29
D2-28
D2-27
D2-26
D2-25
D2-24
D2-23
D2-22
D2-21
D2-20
D2-19
D2-18
D2-17
D2-16
D2-15
D2-14
D2-13
D2-12
D2-11
D2-10
D2-09
D2-08
D2-07
D2-06
D2-05
D2-04
D2-03
D2-02
D2-01
D2-00
TEST2
TEST1
TEST0
DLC
DZ1
DZ0
0
0
TWO_DOFF
UL1
UL0
ULD
0
OFFSET_SW
0
0
0
0
0
0
ALC_OFF
XLVL2
XLVL1
XLVL0
X_SW_2
X_SW_1
X_SW_0
0
0
0
0
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L H L
L
L
L
L H L
L
L
(18)
(17) (16)
(15) (14) (13)
(37)
(37)
(12)
(11)
(10)
Normal operation
Stopped
IC test mode
These bits are
normally set to :
TEST0 = 0
TEST1 = 0
TEST2 = 0
(9)
IC internal signals
I/O ports
Control data
0 : input, 1 : output
Normally set to 0.
Charge pump
control
0
1
LSB
D2-31
MSB
L
X’tal-OSC
Buffer output
0
1
Normal operation
Stopped
ALC_ON/OFF
Switch
0
1
ALC_OFF
Normal operation (ALC_ON)
X’tal OSC
Oscillation level
fine adjustment
000
001
010
0 11
100
101
11 0
111
Unlock detection switching
Detection pin output
UL1 UL0
0
0
0
1
1
0
1
1
Dead zone control
DZ1 DZ0 Dead zone mode
DZA
0
0
DZB
0
1
DZC
1
0
DZD
1
1
X’tal OSC Frequency fine adjustment
000
001
010
0 11
100
101
11 0
111
No.A1668-27/40
LV25450PNW
9Bit-DAC temperature characteristics
compensation slope switching
FM AGC ON
0
1
Normal
ON
00
01
10
11
AM AGC ON
0
1
Normal
ON
IN3-1 tuner setting 1
Address 69h, Subaddress[0]
A A A A B B B B IN
3 2 1 0 3 2 1 0
Standard (gradual)
0
0 1 1 0 1 0 0 1
Sub Address Code
D31-01
D31-00
RFDAC2
RFDAC1
RFDAC0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
(21)
2.7V REG ADJ
0 0 -23mV
0 1 (Center value)
1 0 +23mV
1 1 +64mV
(20)
LSB
D31-02
RFDAC3
ANTDAC1
RFDAC4
D31-10
ANTDAC2
D31-03
D31-11
ANTDAC3
RFDAC5
D31-12
ANTDAC4
D31-04
D31-13
ANTDAC5
RFDAC6
D31-14
ANTDAC6
D31-05
D31-15
ANTDAC7
RFDAC7
D31-16
ANTDAC8
D31-06
D31-17
REG_ADJ0
L
Gain Down
Gain Up
RFDAC8
D31-18
0
1
D31-07
D31-19
0
REG_ADJ1
L
IQ mixer gain
adjustment
D31-08
D31-20
L
(22)
ANTDAC0
D31-21
0
L
(27) (26) (25) (24) (23)
D31-09 TUNEROFF
D31-22
DAC9_SW
L
L
D31-23 DAC9_SW2
D31-24
L
D31-25 IQMIX_GAIN
L
IQ_SW
D31-27 FMAGC_ON
L
D31-26
D31-28 AMAGC_ON
0
L
D31-29 NARROW_OFF
(36)
D31-30
MSB
D31-31 Sub-Address
L
Address Code
(19)
Tuner off setting
0
1
Normal operation
Tuner off
IQMIX
phase switching
0
1
IFAGC-Amp
0
1
ON
OFF
Lower
Upper
ANT-DAC
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001000
111111010
111111011
111111100
111111101
111111110
111111111
0.4V
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
7.1V
RF-DAC
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001000
111111010
111111011
111111100
111111101
111111110
111111111
0.4V
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
7.1V
No.A1668-28/40
LV25450PNW
FM-Keyed-AGC operation
0
1
Keyed AGC normal operation
Keyed Wide AGC control function off
IN3-2 tuner setting 2
Address 69h, Subaddress [1]
A A A A B B B B IN
FM-RFAGC operation
0
1
3 2 1 0 3 2 1 0
Normal operation
FET OFF
1
0 1 1 0 1 0 0 1
Sub Address Code
D32-27
D32-26
D32-25
D32-24
D32-23
D32-22
D32-21
D32-20
D32-19
D32-18
D32-17
D32-16
D32-15
D32-14
D32-13
D32-12
D32-11
D32-10
D32-09
D32-08
D32-07
D32-06
D32-05
D32-04
D32-03
D32-02
D32-01
D32-00
0
ADJ_N2
ADJ_N1
ADJ_N0
S_METER4
S_METER3
S_METER2
S_METER1
S_METER0
APF_ADJ3
APF_ADJ2
APF_ADJ1
APF_ADJ0
KEY_AGC3
KEY_AGC2
KEY_AGC1
KEY_AGC0
0
0
0
1
N_AGC3
N_AGC2
N_AGC1
N_AGC0
W_AGC3
W_AGC2
W_AGC1
W_AGC0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
(36) (35) (34)
(33)
(32)
(31)
AM-RF-AGC
amplifier threshold
(steep)
IF AGC clamp variations
correction
000
001
010
011
100
101
110
111
0000
0001
0010
0011
0100
-2dB
↓
↓
Center
↓
↓
↓
+2dB
S-Meter Shift(TSOUT)
0 0 0 0 0 180μA(2.65V)
00001
↓
00010
↓
00011
↓
00100
↓
00101
↓
00110
↓
00111
↓
↓
↓
11010
↓
11011
↓
11100
↓
11101
↓
11110
↓
1 1 1 1 1 245μA(3.3V)
(30)
1011
1100
1101
1110
1111
1.0V
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
2.5V
[AM] RF-AGC
Amp threshold
(gradual)
[FM] All Pass Filter
Steps on the software
0000
0001
0010
0011
0100
0000
1000
0100
1100
0010
0
1
2
3
4
1101
0011
1011
0111
1111
11
12
13
14
15
1011
1100
1101
1110
1111
1.0 +VBE
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
2.5 +VBE
(29)
FM-Keyed
AGC
threshold
0.14V
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
2.2V
Phase shift
trimming
Small
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
LSB
D32-28
W_KEYED
D32-30
D32-29 FMFETOFF
D32-31 Sub-Address
MSB
L
Address Code
(28)
FM/AM-Wide-AGC Sensitivity
0000
0001
0010
0011
0100
1011
1100
1101
1110
1111
0.14V
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
2.57
FM/AM-Narrow-AGC Sensitivity
0000
0001
0010
0011
0100
1011
1100
1101
1110
1111
0.14V
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
2.5V
Large
No.A1668-29/40
LV25450PNW
Control Data Documentation
No.
Control block/data
(1)
Programmable divider data
P0 to P15
DVS
Description
Related data
AM/FM
• Sets the programmable divider's divisor.
This is a binary value in which P0 is the LSB, P15 the MSB.
OSC D1, D2
DVS = 0 : The IC internal PLL IN pin is stopped (pulled down)
WB, OSC DIV
DVS = 1 : The IC internal PLL IN pin is selected
Set divisor (N) : 272 to 65536
Input frequency range : 120 to 270 MHz
* : See the "Programmable Divider Structure" section for more information.
(2)
AM oscillator divisor control
• OSC D1, OSC D2−AM oscillator divisor control
Tuner mode switching
P0 to P15
OSC D2
Divisor
0
0
Divide by 10
0
1
Divide by 8
1
0
Divide by 6
1
1
Divide by 4
OSC D1, OSC D2
(3)
AM/FM
OSC D1
• Tuner mode switching between AM and FM
1 = AM
P0 to P15
0 = FM
OSC D1, D2
AM/FM
(4)
Programmable divider stop
• DVS = 0 : The IC internal PLL-IN pin is stopped (pulled down)
DVS = 1 : The IC internal PLL-IN pin is selected
DVS
Set divisor (N) : 272 to 65536
Input frequency range : 120 to 270 MHz
* : See the "Programmable Divider Structure" section for more information.
(5)
Reference divider data
• Selects the reference frequency.
Reference frequency setting (kHz)
R0 to R3
R3
R2
R1
R0
Crystal : 4.5MHz
0
0
0
0
100
0
0
0
1
50
0
0
1
0
25
0
0
1
1
25
0
1
0
0
12.5
0
1
0
1
6.25
0
1
1
0
3.125
0
1
1
1
3.125
1
0
0
0
10
1
0
0
1
9
1
0
1
0
5
1
0
1
1
1
1
1
0
0
3
1
1
0
1
30
1
1
1
0
Illegal value
1
1
1
1
Illegal value
Continued on next page.
No.A1668-30/40
LV25450PNW
Continued from preceding page.
No.
(6)
Control block/data
Tuner mode switching
AM/FM oscillator divisor
OSC_DIV
WB
Description
Related data
(1) AM/FM/WB oscillator divisor control
P0 to P15
WB
OSC DIV
Divisor
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 1
1
1
Divide by 1
DVS
* : WB: Select 1 for weather band reception
(2) AM oscillator divisor control
OSD D2
OSC D1
Divisor
0
0
Divide by 10
1
0
Divide by 8
0
1
Divide by 6
1
1
Divide by 4
In FM mode, only the WB and OSC DIV bits are valid.
In AM mode, this function is set up by combination of the OSC D2, OSC (however, this is
fixed at the divide-by-2 setting) D1, WB, and the OSC DIV bits.
FM (Japan) : Fixed at the divide-by-3 setting
FM (other regions) : Fixed at the divide-by-2 setting
WB : Fixed at the divide-by-1 setting (OK if WB = 1)
In AM mode, set WB = 0, OSC DIV = 0 for the divide-by-2 setting.
The OSC D2 and OSC D1 bits can be set according to end product needs.
Example : USA : (1) <divide by 2> × (2) <divide by 10> = divide by 20
SW2 : (1) <divide by 2> × (2) <divide by 4> = divide by 8
(7)
FM IQ mixer phase
• FM IQ mixer phase adjustment
OSC_DIV
FM-IQMIX phase_Adjust
adjustment
DELAY_ADJ2
DELAY_ADJ1
DELAY_ADJ0
Adjustment amount
DELAY_ADJ0 to
0
0
0
Small
DELAY_ADJ1
0
0
1
↓
0
1
0
↓
0
1
1
↓
1
0
0
↓
1
0
1
↓
1
1
0
↓
1
1
1
Large
Continued on next page.
No.A1668-31/40
LV25450PNW
Continued from preceding page.
No.
(8)
Control block/data
PLL filter switching mode
Description
Related data
• Switches the PLL filter
AM/FM
PLL filter switching
FMFIL
Filter state
AMFIL
Normal
AM/FM
AM filter
0
OFF
FM filter
ON
1
ON
OFF
Normal mode (MODE = 0)
The filter state is switched in conjunction with the AM/FM bit.
FM mode (AM/FM = 0)
A filter is formed on pins 8 and 11.
Since this filter can be independent of the filter used in AM mode, PLL locking can be
fast.
AM mode (AM/FM = 1)
A filter is formed on pins 9 and 10 and with the two internal switches SW1 and SW2.
An additional filter is added to pin 5 using an internal
resistor and an external capacitor.
VDD
PIN26
+8V
PIN61
CP1
3kΩ
SW2
5kΩ
1kΩ
SW3
SW1
C7
0.01μF
12
13
FM_CP
11
AM_CP
10
AM_FET_OUT
9
FM_FET_OUT
8
FET_GND
VT
7
C10A
1μF
C11A
0.033μF
R7
30kΩ
R11
1.3kΩ
(9)
IC internal signals
I/O ports
Control data
R12
2.2kΩ
C11B
2200pF
• Specifies the I/O direction for the I/O ports
Data = 0 : Input port. The value 0 should be specified in normal operation.
= 1 : Output port. A value of 1 is used for IC testing.
* : This data must be set to 0 at all times other than IC evaluation.
Normally set to 0.
(10)
Crystal oscillator
• Adjusts the crystal 4.5 MHz reference frequency if beating occurs
frequency fine adjustment
data
X_SW_0 to X_SW_2
R0 to R3,
XLVL0 to XLVL2
oscillation
X’tal OSC ADJ [When a 4.5MHz oscillator element is used]
000
High (+100Hz)
001
↓
010
↓
011
4.5MHz (Center value)
100
↓
101
↓
110
↓
111
Low (-100Hz)
Continued on next page.
No.A1668-32/40
LV25450PNW
Continued from preceding page.
No.
Control block/data
(11)
Crystal oscillator oscillation
level
Description
Related data
• Data used to adjust the crystal 4.5MHz oscillation level when the S/N condition is
R0 to R3,
X_SW_0 to
worsening.
adjustment data
X_SW_2
X’tal OSC oscillation level adjustment
XLVL0 to XLVL2
(12)
Crystal oscillator
ACL circuit
000
Low
001
↓
010
↓
011
↓
100
↓
101
↓
110
↓
111
High
• Switches on and off the ALC (Auto level control) in the crystal oscillation circuit. Normally
set to high.
ALC_ON/OFF
ON/OFF switching
switching
ALC_OFF
(13)
DO pin control data
0
ALC_OFF
1
Normal operation (ALC_ON)
UL0, UL1
• Determines the DO pin output.
DO pin control data
ULD
ULD
DO pin
0
Low when not locked.
1
Open
* In such a case that the DO pin is multiplexed with EEPROM, transmit a setting data that
opens the LV25450PNW DO pin control just before reading out the EEPROM data.
The following item (14) must also be set when monitoring the unlock detection signal.
(14)
Unlock state detection data
• Selects the phase error (øE) detection width used to judge the PLL locked state.
ULD
If a phase error in excess of the øE detection width from the table below occurs, the
UL0, UL1
PLL is seen as being in the unlocked state.
When the PLL is seen as being unlocked, the detection pin (DO) is set low.
φE detection width
UL1
UL0
0
0
Stopped
Open
0
1
0
φE is output directly
1
0
±0.5μs
φE is delayed by 1 to 2 ms.
1
1
±1μs
φE is delayed by 1 to 2 ms.
≈
φE
DO
Detection pin output
Delay
≈
1 to 2ms
Unlock state output
(15)
Crystal oscillator buffer
• Stops the crystal oscillator buffer output.
output stop switching
1 bit
Crystal oscillator
buffer switching
TWO_DOFF
(16)
Phase comparator control
data
DZ0, DZ1
0
Normal operation
1
Stopped
• Controls the phase comparator's dead zone.
DZ1
DZ0
Dead zone mode
0
0
DZA
0
1
DZB
1
0
DZC
1
1
DZD
The DZA setting is selected after the power-on reset.
Continued on next page.
No.A1668-33/40
LV25450PNW
Continued from preceding page.
No.
(17)
Control block/data
Charge pump control data
Description
Related data
• Forcibly sets the charge pump output to the low level (VSS level).
DLC = 1 : Low level
DLC
DLC = 0 : Normal operation
* : If the IC deadlocks with VCO oscillator stopped with the VCO control voltage (Vtune) at
0 V, the deadlock can be resolved by setting the charge pump output to the low level
and setting Vtune to VCC.
This item is set to the normal operation state after the power-on reset.
(18)
IC internal signal I/O port
• Specifies the I/O direction for the I/O ports
control data
Data = 0 : Input port. The value 0 should be specified in normal operation.
TEST0, TEST1, TEST2
= 1 : Output port. A value of 1 is used for IC testing.
* : This data must be set to 0 at all times other than IC evaluation.
(19)
RF tuning D/A converter
• Applies a control voltage to the RF tuning circuit (varactor).
DAC9_SW2,
DAC9_SW
output
9 bit
RFDAC0 to RFDAC8
(20)
(21)
Tuner off setting
• Set the IC to tuner off mode.
TUNEROFF
1 bit
Antenna tuning D/A
Tuner OFF mord
0
Normal operation
1
Tuner-OFF
• Applies a control voltage to the antenna tuning circuit (varactor).
DAC9_SW2,
DAC9_SW
converter output
9 bit
ANTDAC0 to ANTDAC8
(22)
2.7V REG
• Adjusts the 2.7 V regulator
ADJ
2.7V REG ADJ
(23)
REG_ADJ0
00
-23mV
REG_ADJ1
01
(Center value)
10
+23mV
11
+64mV
RF block tuning circuit
• RF block tuning circuit temperature characteristics compensatioin slope switching bits
temperature characteristics
compensatioin slope
RFDAC0 to
RFDAC8,
9bit temperature characteristics compensatioin slope switching
switching
00
data
01
ANTDAC0 to
ANTDAC8
10
DAC9_SW2
11
Standard (Gradual)
DAC9_SW
(24)
IQ mixer gain adjustment
• Data used to switch FM IQ mixer gain.
data
1 bit
IQMIX_GAIN
(25)
IQ mixer phase switching
IQ mixer gain adjustment
0
Gain Down (with RF-Amp)
1
Gain Up (without RF-Amp)
• Data used to switch FM IQ mixer phase.
data
1 bit
IQ_SW
(26)
Forced AGC (AM/FM)
IQ mixer phase switching
0
Lower
1
Upper
• Data used to operate the forced AGC circuit (antenna dumping).
switching data
FMAGC_ON : FM AGC ⎡0⎦ = NORMAL, ⎡1⎦ = ON
FMAGC_ON
AMAGC_ON : AM AGC ⎡0⎦ = NORMAL, ⎡1⎦ = ON
AMAGC_ON
Each 1 bit
Continued on next page.
No.A1668-34/40
LV25450PNW
Continued from preceding page.
No.
Control block/data
(27)
IF AGC amplifier circuit off
Description
Related data
• Switches off the IF AGC amplifier circuit.
switching
1 bit
IF AGC amplifier
NARROW_OFF
(28)
(29)
(30)
0
ON (normal operation)
1
OFF
AM/FM wide AGC setting
• Sets the AM/FM wide AGC sensitivity.
W_AGC0 to W_AGC3
4 bit
AM/FM narrow AGC setting
• Sets the AM/FM narrow AGC sensitivity.
N_AGC0 to N_AGC3
4 bit
AM RF AGC amplifier
• Sets the AM RF AGC amplifier circuit threshold (steep) and the FM Keyed AGC
threshold (steep) and
AM/FM
AM/FM
AM/FM
sensitivity.
Keyed AGC setting data
4 bit
KEY_AGC0 to KEY_AGC3
(31)
AM RF AGC amplifier
AM-RF-AGC
FM-Keyed
Amp threshold (steep)
AGC threshold
0000
1.0V
0.14V
0001
↓
↓
0010
↓
↓
0011
↓
↓
0100
↓
↓
•
↓
↓
•
↓
↓
1011
↓
↓
1100
↓
↓
1101
↓
↓
1110
↓
↓
1111
2.5V
2.2V
• Data used to set the AM RF AGC amplifier threshold (gradual) and the All Pass Filter.
AM/FM
threshold (gradual) and All
Pass Filter setting data
4 bit
APF_ADJ0 to APF_ADJ3
AM-RF-AGC
FM-Keyed AGC threshold
phase shift
Amp threshold
the software
trimming
(gradual)
0000
1.0+VBE
0000
0
Small
0001
↓
1000
1
↓
0010
↓
0100
2
↓
0011
↓
1100
3
↓
0100
↓
0010
4
↓
•
↓
•
•
↓
•
↓
•
•
↓
1011
↓
1101
11
↓
1100
↓
0011
12
↓
1101
↓
1011
13
↓
1110
↓
0111
14
↓
1111
2.5V+VBE
1111
15
Large
(32)
S-meter shifter control
• Controls the FM S-meter shifter circuit output value.
S_METER0 to S_METER4
5 bit
(33)
Analog (narrow) IF AGC
• Corrects the sample-to-sample variations in the IF AGC clamp circuit.
clamp variations correction
Amount of correction : ±2 dB
ADJ_N0 to ADJ_N2
3 bit
(34)
FM PIN diode forced on
• Forcibly sets the FM PIN diode to the on state.
state bit
1 bit
FMFETOFF
Continued on next page.
No.A1668-35/40
LV25450PNW
Continued from preceding page.
No.
(35)
Control block/data
Description
LSI test data
• Modifies the keyed AGC connection circuit.
W_KEYED
1 bit
Related data
Keyed AGC switch
0
Wide + narroww
1
Narrow only
(36)
Sub-Address
• Sub-code address
(37)
OFFSET_SW
• The DC offset was given to the differential motion part of LO-OSC for the IRR
Each 1 bit
improvement, and the function to correct Duty was added.
It is control Bit to stop this function, and to switch in a state past (The offset giving is not
done).
1BITbit
Programmable Divider Structure
4 bits
12 bits
fvco/N
PLL IN
Swallow
Counter
DVS
Programmable
Divider
PD
φE
ferf
fvco = ferf × N
DVS
Set divisor (N)
Input frequency range (f (MHz))
IC internal PLL IN pin
1
272 to 65535
120 ≤ f ≤ 270
Selected
0
-
-
Stopped
* : Since the IC is closed internally, the input sensitivity is not specified.
No.A1668-36/40
LV25450PNW
Phase Comparator and Charge Pump Circuits
(1) Phase comparator and charge pump operation
In the PLL circuit block shown in figure 1, the phase comparator compares the phases of the reference frequency (fr)
and the comparison frequency (fp), and outputs the amount of the phase difference from the charge pump.
Figure 1 PLL Circuit Block
RF
Mixer
Leakage during
strong-field input
fr
Reference Divider
Phase
Detector
Programmable Divider
Charge
Pump
LPF
VCO
fp
Figure 2 shows the phase comparator/charge pump output characteristics. The phase comparator outputs a voltage Vφ
that is proportional to the phase difference φ between fr and fp. The phase comparator's characteristics can be
switched by changing the phase comparator dead zone mode setting. The phase comparator can be set to modes (DZA,
DZB) in which both the charge pump p-channel and n-channel sides are turned on when the phase difference is small,
or can be set to a mode (DZD) that does not output the phase difference when the phase difference is small.
Figure 2 Phase Comparator/Charge Pump Characteristics
Vφ[V]
Vφ[V]
fp > fr
D ZA
mode
fp > fr
D ZB
mode
φ err[ns]
fr > fp
Dead Zone(--)
φ err[ns]
Vφ[V]
D ZC
mode
Dead Zone(-)
fr > fp
Vφ[V]
fp > fr
D ZD
mode
φ err[ns]
fp > fr
φ err[ns]
fr > fp
Dead Zone ≈ 0
fr > fp
Dead Zone(+)
No.A1668-37/40
LV25450PNW
(2) Dead zone mode characteristics and selection criteria
This section describes the characteristics of each dead zone mode and the criteria for selecting that mode.
(1) DZA mode
In DZA mode, the correction signal is output from the charge pump even if the reference frequency (fr) and
comparison frequency (fp) match. This results in excellent signal-to-noise ratio characteristics. However, due to
the generation of reference frequency component sidebands, beating may occur in the presence of a strong input
signal. This is because the PLL loop responds sensitively to leakage components from the RF stage through the
mixer and this modulates the VCO.
(2) DZB mode
Like DZA mode, in DZB mode the correction signal is output from the charge pump even if the reference
frequency (fr) and comparison frequency (fp) match. However, the correction signal voltage is lower in DZB
mode than in DZA mode. The feature of this mode is that it provides a better signal-to-noise ratio than DZC or
DZD mode yet is less susceptible to beating than DZA mode.
(3) DZC mode
In DZC mode, a correction signal proportional to the phase difference between the reference frequency (fr) and
comparison frequency (fp) is output from the charge pump. A small amount of noise may occur when the phase
difference is close to 0 ns. Since the signal-to-noise ratio may degrade significantly at low temperatures (under
-30°C), this mode should not be used.
(4) DZD mode
In DZD mode, a correction signal proportional to the phase difference between the reference frequency (fr) and
comparison frequency (fp) is output from the charge pump. The correction signal is not output when the phase
difference is in the vicinity of ± <a few ns>. As a result the signal-to-noise ratio is worse than the other modes, but
the occurrence of beating is suppressed.
Power supply turning on/cutting timing and power-on reset
Recommended operating conditions/Ta=25°C, GND=0V
Parameter
Symbol
Ratings
Conditions
min
Operation power-supply voltage
Internal logic voltage
Power supply turning on time(8.0V → 5.0V)
Internal register maintenance voltage
typ
Unit
max
Vcop_H
PIN 3,27,35,54,55,61
7.5
8.5
V
Vcop_L
PIN 16,25,41
4.5
5.5
V
VREG3
PIN 26
2.7
3.3
V
VREG4
PIN 15
3.7
4.3
V
10
100
ms
T7
Vhmin3
PIN 26 *1
VREG3
2.2
V
Vhmin4
PIN 15 *1
V
VREG4
2.2
Internal register reset voltage
Voff
PIN 16,25,41 *1
0
0.2
V
Internal register reset power supply start-up time
tPOR
PIN 16,25,41 *1
0.05
3
ms
10
100
ms
Power supply turning on time(5.0V → 8.0V)
T14
*1: Design reference value
No.A1668-38/40
Pin_D2
1SV251
C103 C105
4pF 5pF
C58B
0.022μF
R56
30kΩ
C56
1000pF
R64
C63 100Ω
0.1μF
R107B
100kΩ
R107A
100kΩ
100pF
R62C
180Ω
R635
180Ω
R63M
180Ω
C107
1000pF
coil
R57
30kΩ
C61
0.022μF
15pF
C57
1000pF
C62C
1000pF
C52
0.022μF
R52B
470Ω
C50
10μF
36pF
54
FE_VCC8V
IN1
IN2
C60
0.1μF AM_MIX
AM_MIX
RF_DAC
61
60
59
58
+
OSC_B
OSC_C
6
Local_OSC
GND
R4
30kΩ
KV1862
SW
C15
0.22μF
7
8
R11
10
C8
0.01μF
9
SW 10kΩ
3kΩ
+8V
AM_Filer
330pF
C4
C5
2pF
3pF
C45
FM OSC
4
5
37
FM_RF_AGC
36
35
FM
amp
AM
amp
VREG27
C10A
1μF
12
CP1
14
C11B
2200pF
33
C15
0.22μF
15
VREG4
16
BUFF
BUFF
bus
VREG3
Analos-IF AGC
34
XTAL_DSC
C11A
0.033μF
13
R10
R11
1.3kΩ 2.2kΩ
11
AM_CP OUT
C38
1000pF
C48
1pF
3
38
swallow programable phase reference
counter
divider
detecter counter
IN1/IN2
IN3-2
IN3-1
VSM
39
FM_CP
OUT
C2
2.2μF
2
div
1/12,1/8 OSC
1/6,1/4 BUFFER
K AGC
40
VREG 4V
C107
1000pF
R2
220kΩ
1
AM MIX
N AGC
W AGC
RF AGC
IQ MIX
ANT d
N AGC
ANT D
57 RF_DAC
55
MIX_OUT2
R62 ANT_DAC
56 ANT_DAC
30Ω
C54
C62
10pF FM_MIX1
IN 62
C1000
8pF FM_MIX2
IN 63
VCD2 C63
SVC208 10pF
FM_ANTD
64
L72
C62
0.022μF
MIX_OUT1
AM_ANT_D
52
C53
30pF N_AGC
53
AM 1st AMP
41
R34
15kΩ
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
6
5
DI
30Ω
C107
0.1μF
1
2
3
4
30kΩ
CS
SK
DO
TEST
C17
10pF
C18
15pF
snd
GND
KTAL_IN
4.5M
KTAL_OUT
XTAL_GND
XTAL_OSC
OUT2
CE
DI
CL
DO
C25
1μF
C26
Disital VCC 0.22μF
VREG 3V
IFAGC_VCCB
AGC_DAC_S
C27A
10μF
280Ω
10.7OUTN
IFAGC_GND
280Ω
C35A
10μF
C41A
10μF
10.7OUTP
DIV_OUT_IF
EEPROM
C16
0.1μF 7 NC
VCC
8
XTAL_VCC
VCC8V
0.15μH
C101
18pF
D70
1SV251
C101
0.022μF
C58A
100μF +
Loding coil
+
+
-
42
AM_ANALOG_IN
FM_IN
AM_IN
R101G
1M
IF_N_IN
Bypass
FM cut
6.8μH
IF_N_IN1
W AGC
VREG49
RF AGC
IF_OUT
L70B
Address_SW
47μH
43
AM_NAGC
44
Analog
VCC
CPH5905
45
C34
0.22μF
IFAGC
Driver
VCC
VREG49
AM_ANALOG
_IN BYPASS
L49A
1mH
46
C36
0.1μF
IFAGC
Driver
GND
R49C
220Ω
47
Analog
GND
48
C38
0.022μF
VSM_AC
49
C49
0.022μF
AM_RF_AGC
50
C51 RF_AGC
1μF BYPASS
51
+
R42B
VREG27
AM_WAGC
C45
0.1μF
R42
3.9kΩ
XTAL_16k
VSM_DC
R49
470Ω
C47
0.022μF
CF_180k
R44
1.8kΩ
C35B
0.022μF
C41B
0.022μF
C16A
0.022μF
47kΩ
C27B
0.022μF
C29
0.022μF
C30
0.022μF
VCCD5V
+
+
+
C16B
10μF
CS
+
XTAL_VCC5V
XTAL_OSC OUT2
CE
DI
CL
DO
pull up
IF AGC_VCC8V
AGC_DAC_S
10.7M_OUT_M
10.7M_OUT_P
DIV_OUT_IF
IFAGC_Driver
VCC8V
VCCA5V
LV25450PNW
Sample Application Circuit
Disital GND
AM_FEL_IN
FM_FEL_IN
FET_GND
FET_GND
No.A1668-39/40
LV25450PNW
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This catalog provides information as of March, 2010. Specifications and information herein are subject
to change without notice.
PS No.A1668-40/40