TDA7498E 160-watt + 160-watt dual BTL class-D audio amplifier Preliminary data Features ■ 160-W + 160-W output power at THD = 10% with RL = 4 Ω and VCC = 36 V ■ 1 x 220 W output power mono parallel BTL at THD = 10% with RL = 3 Ω and VCC = 36 V ■ Wide-range single-supply operation (14 - 36 V) ■ High efficiency (η = 85%) ■ Parallel BTL function using the MODE pin ■ Four selectable, fixed gain settings of nominally 23.8 dB, 29.8 dB, 33.3 dB and 35.8 dB ■ Differential inputs minimize common-mode noise ■ Standby and mute features ■ Smart protection ■ Thermal overload protection ■ Small offset less than 20 mV Table 1. PowerSSO36 with exposed pad up Description The TDA7498E is a dual BTL class-D audio amplifier with a single power supply designed for home systems and active speaker applications. It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Device summary Order code Operating temp. range Package Packaging TDA7498E 0 to 70 °C PowerSSO36 (EPU) Tube TDA7498ETR 0 to 70 °C PowerSSO36 (EPU) Tape and reel December 2011 Doc ID 022595 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/20 www.st.com 20 Contents TDA7498E Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4 5 2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 For RL = 4 Ω, stereo configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 For RL = 3 Ω, mono BTL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Stereo and mono BTL operation selection using the MODE pin . . . . . . . 16 5.2 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 Smart protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 Doc ID 022595 Rev 1 TDA7498E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuit stereo application and mono BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FFT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 022595 Rev 1 3/20 Device block diagram 1 TDA7498E Device block diagram Figure 1 shows the block diagram of one of the two identical channels of the TDA7498E. Figure 1. 4/20 Internal block diagram (showing one channel only) Doc ID 022595 Rev 1 TDA7498E Pin description 2 Pin description 2.1 Pinout Figure 2. Pin connections (top view, PCB view) SUB_GND 1 OUTPB 2 34 VREF OUTPB 3 33 INNB PGNDB 4 32 INPB PGNDB 5 31 MODE PVCCB 6 30 GAIN PVCCB 7 29 SVR OUTNB 8 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 OUTNA 36 VSS 35 SVCC VDDS 11 25 SYNCLK PVCCA 12 24 ROSC PVCCA 13 23 INNA PGNDA 14 22 INPA EP, exposed pad Connect to ground 21 MUTE 20 STBY PGNDA 15 OUTPA 16 OUTPA 17 19 VDDPW Doc ID 022595 Rev 1 PGND 18 5/20 Pin description 2.2 TDA7498E Pin list Table 2. Pin description list Number 6/20 Name Type Description 1 SUB_GND PWR Connect to the frame 2,3 OUTPB O Positive PWM for right channel 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN I Gain setting input 31 MODE I Enables stereo or mono BTL mode of operation 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground Doc ID 022595 Rev 1 TDA7498E Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage for pins PVCCA, PVCCB, SVCC 40 V VI Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN, MODE -0.3 to 4.0 V Tj Operating junction temperature 0 to 150 °C Top Operating ambient temperature 0 to 70 °C Tstg Storage temperature -40 to 150 °C 3.2 Thermal data Table 4. Thermal data Symbol Rth j-case Parameter Thermal resistance, junction to case 3.3 Recommended operating conditions Table 5. Recommended operating conditions Symbol Min - Parameter Typ Max 3.0 Min Typ Unit °C/W Max Unit VCC Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 36 V Tamb Ambient operating temperature 0 - 70 °C Doc ID 022595 Rev 1 7/20 Electrical specifications 3.4 TDA7498E Electrical specifications Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 36 V, RL = 4 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 23.6 dB Tamb = 25 °C. Table 6. Electrical specifications Symbol Parameter Condition Min Typ Max Unit Iq Total quiescent current No LC filter, no load - 60 mA IqSTBY Quiescent current in standby - - 1 µA VOS Output offset voltage Vi = 0 Av = 23.6 dB, no load -20 - 20 mV IOCP Overcurrent protection threshold RL = 0 Ω 10 11 14 A Tj Junction temperature at thermal shutdown - 140 150 160 °C Ri Input resistance Differential input 69 - kΩ VUVP Undervoltage protection threshold - - - 8 V High side - 0.15 - RdsON Power transistor on resistance Low side - 0.15 - THD = 10% - 160 - Po Output power THD = 1% - 125 - Parallel BTL (mono) output power, THD = 10% RL = 3 ohm, Vcc = 36 V THD = 1% - 220 - Po - 170 - η Efficiency - 85 - % THD Total harmonic distortion - 0.05 - % GV Ω W Po = 1 W W GAIN0 < 0.25*VDD 23.8 0.25*VDD < GAIN < 0.5*VDD 29.8 0.5*VDD < GAIN < 0.75*VDD 33.3 GAIN > 0.75*VDD 35.8 Closed-loop gain dB ΔGV Gain matching - -1 - 1 dB CT Crosstalk f = 1 kHz, Po = 1 W 50 60 - dB Vn Inputs shorted and to Ground A curve 231 µV Inputs shorted and to Ground f = 20 Hz to 20 kHz 400 µV Total output noise SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF - 55 - dB Tr, Tf Rise and fall times - - 35 - ns fSW Switching frequency Internal oscillator 240 310 400 kHz fSWR Output switching frequency range With internal oscillator by changing Rosc(1) 240 - 8/20 Doc ID 022595 Rev 1 kHz TDA7498E Table 6. Symbol Electrical specifications Electrical specifications (continued) Parameter VinH Digital input high (H) VinL Digital input low (L) Min Typ Max 2.0 - - - - 0.8 - Function mode Standby & mute & play Mute attenuation AMUTE 1. fSW = Condition 106 Unit V STBY < 0.5 V, MUTE = X StandBy STBY > 2.5 V ; MUTE < L Mute STBY > 2.5 V, MUTE > H Play VMUTE < L, VSTBY = H - 75 - dB / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 3) Doc ID 022595 Rev 1 9/20 10/20 3 L- Doc ID 022595 Rev 1 PS C29 2.2uF 1 3 MUTE IC2 IN C12 GND C9 100nF 2 2 1uF R4 6.8k D1 18V R8 VCC 33k R19 120k 33k R2 3V3 POWER SUPPLY 2 1 L4931CZ33 3 1 3 S1 STBY S2 + + C7 2.2uF 16V C15 2.2uF 16V C14 1nF C13 1nF C10 100nF TDA7498E IC1 TDA7498E (PSSO36) CLASS-D AMPLIFIER 20 STBY 21 MUTE 33 INNB 32 INPB 36 VSS 35 SVCC 31 MODE 30 GAIN 24 ROSC 25 SYNCLK 18 PGND 19 VDDPW C19 D7 8 SVR 29 VREF 34 OUTNB 9 C16 10uF 10V C17 10uF 10V D9 D8 VCC PGNDB OUTNB C21 330pF 4 1uF C31 R5 22R D6 VCC 5 100nF 6 7 2 3 D5 D4 VCC PGNDB PVCCB PVCCB OUTPB OUTPB OUTNA 11 OUTNA 10 C27 330pF C30 1uF L4S L4 C28 220nF C22 1uF C20 220nF C18 C23 + 2200uF 50V 220nF C24 1uF C26 220nF JUMPER J5 J6,J3,J8 MODE STEREO MONO MODE SETTING Optional components or circuitry L2S L2 MONO OUT WR- WL- L1S C32 + 2200uF 50V L1 L3 L3S MONO OUT WR+ WL+ VCC R15 GND VCC RJ14 1 J11 J12 35.6dB J10 J9 JUMPER 33.1dB 29.6dB 23.6dB GAIN J13 2 R-OUTPUT Load=4 ohm R+ 2 L- LOUTPUT Load=4 ohm L+ 1 GAIN SETTING 8R R18 220nF C43 220nF C42 8R R17 J2 2 1 8R R16 220nF C41 220nF C40 8R Test circuit stereo application and mono BTL mode 1uF J5 J10 J9 J12 J6 VDDS VDDS J11 R3 39K SYNC DIAG PVCCA 13 PVCCA 12 100nF C25 22R R6 D3 D2 Figure 3. C11 R12 100k 100k R11 C8 100nF 100nF C6 47k 28 DIAG PGNDA 15 PGNDA 14 OUTPA 17 OUTPA 16 Test circuit OUT J4 100k 2 J8 For Single-Ended Input and MONO Config VDDS R10 1 R9 180K Q1 KTC3875(S) 3 R13 FREQUENCY SHIFT 47k R14 PS 100k R7 22R R1 26 VDDS 27 SGND 23 INNA 22 INPA SUB_GND 3.5 3V3 MONO Config J3 L+, L- Only INPUT MONO 2 R+ 1 R- For Single-Ended J7 Input 100nF INPUT 4 L+ C5 J1 VDDS C4 1nF 1uF C2 C3 1nF 1uF C1 1 Electrical specifications TDA7498E Characterization curves 4 TDA7498E Characterization curves Unless otherwise stated, measurements were made under the following conditions: Vcc = 36 V, f = 1 kHz , GV = 23.6 dB, Rosc = 39 kΩ, Cosc = 100 nF, Tamb = 25 °C. 4.1 For RL = 4 Ω, stereo configuration Figure 4. Output power vs. supply voltage 11/20 Doc ID 022595 Rev 1 Characterization curves Figure 5. THD vs. output power Figure 6. THD vs. frequency 12/20 TDA7498E Doc ID 022595 Rev 1 TDA7498E Characterization curves Figure 7. FFT performance Figure 8. Crosstalk vs. frequency Doc ID 022595 Rev 1 13/20 Characterization curves TDA7498E 4.2 For RL = 3 Ω, mono BTL configuration Figure 9. Output power vs. supply voltage 14/20 Doc ID 022595 Rev 1 TDA7498E Characterization curves Figure 10. THD vs. output power Figure 11. THD vs. frequency Doc ID 022595 Rev 1 15/20 Application information TDA7498E 5 Application information 5.1 Stereo and mono BTL operation selection using the MODE pin The TDA7498E can be used in stereo applications or mono BTL applications. Connecting the MODE pin to the VDDS pin configures the device in mono BTL. The output of the two channels can be paralleled. When the MODE pin is connected to ground or floating (pulled down internally) the device works as a stereo amplifier. 5.2 Gain setting The gain of the TDA7498E is set by GAIN (pin 30). Table 7. Gain settings GAIN0 5.3 Total Gain Application suggestion VGAIN < 0.25*VDDS 23.6 dB GAIN pin connected to SGND 0.25*VDDS < VGAIN < 0.5*VDDS 29.6 dB Rc10 = Rc11= Rc12 = 100 K max 0.5*VDDS < VGAIN < 0.75*VDDS 33.1 dB Rc10 = Rc11 = Rc12 = 100K max VGAIN > 0.75*VDDS 35.6 dB GAIN pin connected to VDDS Smart protection To avoid dynamic impedance drop, two overcurrent thresholds are set. The first threshold is for the overcurrent limit. The device limits the output current to the first threshold but does not shut down the PWM outputs. If the device is shorted and at least one of the two output currents reaches the second threshold, the device is shut down immediately. The device will recover automatically when the fault is removed from the BTL outputs. 16/20 Doc ID 022595 Rev 1 TDA7498E 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. The TDA7498E comes in a 36-pin PowerSSO package with exposed pad up. Figure 12 shows the package outline and Table 8 gives the dimensions. Table 8. PowerSSO36 EPU dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees - - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 Doc ID 022595 Rev 1 17/20 TDA7498E Figure 12. PowerSSO36 EPU outline drawing h x 45° Doc ID 022595 Rev 1 Package mechanical data 18/20 TDA7498E 7 Revision history Revision history Table 9. Document revision history Date Revision 12-Dec-2011 1 Changes Initial release. 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