SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y 14 1B 1A NC VCC 4B 1 1Y NC 2A NC 2B 13 4B 2 3 12 4A 4 11 4Y 10 3B 9 3A 5 6 7 8 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1 SN54AHC132 . . . FK PACKAGE (TOP VIEW) SN74AHC132 . . . RGY PACKAGE (TOP VIEW) VCC 1A 1B 1Y 2A 2B 2Y GND D 3Y D Same Pinouts as ’AHC00 Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1A D D D Operating Range 2-V to 5.5-V VCC Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity GND D D NC – No internal connection description/ordering information The ’AHC132 devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic. ORDERING INFORMATION TOP-SIDE MARKING QFN – RGY Tape and reel SN74AHC132RGYR HA132 PDIP – N Tube SN74AHC132N SN74AHC132N Tube SN74AHC132D Tape and reel SN74AHC132DR SOP – NS Tape and reel SN74AHC132NSR AHC132 SSOP – DB Tape and reel SN74AHC132DBR HA132 TSSOP – PW Tape and reel SN74AHC132PWR HA132 TVSOP – DGV Tape and reel SN74AHC132DGVR HA132 CDIP – J Tube SNJ54AHC132J SNJ54AHC132J CFP – W Tube SNJ54AHC132W SNJ54AHC132W LCCC – FK Tube SNJ54AHC132FK SNJ54AHC132FK SOIC – D –40°C to 85°C –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA AHC132 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 description/ordering information (continued) Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. FUNCTION TABLE (each gate) INPUTS OUTPUT Y A B H H L L X H X L H logic diagram, each gate (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 recommended operating conditions (see Note 4) SN54AHC132 SN74AHC132 MIN MAX MIN MAX UNIT VCC VI Supply voltage 2 5.5 2 5.5 V Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC –50 0 VCC –50 mA IOH VCC = 2 V VCC = 3.3 V ± 0.3 V High-level output current VCC = 5 V ± 0.5 V VCC = 2 V IOL VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V Low-level output current –4 –4 –8 –8 50 50 4 4 8 8 V mA mA mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TA = 25°C TYP MAX SN54AHC132 MIN MAX SN74AHC132 MIN MAX VT+ Positive-going input threshold voltage 3V 1.2 2.2 1.2 2.2 1.2 2.2 4.5 V 1.75 3.15 1.75 3.15 1.75 3.15 5.5 V 2.15 3.85 2.15 3.85 2.15 3.85 VT– Negative-going input threshold voltage 3V 0.9 1.9 0.9 1.9 0.9 1.9 4.5 V 1.35 2.75 1.35 2.75 1.35 2.75 5.5 V 1.65 3.35 1.65 3.35 1.65 3.35 3V 0.3 1.2 0.3 1.2 0.3 1.2 4.5 V 0.4 1.4 0.4 1.4 0.4 1.4 5.5 V 0.5 1.6 0.5 1.6 0.5 1.6 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 3V 2.58 2.48 2.48 4.5 V 3.94 3.8 3.8 ∆VT Hysteresis (VT+ – VT– T ) IOH = –50 mA VOH IOH = –4 mA IOH = –8 mA IOL = 50 mA VOL IOL = 4 mA IOL = 8 mA II ICC VI = 5.5 V or GND VI = VCC or GND, IO = 0 UNIT V V V V 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 V 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1* ±1 mA 2 20 20 mA 10 pF 5.5 V Ci VI = VCC or GND 5V 1.9 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC132 SN74AHC132 MIN MAX MIN MAX 5.6* 11.9* 1* 14* 1 14 5.6* 11.9* 1* 14* 1 14 7.6 15.4 1 17.5 1 17.5 7.6 15.4 1 17.5 1 17.5 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC132 SN74AHC132 MIN MAX MIN MAX 3.9* 7.7* 1* 9* 1 9 3.9* 7.7* 1* 9* 1 9 5.3 9.7 1 11 1 11 5.3 9.7 1 11 1 11 UNIT ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 5) SN74AHC132 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.45 0.8 V Quiet output, minimum dynamic VOL –0.35 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.8 High-level dynamic input voltage V 3.5 VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. V 1.5 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 11 pF SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AHC132D ACTIVE SOIC D 14 SN74AHC132DBR ACTIVE SSOP DB SN74AHC132DBRE4 ACTIVE SSOP SN74AHC132DBRG4 ACTIVE SN74AHC132DE4 50 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132DGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AHC132NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AHC132NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHC132RGYR ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74AHC132RGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 19-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AHC132DBR DB 14 MLA 330 16 8.2 6.6 2.5 12 16 Q1 SN74AHC132DGVR DGV 14 MLA 330 12 6.8 4.0 1.6 8 16 Q1 SN74AHC132DR D 14 MLA 330 16 6.5 9.0 2.1 8 16 Q1 SN74AHC132NSR NS 14 MLA 330 16 8.2 10.5 2.5 12 16 Q1 SN74AHC132PWR PW 14 MLA 330 12 7.0 5.6 1.6 8 12 Q1 SN74AHC132RGYR RGY 14 MLA 180 12 3.85 3.85 1.35 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74AHC132DBR DB 14 MLA 342.9 336.6 28.58 SN74AHC132DGVR DGV 14 MLA 338.1 340.5 20.64 SN74AHC132DR D 14 MLA 342.9 336.6 28.58 SN74AHC132NSR NS 14 MLA 342.9 336.6 28.58 SN74AHC132PWR PW 14 MLA 338.1 340.5 20.64 SN74AHC132RGYR RGY 14 MLA 190.0 212.7 31.75 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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