Data Sheet April 2001 Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Features ■ Pin equivalent to the general-trade 26LS32 device, with improved speed, reduced power consumption, and significantly lower levels of EMI ■ High input impedance approximately 8 kΩ ■ Four line receivers per package ■ 400 Mbits/s maximum data rate when used with Agere Systems Inc. data transmission drivers ■ Meets enhanced small device interface (ESDI) standards ■ 4.0 ns maximum propagation delay ■ <0.20 V input sensitivity ■ −1.2 V to +7.2 V common-mode range ■ ■ −40 °C to +125 °C ambient operating temperature range (wider than the 41 Series) Single 5.0 V ± 10% supply ■ Output defaults to logic 1 when inputs are left open* ■ Available in four package types ■ Lower power requirement than the 41 Series Description These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. All devices in this family have four receivers with a common enable control. These receivers are pin equivalent to the general-trade 26LS32, but offer increased speed and decreased power consumption. They replace the Agere 41 Series receivers. * This feature is available on BRF1A and BRF2A. The BRF1A device is the generic receiver in this family and requires the user to supply external resistors on the circuit board for impedance matching. The BRF2A is identical to the BRF1A, but has an electrostatic discharge (ESD) protection circuit added to significantly improve the ESD human-body model (HBM) characteristics on the differential input terminals. The BRS2B is identical to the BRF2A, but has a preferred state feature that places the output in the high state when the inputs are open, shorted to ground, or shorted to the power supply. The BRR1A is equivalent to the BRF1A, but has a 110 Ω resistor connected across the differential inputs. This eliminates the need for an external resistor when terminating a 100 Ω impedance line. This device is designed to work with the DP1A or PNPA in point-to-point applications. The BRT1A is equivalent to the BRF1A; however, it is provided with a Y-type resistor network across the differential inputs and terminated to ground. The Y-type termination provides the best EMI results. This device is not recommended for applications where the differences in ground voltage between the driver and the receiver exceed 1 V. This device is designed to work with the DG1A or PNGA in point-topoint applications. The powerdown loading characteristics of the receiver input circuit are approximately 8 kΩ relative to the power supplies; hence, they will not load the transmission line when the circuit is powered down. For those circuits with termination resistors, the line will remain impedance matched when the circuit is powered down. The packaging options that are available for these quad differential line drivers include a 16-pin DIP; a 16-pin, J-lead SOJ; a 16-pin, gull-wing small-outline integrated circuit (SOIC); and a 16-pin, narrow-body, gull-wing SOIC. Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Pin Information AI AI 16 VCC 1 A AI 15 DI 2 D 16 VCC 1 A AI 2 D AI 16 VCC 1 15 DI AI 2 14 DI AO 3 A 15 DI D 14 DI AO 3 4 13 DO E1 4 13 DO E1 4 13 DO BO 5 12 E2 BO 5 12 E2 BO 5 12 E2 BI 6 11 CO BI 6 11 CO BI 6 BI 7 10 CI BI 7 10 CI BI 7 GND 8 CI GND 8 CI GND 8 AO 3 E1 B C 9 B C 9 B 11 CO C 10 CI 9 BRR1A BRF1A BRF2A BRS2B 14 DI CI BRT1A 12-2281.a(F) Figure 1. Quad Differential Receiver Logic Diagrams Table 1. Enable Truth Table E1 E2 Condition 0 1 0 1 0 0 1 1 Active Active Disabled Active Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Power Supply Voltage Ambient Operating Temperature Storage Temperature Symbol Min Max Unit VCC TA Tstg — −40 −40 6.5 125 150 V °C °C Electrical Characteristics For electrical characteristics over the temperature range, see Figure 7 through Figure 10. Table 2. Power Supply Current Characteristics See Figure 7 for variation in ICC over the temperature range. TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V. Parameter Symbol Min Typ Max Unit Power Supply Current (VCC = 5.5 V): All Outputs Disabled All Outputs Enabled ICC ICC 30 20 45 32 mA mA 2 Agere Systems Inc. Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Electrical Characteristics (continued) Table 3. Voltage and Current Characteristics For variation in minimum VOH and maximum VOL over the temperature range, see Figure 8. TA = –40 °C to +125 °C. Parameter Sym Min Typ Max Unit Output Voltages, VCC = 4.5 V: Low, IOL = 8.0 mA VOL — — 0.5 V High, IOH = −400 µA VOH 2.4 — — V Low, VCC = 5.5 V VIL1 — — 0.7 V High, VCC = 5.5 V VIH1 2.0 — — V Clamp, VCC = 4.5 V, II = –5.0 mA VIK — — –1.0 V VTH1 — 0.1 0.20 V Input Offset Voltage VOFF 0.02 0.05 V Input Offset Voltage BRS2B VOFF 0.1 0.15 V Off-state (high Z), VO = 0.4 V IOZL — — –20 µA Off-state (high Z), VO = 2.4 V IOZH — — 20 µA Short Circuit IOS3 –25 — –100 mA Low, VIN = 0.4 V IIL — — –400 µA High, VIN = 2.7 V IIH — — 20 µA Reverse, VIN = 5.5 V IIH — — 100 µA Low, VIN = –1.2 V IIL — — −1.0 mA High, VIN = 7.2 V IIH — — 1.0 mA RO — 110 — Ω R1 — 60 — Ω R2 — 90 — Ω Enable Input Voltages: Differential Input Voltages, VIH – VIL:2 −0.80 V < VIH < 7.2 V, −1.2 V < VIL < 6.8 V Output Currents, VCC = 5.5 V: Enable Currents, VCC = 5.5 V: Differential Input Currents, VCC = 5.5 V: Differential Input Impedance (BRR1A): Connected Between RI and RI Differential Input Impedance (BRT1A)4 1. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment. 2. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recommended that all unused positive inputs be tied to the positive power supply. No external series resistor is required.) 3. Test must be performed one lead at a time to prevent damage to the device. 4. See Figure 2. R1 R1 RI RI R2 12-2819.a(F) Figure 2. BRT1A Terminating Resistor Configuration Agere Systems Inc. 3 Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Timing Characteristics Table 4. Timing Characteristics (See Figure 4 and Figure 5.) For propagation delays (tPLH and tPHL) over the temperature range, see Figure 9 and Figure 10. Propagation delay test circuit connected to output is shown in Figure 6. TA = –40 °C to +125 °C, VCC = 5 V ± 0.5 V. Parameter Symbol EXTRINSIC PROPAGATION DELAY, tP (ns) Propagation Delay: Input to Output High tPLH Input to Output Low tPHL Disable Time, CL = 5 pF: High-to-high Impedance t PHZ Low-to-high Impedance tPLZ Pulse Width Distortion, ltpHL − tpLHI: Load Capacitance (CL) = 15 pF tskew1 L Load Capacitance (C ) = 150 pF tskew1 Output Waveform Skews: Part-to-Part Skew, TA = 75 °C ∆tskew1p-p Part-to-Part Skew, TA = –40 °C to +125 °C ∆tskew1p-p Same Part Skew ∆tskew Enable Time: High Impedance to High tPZH High Impedance to Low tPZL Rise Time (20%—80%) ttLH Fall Time (80%—20%) ttHL Min Typ Max Unit 1.5 1.5 2.5 2.5 4.0 4.0 ns ns — — 5 5 12 12 ns ns — — — — 0.7 4.0 ns ns — — — 0.8 — — 1.4 1.5 0.3 ns ns ns — — — — 8 8 — — 12 12 3.0 3.0 ns ns ns ns 7 6 5 4 tPLH (TYP) 3 2 tPHL (TYP) 1 0 0 25 50 75 100 125 150 175 200 LOAD CAPACITANCE, CL (pF) 12-3462(F) Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the delay due to the external capacitance and the intrinsic delay of the device. Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C 4 Agere Systems Inc. Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Timing Characteristics (continued) 3.7 V INPUT 3.2 V 2.7 V INPUT tPLH tPHL OUTPUT 80% VOH 80% 1.5 V 20% 20% ttHL VOL ttLH 12-2251.b(F) Figure 4. Receiver Propagation Delay Timing 3V E1* 1.5 V 0V 3V E2† 1.5 V 0V tPZH tPHZ tPLZ tPZL VOH OUTPUT VOL ∆V = 0.5 V ∆V = 0.5 V ∆V = 0.5 V ∆V = 0.5 V 12-253.b(F) * E2 = 1 while E1 changes state. † E1 = 0 while E2 changes state. Figure 5. Receiver Enable and Disable Timing Test Conditions Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits. 5V 2 kΩ TO OUTPUT OF DEVICE UNDER TEST CL 15 pF* 5 kΩ 12-2249(F) * Includes probe and jig capacitances. Note: All 458E, IN4148, or equivalent diodes. Figure 6. Receiver Propagation Delay Test Circuit Agere Systems Inc. 5 Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Temperature Characteristics 4.00 30 ICC MAX VCC = 5.5 28 ICC (mA) PROPAGATION DELAY (ns) 32 26 24 ICC TYP VCC = 5.0 22 20 18 –50 –25 0 25 50 75 100 125 3.50 MAX 3.00 TYP 2.50 MIN 2.00 1.50 1.00 –50 150 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) 12-3465(F) 12-3463.a(F) Figure 7. Typical and Maximum ICC vs. Temperature Figure 9. Propagation Delay for a High Output (tPLH) vs. Temperature at VCC = 5.0 V 3.8 4.00 3.6 PROPAGATION DELAY (ns) VOLTAGE (V) 3.2 IOH MIN 2.8 2.4 2.0 1.6 1.2 0.8 IOL MAX 0.4 0.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) MAX 3.50 3.00 TYP 2.50 MIN 2.00 1.50 1.00 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 12-3464.a(F) 12-3466(F) Figure 8. Minimum VOH and Maximum VOL vs. Temperature at VCC = 4.5 V Figure 10. Propagation Delay for a Low Output (tPHL) vs. Temperature at VCC = 5.0 V Handling Precautions CAUTION: This device is susceptible to damage as a result of ESD. Take proper precautions during both handling and testing. Follow guidelines such as JEDEC Publication No. 108-A (Dec. 1988). When handling and mounting line driver products, proper precautions should be taken to avoid exposure to ESD. The user should adhere to the following basic rules for ESD control: 1. Assume that all electronic components are sensitive to ESD damage. 2. Never touch a sensitive component unless properly grounded. 3. Never transport, store, or handle sensitive components except in a static-safe environment. 6 Agere Systems Inc. Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 The HBM ESD threshold voltage presented here was obtained by using the following circuit parameters: ESD Failure Models Agere employs two models for ESD events that can cause device damage or failure: 1. An HBM that is used by most of the industry for ESD-susceptibility testing and protection-design evaluation. ESD voltage thresholds are dependent on the critical parameters used to define the model. A standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. 2. A charged-device model (CDM), which many believe is the better simulator of electronics manufacturing exposure. Table 5. Typical ESD Thresholds for Data Transmission Receivers Device HBM Threshold BRF1A, BRR1A, BRT1A BRF2A, BRS2B CDM Threshold Differential Inputs Others >800 >2000 >1000 >2000 >2000 >2000 Table 6. ESD Damage Protection Table 5 and Table 6 illustrates the role these two models play in the overall prevention of ESD damage. HBM ESD testing is intended to simulate an ESD event from a charged person. The CDM ESD testing simulates charging and discharging events that occur in production equipment and processes, e.g., an integrated circuit sliding down a shipping tube. ESD Threat Controls Control Model Personnel Processes Wrist straps. ESD shoes. Antistatic flooring. Human body model (HBM). Static-dissipative materials. Air ionization. Charged-device model (CDM). Latch Up Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if powersupply current exceeds the specified maximum due to the application of a stress to the device under test. A device is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at that level after the stress is removed. Agere performs latch up testing per an internal test method that is consistent with JEDEC Standard No. 17 (previously JC-40.2) CMOS Latch Up Standardized Test Procedure. Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels: 1. dc current stressing of input and output pins. 2. Power supply slew rate. 3. Power supply overvoltage. Table 7. Latch Up Test Criteria and Test Results Data Transmission Receiver ICs dc Current Stress of I/O Pins Power Supply Slew Rate Power Supply Overvoltage Minimum Criteria ≥150 mA ≤1 µs ≥1.75 x Vmax Test Results ≥250 mA ≤100 ns ≥2.25 x Vmax Based on the results in Table 7, the data transmission receivers pass the Agere latch-up esting requirements and are considered not susceptible to latch up. Agere Systems Inc. 7 Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Power Dissipation System designers incorporating Agere data transmission drivers in their applications should be aware of package and thermal information associated with these components. Proper thermal management is essential to the longterm reliability of any plastic encapsulated integrated circuit. Thermal management is especially important for surface-mount devices, given the increasing circuit pack density and resulting higher thermal density. A key aspect of thermal management involves the junction temperature (silicon temperature) of the integrated circuit. Several factors contribute to the resulting junction temperature of an integrated circuit: ■ Ambient use temperature ■ Device power dissipation ■ Component placement on the board ■ Thermal properties of the board ■ Thermal impedance of the package Thermal impedance of the package is referred to as Data Sheet April 2001 The power dissipated in the output is a function of the: ■ Termination scheme on the outputs ■ Termination resistors ■ Duty cycle of the output Package thermal impedance depends on: ■ Airflow ■ Package type (e.g., DIP, SOIC, SOIC/NB) The junction temperature can be calculated using the previous equation, after power dissipation levels and package thermal impedances are known. Figure 11 illustrates the thermal impedance estimates for the various package types as a function of airflow. This figure shows that package thermal impedance is higher for the narrow-body SOIC package. Particular attention should, therefore, be paid to the thermal management issues when using this package type. In general, system designers should attempt to maintain junction temperature below 125 °C. The following factors should be used to determine if specific data transmission drivers in particular package types meet the system reliability objectives: Θja and is measured in °C rise in junction temperature ■ System ambient temperature per watt of power dissipation. Thermal impedance is also a function of airflow present in system application. ■ Power dissipation ■ Package type ■ Airflow The following equation can be used to estimate the junction temperature of any device: Tj = TA + PD Θja 140 where: TA is ambient temperature (°C). PD is power dissipation (W). Θja is package thermal impedance (junction to ambient—°C/W). The power dissipation estimate is derived from two factors: ■ Internal device power ■ Power associated with output terminations Multiplying ICC times VCC provides an estimate of internal power dissipation. 130 THERMAL RESISTANCE Θja (°C/W) Tj is device junction temperature (°C). 120 110 100 SOIC/NB 90 80 70 J-LEAD SOIC/GULL WING 60 50 40 DIP 0 200 400 600 800 1000 1200 AIRFLOW (ft./min.) 12-2753(F) Figure 11. Power Dissipation 8 Agere Systems Inc. Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Outline Diagrams 16-Pin DIP Dimensions are in millimeters. L N B 1 W PIN #1 IDENTIFIER ZONE H SEATING PLANE 0.38 MIN 2.54 TYP 0.58 MAX 5-4410(F) Package Description Number of Pins (N) Plastic Dual In-Line Package (PDIP3) 16 Package Dimensions Maximum Length (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 20.57 6.48 7.87 5.08 Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Systems sales representative. Agere Systems Inc. 9 Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Outline Diagrams (continued) 16-Pin SOIC (SONB/SOG) Dimensions are in millimeters. L N B 1 PIN #1 IDENTIFIER ZONE W H SEATING PLANE 0.10 0.51 MAX 1.27 TYP 0.61 0.28 MAX 5-4414(F) Package Description Number of Pins (N) Small-Outline, Narrow Body (SONB) Small-Outline, Gull-Wing (SOG) Package Dimensions Maximum Length (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 16 10.11 4.01 6.17 1.73 16 10.49 7.62 10.64 2.67 Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Systems sales representative. 10 Agere Systems Inc. Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Outline Diagrams (continued) 16-Pin SOIC (SOJ) Dimensions are in millimeters. L N B 1 PIN #1 IDENTIFIER ZONE W H SEATING PLANE 0.10 1.27 TYP 0.51 MAX 0.79 MAX 5-4413(F) Package Description Number of Pins (N) Small-Outline, J-Lead (SOJ) 16 Package Dimensions Maximum Length (L) Maximum Width Without Leads (B) Maximum Width Including Leads (W) Maximum Height Above Board (H) 10.41 7.62 8.81 3.18 Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Systems sales representative. Agere Systems Inc. 11 Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A Data Sheet April 2001 Ordering Information Part Number BRF1A16E BRF1A16E-TR BRF1A16G BRF1A16G-TR BRF1A16NB BRF1A16NB-TR BRF1A16P BRF2A16E BRF2A16E-TR BRF2A16G BRF2A16G-TR BRF2A16NB BRF2A16NB-TR BRF2A16P BRR1A16E BRR1A16E-TR BRR1A16G BRR1A16G-TR BRR1A16NB BRR1A16NB-TR BRR1A16P BRS2B16E BRS2B16E-TR BRS2B16G BRS2B16G-TR BRS2B16P BRS2B16NB BRS2B16NB-TR BRT1A16E BRT1A16E-TR BRT1A16G BRT1A16G-TR BRT1A16NB BRT1A16NB-TR BRT1A16P Package Type Comcode Former Pkg. Type Former Part Number 16-pin, Plastic SOJ Tape & Reel SOJ 16-pin, Plastic SOIC Tape & Reel SOIC 16-pin, Plastic SOIC/NB Tape & Reel SOIC/NB 16-pin, Plastic DIP 16-pin, Plastic SOJ Tape & Reel SOJ 16-pin, Plastic SOIC Tape & Reel SOIC 16-pin, Plastic SOIC/NB Tape & Reel SOIC/NB 16-pin, Plastic DIP 16-pin, Plastic SOJ Tape & Reel SOJ 16-pin, Plastic SOIC Tape & Reel SOIC 16-pin, Plastic SOIC/NB Tape & Reel SOIC/NB 16-pin, Plastic DIP 16-pin, Plastic SOJ Tape & Reel SOJ 16-pin, Plastic SOIC Tape & Reel SOIC 16-pin, Plastic DIP 16-pin, Plastic SOIC/NB Tape & Reel SOIC/NB 16-pin, Plastic SOJ Tape & Reel SOJ 16-pin, Plastic SOIC Tape & Reel SOIC 16-pin, Plastic SOIC/NB Tape & Reel SOIC/NB 16-pin, Plastic DIP 107949927 107949935 107950297 107950305 107949968 107949976 107949984 107949992 107950008 107950016 107950024 107950032 107950040 107950057 107950065 107950073 107950081 107950099 107950107 107950115 107950123 108888470 108888488 108699133 108699125 108888447 108888454 108888462 107950131 107950149 107950156 107950164 107950313 107950321 107950339 1041 1041 1141 1141 1241 1241 41 1041 1041 1141 1141 1241 1241 41 1041 1041 1141 1141 1241 1241 41 1041 1041 1141 1141 41 1241 1241 1041 1041 1141 1141 1241 1241 41 LF, MF, LS LF, MF, LS LF, MF, LS LF, MF, LS LF, MF, LS LF, MF, LS LF, MF, LS LF2, MF2 LF2, MF2 LF2, MF2 LF2, MF2 LF2, MF2 LF2, MF2 LF2, MF2 LR, MR LR, MR LR, MR LR, MR LR, MR LR, MR LR, MR MF, MF2, LS MF, MF2, LS MF, MF2, LS MF, MF2, LS MF, MF2, LS MF, MF2, LS MF, MF2, LS LT, MT LT, MT LT, MT LT, MT LT, MT LT, MT LT, MT For additional information, contact your Agere Systems Account Manager or the following: http://www.agere.com INTERNET: [email protected] E-MAIL: N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC Tel. (86) 21 50471212, FAX (86) 21 50472266 JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A. April 2001 DS01-069ANET-1 (Replaces DS01-069ANET)