AGERE BTF1A

Data Sheet
March 2001
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Features
■
Electrostatic discharge (ESD) performance better
than the 41 Series
Driver Features
■
Lower power requirement than the 41 Series
■
Produces a logic zero in third state
■
400 mV difference voltage in third state
■
Two line drivers per package
■
Logic to convert TTL input logic levels to differential, pseudo-emmiter coupled logic (ECL) output
logic levels
■
No line loading when VCC = 0 V
■
High output driver for 50 Ω loads
■
200 mA short-circuit current (typical)
■
2.0 ns maximum propagation delay
■
<0.2 ns output skew (typical)
Receiver Features
■
Two line receivers per package
■
High input impedance ≅ 8 kΩ
■
Logic that converts differential input logic levels to
TTL output logic levels
■
4.0 ns maximum propagation delay
■
<0.20 V input sensitivity (typical)
■
−1.2 V to +7.2 V common-mode range
Common Device Features
■
■
Common enable for each driver/receiver pair
Operating temperature range: –40 °C to +125 °C
(wider than the 41 Series)
■
Single 5.0 V ± 5% supply
■
400 Mbits/s maximum data rate
■
Meets enhanced small device interface (ESDI)
standards
Description
The BTF1A device is a dual differential transceiver
circuit that transmits and receives digital data over
balanced transmission lines and is compatible with
Lucent Technologies Microelectronics Group differential drivers and receivers. It is designed to provide
a strong logic zero when in the third state. The minimum difference voltage in the third state is 400 mV. It
is designed specifically for bus applications where a
well-defined logic state is needed when the bus is
idle. The driver puts out a logic zero when in the third
state mode, which is easily overriden by an active
buffer on the bus. When all the buffers on the bus are
inactive (third state), the signal on the bus is a zero
indicating that the bus is idle.
The dual drivers translate input TTL logic levels to differential pseudo-ECL output levels. The dual receiver
converts differential input logic levels to TTL output
levels. Each driver/receiver pair has its own common
enable control allowing serial data and a control clock
to be transmitted and received on a single integrated
circuit. The BTF1A transceiver requires the customer
to supply termination resistors on the circuit board.
The powerdown loading characteristics of the
receiver input circuit are approximately 8 kΩ relative
to the power supplies; hence, it will not load the
transmission line when the circuit is powered down.
For those circuits with termination resistors, the line
will remain impedance matched when the circuit is
powered down. The driver does not load the line
when it is powered down.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Pin Information
RO1
16 RI1
1
R1
DI1
2
VCC
3
15 RI1
14 DO1
D1
ED
4
ER
5
13 DO1
12 DO2
D2
GND
6
DI2
7
11 DO2
10 RI2
R2
RO2
8
9
RI2
BTF1A
12-2747.a(F)
Figure 1. Differential Transceiver Logic Diagram
Table 1. Enable Truth Table
ED
ER
D1
D2
R1
R2
0
1
0
1
0
0
1
1
Active
Disabled
Active
Disabled
Active
Disabled
Active
Disabled
Active
Active
Disabled
Disabled
Active
Active
Disabled
Disabled
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Power Supply Voltage
Ambient Operating Temperature
Storage Temperature
2
Symbol
Min
Max
Unit
VCC
TA
Tstg
—
−40
−55
6.5
125
150
V
°C
°C
Agere Systems Inc.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Electrical Characteristics
For variations in electrical characteristics over the temperature range, see Figure 10 through Figure 12.
Table 3. Power Supply Current Characteristics
TA = −40 °C to +125 °C, VCC = 5 V ± 0.25 V.
Parameter
Power Supply Current (VCC = 5.5 V)
All Outputs Disabled
All Outputs Enabled
Symbol
Min
Typ
Max
Unit
ICC
ICC
—
—
40
20
65
35
mA
mA
Third State
The BTF1A driver produces pseudo-ECL levels, and has a third-state mode, which is different than a conventional
TTL device. When a driver is placed in the third state, the base of the output transistors are pulled low, bringing the
outputs below the active-low level. The BTF1A is unique because it provides a logic zero at its output when in the
third state. If all the buffers on the bus are in the third state, the BTF1A is designed to deliver a logic zero to the bus
to act as an indicator that the bus is idle. The guaranteed zero level, Vdo – Vdo, is 0.4 V.
Agere Systems Inc.
3
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Electrical Characteristics (continued)
Table 4. Driver Voltage and Current Characteristics
For variations in output voltage over the temperature range, see Figure 10 and Figure 11. TA = −40 °C to +125 °C.
Parameter
Output Voltages:
Low1
High1:
Differential Voltage (VOH – VOL)
Output Voltage Third State:
Difference Voltage Vdo - Vdo
Third State, IOH = –1.0 mA, VCC = 4.75 V
Output Voltages (TA = 0 °C to 85 °C):
Low1
High1:
Differential Voltage (VOH – VOL)
Input Voltages:
Low, VCC = 5.25 V:
Data Input
Enable Input
High, VCC = 4.75 V
Clamp, VCC = 4.75 V, II = –5.0 mA
Short-circuit Output Current, VCC = 5.25 V
Input Currents, VCC = 5.25 V:
Low, VI = 0.4 V
High, VI = 2.7 V
Reverse, VI = 5.25 V
Symbol
Min
Typ
Max
Unit
VOL
VOH
VDIFF
VOH – 1.4
VCC − 1.8
0.65
VOH − 1.1
VCC − 1
1.1
VOH − 0.65
VCC − 0.8
1.4
V
V
V
VDIFZ
VOZ
0.4
—
0.6
—
—
VOL − 0.2
V
V
VOL
VOH
VDIFF
VOH – 1.4
VCC − 1.5
0.8
VOH − 1.1
VCC − 1
1.1
VOH − 0.8
VCC − 0.8
1.4
V
V
V
VIL2
VIL3
VIL3
VIH2
VIK
IOS
—
—
—
2.0
—
–100
—
—
—
—
—
—
0.8
0.8
0.7
—
−1.0
—
V
V
V
V
V
mA
IIL
IIH
IIH
—
—
—
—
—
—
−400
20
100
µA
µA
µA
1. Values are with terminations as per Figure 7.
2. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.
3. Test must be performed one lead at a time to prevent damage to the device.
4
Agere Systems Inc.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Electrical Characteristics (continued)
Table 5. Receiver Voltage and Current Characteristics
For variation in minimum VOH and maximum VOL over the temperature range, see Figure 10. TA = –40 °C to +125 °C.
Parameter
Output Voltages VCC = 4.75 V:
Low, IOL = 8.0 mA1
High, IOH = −400 µA
Enable Input Voltages:
Low, VCC = 5.25 V
High, VCC = 4.75 V
Clamp, VCC = 4.75 V, II = –5.0 mA
Minimum Differential Input Voltages, VIH – VIL:2
−0.80 V < VIH < 7.2 V, −1.2 V < VIL < 6.8 V
Input Offset Voltage
Output Currents, VCC = 5.25 V:
Off-state (high Z), VO = 0.4 V
Off-state (high Z), VO = 2.4 V
Short Circuit
Enable Input Currents, VCC = 5.25 V:
Low, VIN = 0.4 V
High, VIN = 2.7 V
Reverse, VIN = 5.5 V
Differential Input Currents:
Low, VIN = –1.2 V
High, VIN = 7.2 V
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
2.4
—
—
0.5
—
V
V
VIL1
VIH1
VIK
—
2.0
—
—
—
—
0.7
—
−1.0
V
V
V
VTH1
VOFF
—

0.1
0.03
0.20
0.05
V
V
IOZL
IOZH
IOS3
—
—
–25
—
—
—
–20
20
–100
µA
µA
mA
IIL
IIH
IIH
—
—
—
—
—
—
–400
20
100
µA
µA
µA
IIL
IIH
—
—
—
—
−1.0
1.0
mA
mA
1. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.
2. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recommended that all unused positive inputs
be tied to the positive power supply. No external series resistor is required.)
3. Test must be performed one lead at a time to prevent damage to the device.
Agere Systems Inc.
5
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Timing Characteristics
Table 6. Driver Timing Characteristics (See Figure 3 and Figure 4.)
For tP1 and tP2 propagation delays over the temperature range, see Figure 13. Propagation delay test circuit connected to output is shown in Figure 7. TA = −40 °C to +125 °C, VCC = 5 V ± 0.25 V.
Parameter
Propagation Delay:
Input High to Output 1
Input Low to Output1
Capacitive Delay
Disable Time (either E1 or E2):
High-to-High Impedance
Low-to-High Impedance
Enable Time (either E1 or E2):
High Impedance to High
High Impedance to Low
Output Skew:
|tP1 – tP2|
|tPHH – tPHL|, |tPLH – tPLL|
Difference Between Drivers
Rise Time (20%—80%)
Fall Time (80%—20%)
Symbol
Min
Typ
Max
Unit
tP12
tP22
∆tp
0.8
0.8
—
1.2
1.2
0.02
2.0
2.0
0.03
ns
ns
ns/pF
tPHZ
tPLZ
4
4
8
8
12
12
ns
ns
tPZH
tPZL
4
4
8
8
12
12
ns
ns
tskew1
tskew2
∆tskew
ttLH
ttHL
—
—
—
—
—
0.1
0.2
—
0.7
0.7
0.3
0.5
0.3
2
2
ns
ns
ns
ns
ns
1. CL = 5 pF. Capacitor is connected from each output to ground.
2. tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 3).
Table 7. Receiver Timing Characteristics (See Figure 5 and Figure 6.)
For propagation delays (tPLH and tPHL) over the temperature range, see Figure 14 and Figure 15. Propagation delay
test circuit connected to output is shown in Figure 8. TA = −40 °C to +125 °C, VCC = 5 V ± 0.25 V.
Parameter
Propagation Delay:
Input to Output High
Input to Output Low
Pulse Width Distortion, ltpHL-tpLHI:
Load Capacitance (CL) = 15 pF
Load Capacitance (CL) = 150 pF
Output Waveform Skews:
Part-to-Part Skew, TA = 75 °C
Part-to-Part Skew, TA = –40 °C to +125 °C
Same Part Skew
Disable Time, CL = 5 pF:
High-to-high Impedance
Low-to-high Impedance
Enable Time:
High Impedance to High
High Impedance to Low
Rise Time (20%—80%)
Fall Time (80%—20%)
6
Symbol
Min
Typ
Max
Unit
tPLH
tPHL
1.5
1.5
2.5
2.5
4.0
4.0
ns
ns
tskew1
tskew1
—
—
—
—
0.7
4.0
ns
ns
∆tskew1p-p
∆tskew1p-p
∆tskew
—
—
—
0.8
—
—
1.4
1.5
0.3
ns
ns
ns
tPHZ
tPLZ
—
—
5
5
12
12
ns
ns
tPZH
tPZL
ttLH
ttHL
—
—
—
—
8
8
—
—
12
ns
12
ns
3.0
ns
3.0
ns
Agere Systems Inc.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
EXTRINSIC PROPAGATION DELAY, tP (ns)
Timing Characteristics (continued)
7
6
5
4
tPLH (TYP)
3
2
tPHL (TYP)
1
0
0
25
50
75
100
125
150
175 200
LOAD CAPACITANCE, CL (pF)
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 2. Typical Extrinsic Propagation Delay Versus Load Capacitance at 25 °C
2.4 V
1.5 V
0.4 V
INPUT
TRANSITION
tP1
tP2
VOH
OUTPUTS
VOL
tPHH
tPLL
OUTPUT
VOH
(VOH + VOL)/2
VOL
OUTPUT
VOH
(VOH + VOL)/2
VOL
tPHL
OUTPUT
tPLH
80%
20%
VOH
80%
20%
ttLH
VOL
ttHL
12-2677(F)
Figure 3. Driver Propagation Delay Timing
Agere Systems Inc.
7
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Timing Characteristics (continued)
3.0 V
1.5 V
0.0 V
ED
OUTPUT
tPHZ
tPZH
VOH
VOL + 0.2 V
VOL
VOL – 0.1 V
OUTPUT – 0.4 V
VOL
VOL – 0.1 V
OUTPUT
tPLZ
tPZL
12-2268.d(F)
Note: In the third state, OUTPUT is 0.4 V more negative than OUTPUT.
Figure 4. Driver Enable and Disable Timing
INPUT
3.7 V
3.2 V
INPUT
2.7 V
tPLH
tPHL
OUTPUT
80%
80%
VOH
1.5 V
20%
20%
ttHL
VOL
ttLH
12-2251.b(F)
Figure 5. Receiver Propagation Delay Timing
8
Agere Systems Inc.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Timing Characteristics (continued)
3V
E1*
1.5 V
0V
3V
E2†
1.5 V
0V
tPZH
tPHZ
tPLZ
tPZL
VOH
OUTPUT
∆V = 0.5 V
VOL
∆V = 0.5 V
∆V = 0.5 V
∆V = 0.5 V
12-2538.b(F)
* E2 = 1 while E1 changes state.
† E1 = 0 while E2 changes state.
Figure 6. Receiver Enable and Disable Timing
Test Conditions
+5 V
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the
data transmission driver devices are measured with the
following output load circuits.
2 kΩ
TO OUTPUT OF
DEVICE UNDER
TEST
CL
15 pF*
5 kΩ
100 Ω
DO
200 Ω
DO
12-2249(F)
200 Ω
* Includes probe and jig capacitances.
Note: All 458E, IN4148, or equivalent diodes.
12-2271.a(F)
Figure 8. Receiver Propagation Delay Test Circuit
Figure 7. Driver Propagation Delay Test Circuit
Agere Systems Inc.
9
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Temperature Characteristics
Figure 9 illustrates typical driver output characteristics.
Included are load lines for two typical termination configurations.
OUTPUT VOLTAGE (V)
VCC – 2 V
VCC – 1 V
VCC
10
Y LOAD
20
VOL
30
π LOAD
OUTPUT CURRENT (mA)
VOH
40
12-2269(F)
OUTPUT VOLTAGE RELATIVE TO VCC
Output Characteristics
0
–0.5
VOH MAX
–1.0
–1.5
VOH MIN
VOL MAX
–2.0
–2.5
–50
VOL MIN
–25
0
25
50
75
100
125 150
TEMPERATURE (°C)
2-3467(F)
Figure 10. VOL and VOH Extremes for Drivers vs.
Temperature for 100 Ω Load
A. Output Current vs. Output Voltage for Loads
Shown in B and C
60 Ω
60 Ω
DO
DO
90 Ω
12-2270(F)
B. Y Load
100 Ω
DO
DIFFERENTIAL VOLTAGE (V)
1.2
VOH – VOL TYP
1.0
0.8
VOH – VOL MIN
0.6
0.4
DO
200 Ω
0
–50
200 Ω
–25
0
25
50
75
100
125 150
TEMPERATURE (°C)
12-3468(F)
12-2271.a(F)
C. π Load
Figure 11. Differential Voltage (VOH – VOL) for
Drivers vs. Temperature
Figure 9. Driver Output Current vs. Voltage
Characteristics
10
Agere Systems Inc.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Temperature Characteristics (continued)
3.8
4.00
PROPAGATION DELAY (ns)
3.6
VOLTAGE (V)
3.2
IOH MIN
2.8
2.4
2.0
1.6
1.2
0.8
IOL MAX
0.4
0.0
–50
–25
0
25
50
75
100
125
3.50
MAX
3.00
TYP
2.50
MIN
2.00
1.50
1.00
–50
150
–25
0
TEMPERATURE (°C)
25
50
75
100
Figure 12. Minimum VOH and Maximum VOL vs.
Temperature at VCC = 4.5 V for the
Receiver
12-3465(F)
Figure 14. Propagation Delay for a High Output
(tPLH) vs. Temperature at VCC = 5.0 V for
the Receivers
4.00
2.1
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
2.3
1.9
1.5
1.3
150
TEMPERATURE (°C)
12-3464.a(F)
1.7
125
RANGE FOR tP1 AND tP2
MAX
MIN
1.1
0.9
0.7
MAX
3.50
3.00
TYP
2.50
MIN
2.00
1.50
0.5
0.3
–50
–25
0
25
50
75
100
125 150
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
12-3469.a(F)
Figure 13. Min and Max for tP1 and tP2 Propagation
Delays vs. Temperature for the Driver
Agere Systems Inc.
1.00
–50
12-3466(F)
Figure 15. Propagation Delay for a Low Output
(tPHL) vs. Temperature at VCC = 5.0 V for
the Receivers
11
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Handling Precautions
CAUTION: This device is susceptible to damage as a result of ESD. Take proper precautions during both
handling and testing. Follow guidelines such as JEDEC Publication No. 108-A (Dec. 1988).
When handling and mounting line driver products, proper precautions should be taken to avoid exposure to ESD.
The user should adhere to the following basic rules for ESD control:
1. Assume that all electronic components are sensitive to ESD damage.
2. Never touch a sensitive component unless properly grounded.
3. Never transport, store, or handle sensitive components except in a static-safe environment.
ESD Failure Models
Lucent employs two models for ESD events that can cause device damage or failure:
1. A human body model (HBM) that is used by most of the industry for ESD-susceptibility testing and protectiondesign evaluation. ESD voltage thresholds are dependent on the critical parameters used to define the model.
A standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and, therefore, can be used for
comparison purposes.
2. A charged-device model (CDM), which many believe is the better simulator of electronics manufacturing exposure.
Table 8 and Table 9 illustrate the role these two models play in the overall prevention of ESD damage. HBM ESD
testing is intended to simulate an ESD event from a charged person. The CDM ESD testing simulates charging and
discharging events that occur in production equipment and processes, e.g., an integrated circuit sliding down a
shipping tube.
The HBM ESD threshold voltage presented here was obtained by using these circuit parameters.
Table 8. Typical ESD Thresholds for Data Transmission Transceivers
Device
HBM Threshold
CDM Threshold
Differential Inputs
All Other Pins
>800
>2000
>1000
>1000
Table 9. ESD Damage Protection
ESD Threat Controls
Control
Model
12
Personnel
Processes
Wrist straps
ESD shoes
Antistatic flooring
Human body model (HBM)
Static-dissipative materials
Air ionization
Charged-device model (CDM)
Agere Systems Inc.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Latch Up
Latch up evaluation has been performed on the data transmission receivers. Latch up testing determines if the
power-supply current exceeds the specified maximum due to the application of a stress to the device under test. A
device is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at
that level after the stress is removed.
Lucent performs latch up testing per an internal test method which is consistent with JEDEC Standard No. 17 (previously JC-40.2) CMOS Latch Up Standardized Test Procedure.
Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 10. Latch Up Test Criteria and Test Results
Data Transmission
Receiver ICs
Agere Systems Inc.
dc Current Stress
of I/O Pins
Power Supply
Slew Rate
Power Supply
Overvoltage
Minimum Criteria
≥150 mA
≤1 µs
≥1.75 x Vmax
Test Results
≥250 mA
≤100 ns
≥2.25 x Vmax
13
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Outline Diagrams
16-Pin SOIC (SONB/SOG)
Dimensions are in millimeters.
L
N
B
1
PIN #1 IDENTIFIER ZONE
W
H
SEATING PLANE
0.10
0.51 MAX
1.27 TYP
0.61
0.28 MAX
5-4414(F)
Package
Description
Number of
Pins
(N)
Small-Outline,
Gull-Wing
(SOG)
16
Package Dimensions
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
10.49
7.62
10.64
2.67
Note: The dimensions in this oultine diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Lucent Technologies sales representative.
14
Agere Systems Inc.
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Power Dissipation
System designers incorporating Lucent data transmission drivers in their applications should be aware of
package and thermal information associated with these
components.
Proper thermal management is essential to the longterm reliability of any plastic encapsulated integrated
circuit. Thermal management is especially important
for surface-mount devices, given the increasing circuit
pack density and resulting higher thermal density. A
key aspect of thermal management involves the junction temperature (silicon temperature) of the integrated
circuit.
Several factors contribute to the resulting junction temperature of an integrated circuit:
■
Ambient use temperature
■
Device power dissipation
■
Component placement on the board
■
Thermal properties of the board
■
Thermal impedance of the package
Thermal impedance of the package is referred to as
The power dissipated in the output is a function of the:
■
Termination scheme on the outputs
■
Termination resistors
■
Duty cycle of the output
Package thermal impedance depends on:
■
Airflow
■
Package type (e.g., DIP, SOIC, SOIC/NB)
The junction temperature can be calculated using the
previous equation, after power dissipation levels and
package thermal impedances are known.
Figure 16 illustrates the thermal impedance estimates
for the various package types as a function of airflow.
This figure shows that package thermal impedance is
higher for the narrow-body SOIC package. Particular
attention should, therefore, be paid to the thermal management issues when using this package type.
In general, system designers should attempt to maintain junction temperature below 125 °C. The following
factors should be used to determine if specific data
transmission drivers in particular package types meet
the system reliability objectives:
Θja and is measured in °C rise in junction temperature
■
System ambient temperature
per watt of power dissipation. Thermal impedance is
also a function of airflow present in system application.
■
Power dissipation
■
Package type
■
Airflow
The following equation can be used to estimate the
junction temperature of any device:
Tj = TA + PD Θja
140
where:
TA is ambient temperature (°C).
PD is power dissipation (W).
Θja is package thermal impedance (junction to
ambient—°C/W).
The power dissipation estimate is derived from two factors:
■
Internal device power
■
Power associated with output terminations
130
THERMAL RESISTANCE
Θja (°C/W)
Tj is device junction temperature (°C).
120
110
100
SOIC/NB
90
80
70
J-LEAD SOIC/GULL WING
60
50
40
DIP
0
200
400
600
800
1000
1200
AIRFLOW (ft/min)
Multiplying ICC times VCC provides an estimate of
internal power dissipation.
Agere Systems Inc.
12-2753(F)
Figure 16. Power Dissipation
15
Dual Differential Transceiver BTF1A
With Idle Bus Indicator
Data Sheet
March 2001
Ordering Information
Part Number
BTF1A16G
BTF1A16G-TR
Driver
Terminating1
None
None
Receiver
Terminating2
None
None
Package Type
Comcode
16-pin, Plastic SOIC
Tape and Reel SOIC
108648861
108698887
1. Indicates on-chip output terminating resistors from each driver output to ground.
2. Indicates on-chip input terminations across receiver inputs.
For additional information, contact your Agere Systems Account Manager or the following:
http://www.agere.com
INTERNET:
[email protected]
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Tel. (65) 778 8833, FAX (65) 777 7495
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Tel. (86) 21 50471212, FAX (86) 21 50472266
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Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
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Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
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Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
March 2001
DS01-068ANET-1 (Replaces DS01-068ANET)