TI TB5R3D

TB5R3
www.ti.com
SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007
QUAD DIFFERENTIAL PECL RECEIVERS
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Functional Replacement for the Agere BRF1A
Pin Equivalent to General Trade 26LS32
High Input Impedance Approximately 8 kΩ
<2.6-ns Maximum Propagation Delay
TB5R3 Provides 50-mV Hysteresis (Typical)
-1.1-V to 7.1-V Common-Mode Input Voltage
Range
Single 5-V ±10% Supply
ESD Protection HBM > 3 kV and CDM > 2 kV
Operating Temperature Range: -40°C to 85°C
Available in Gull-Wing SOIC (JEDEC MS-013,
DW) and SOIC (D) Package
APPLICATIONS
•
Digital Data or Clock Transmission Over
Balanced Lines
DESCRIPTION
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels.
The TB5R3 is a pin- and function-compatible
replacement for the Agere systems BRF1A; it
includes 3-kV HBM and 2-kV CDM ESD protection.
The power-down loading characteristics of the
receiver input circuit are approximately 8 kΩ relative
to the power supplies; hence they do not load the
transmission line when the circuit is powered down.
The packaging for this differential line receiver is a
16-pin gull wing SOIC (DW) or a 16 pin SOIC (D).
The enable inputs of this device include internal
pull-up resistors of approximately 40 kΩ that are
connected to VCC to ensure a logical high level input
if the inputs are open circuited.
FUNCTIONAL BLOCK DIAGRAM
PIN ASSIGNMENTS
AI
SOIC PACKAGE
(TOP VIEW)
AO
AI
BI
AI
AI
AO
E1
BO
BI
BI
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
DI
DI
DO
E2
CO
CI
CI
BO
BI
C1
CO
C1
D1
DO
D1
E1
E2
Enable Truth Table
E1
E2
OUTPUT
CONDITION
0
0
Active
1
0
Active
0
1
Disabled
1
1
Active
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
TB5R3
www.ti.com
SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART MARKING
PACKAGE (2)
LEAD FINISH
STATUS
TB5R3DW
TB5R3
Gull-Wing SOIC
NiPdAu
Production
TB5R3D
TB5R3
SOIC
NiPdAu
Production
PART NUMBER
(1)
(2)
(1)
Add the R suffix for tape and reel carrier (i.e., TB5R3DR)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
POWER DISSIPATION RATINGS
PACKAGE
DW
D
(1)
(2)
(3)
POWER RATING
TA ≤ 25°C
THERMAL RESISTANCE,
JUNCTION-TO-AMBIENT
WITH NO AIR FLOW
Low-K (2)
831 mW
High-K (3)
1240 mW
Low-K (2)
CIRCUIT BOARD
MODEL
High-K
(3)
DERATING
FACTOR (1)
TA ≥ 25°C
POWER RATING
TA = 85°C
120.3°C/W
8.3 mW/°C
332 mW
80.8°C/W
12.4 mW/°C
494 mW
763 mW
131.1°C/W
7.6 mW/°C
305 mW
1190 mW
84.1°C/W
11.9 mW/°C
475 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.
In accordance with the low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
θJB
Junction-to-Board Thermal Resistance
θJC
Junction-to-Case Thermal Resistance
PACKAGE
VALUE
DW
53.7
D
47.5
DW
47.1
D
44.2
UNIT
°C/W
°C/W
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Supply voltage, VCC
0 V to 6 V
Magnitude of differential bus (input) voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI|
ESD
Human Body Model
(2)
Charged-Device Model (3)
All pins
±3.5 kV
All pins
±2 kV
Continuous power dissipation
See Dissipation Rating Table
Storage temperature, Tstg
(1)
(2)
(3)
2
8.4 V
-65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
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SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC
Bus pin input voltage, VAI, VAI, VBIVBI, VCI , or VCI, VDI, VDI
Magnitude of differential input voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI|
Low-level enable input voltage
MIN
NOM
4.5
5
5.5
V
-1.2 (1)
7.2
V
0.1
6
V
0.8
V
85
°C
(2)
, VIL (VCC = 5.5 V)
High-level enable input voltage (2), VIH (VCC = 5.5 V)
2
Operating free-air temperature, TA
(1)
(2)
MAX UNIT
V
-40
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless
otherwise noted.
The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
DEVICE ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
Supply current (1)
ICC
(1)
TEST CONDITIONS
MIN
TYP MAX
UNIT
Outputs disabled
50
mA
Outputs enabled
48
mA
Current is dc power draw as measured through GND pin and does not include power delivered to load.
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
VOL
Output low voltage
VCC = 4.5 V,
IOL = 8 mA
VOH
Output high voltage
VCC = 4.5 V,
IOH = -400 µA
MIN
TYP
MAX
0.4
2.4
UNIT
V
V
VIK
Enable input clamp voltage
VCC = 4.5 V,
VTH+
Positive-going differential input threshold voltage (2), (Vxl - VxI)
x = A, B, C, or D
100
mV
VTH-
Negative-going differential input threshold voltage (2), (Vxl - VxI)
x = A, B, C, or D
100 (1)
mV
VHYST
Differential input threshold voltage hysteresis, (VTH+ - VTH–)
IOZL
VCC = 5.5 V
IOS
Output short circuit current
VCC = 5.5 V
IIL
Enable input low current
VCC = 5.5 V,
IIH
Enable input high current
Enable input reverse current
VCC = 5.5 V
µA
VO = 2.4 V
20
µA
400 (1)
mA
400 (1)
µA
VIN = 2.7 V
20
µA
VIN = 5.5 V
100
µA
-2 (1)
mA
1
mA
VIN = 0.4 V
VCC = 5.5V,
VIN = -1.2 V
IIH
Differential input high current
VCC= 5.5V,
VIN = 7.2 V
(1)
(2)
mV
-20 (1)
Differential input low current
Small-signal output resistance
V
VO = 0.4 V
IIL
RO
-1
50
Output off-state current, (High-Z)
IOZH
II = -5 mA
(1)
Output High
50
Output Low
25
Ω
This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
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SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007
SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tPHZ
Output disable time, high-level-to-high-impedance
output (3)
tskew1
Pulse-width distortion, |tPHL - tPLH|
1.57
<2.6
2.2
3.5
2.1
3.5
7.7
12
ns
5.2
12
ns
0.7
ns
4
ns
1.4
ns
CL = 10 pF, See Figure 2 and Figure 4
1.5
ns
CL = 10 pF, See Figure 2 and Figure 4
0.3
ns
6.9
12
ns
6.3
12
ns
1
ns
1
ns
CL = 10 pF, See Figure 2 and Figure 4
CL = 150 pF, See Figure 2 and Figure 4
CL = 10 pF, TA = 75°C, See Figure 2 and
Figure 4
Part-to-part output waveform skew
Δtskew
Same part output waveform skew
tPZH
Output enable time, high-impedance-to-high-level
output (3)
tPZL
Output enable time, high-impedance-to-low-level
output (3)
tTLH
Rise time (20%-80%)
tTHL
Fall time (80%-20%)
UNIT
ns
ns
CL = 5 pF, See Figure 3 and Figure 5
-p
(1)
(2)
(3)
MAX
<2.6
CL = 50 pF, See Figure 2 and Figure 4 (2)
Output disable time, low-level-to-high-impedance
output (3)
TYP
1.64
CL = 0 pF ,
See Figure 2 and Figure 4
tPLZ
Δtskew1p
MIN
(1)
0.8
CL = 10 pF, See Figure 3 and Figure 4
CL = 10 pF, See Figure 2 and Figure 4
The propagation delay values with a 0 pF load are based on design and simulation.
tr/tf: 3 ns (20% - 80%)
See Table 1.
See Note A
See Note A
tf
tr
INPUT
3.7 V
80%
80%
20%
20%
3.2 V
2.7 V
INPUT
t PHL
OUTPUT
t PLH
80%
80%
V OH
1.5 V
20%
20%
t THL
A.
V OL
t TLH
tr/tf: 3 ns (20% - 80%)
Figure 1. Receiver Propagation Delay Times
4
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E2
See
Note A
2.4 V
1.5 V
0.4 V
2.4 V
E1
See
Note B
1.5 V
0.4 V
t PHZ
t PZH
t PLZ
t PZL
VOH
OUTPUT
0.2 V
VOL
0.2 V
0.2 V
0.2 V
A.
E2 = 1 while E1 changes states.
B.
E1 = 0 while E2 changes states.
Figure 2. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
5V
TO OUTPUT
OF DEVICE
UNDER TEST
2k
CL
5k
DIODES TYPE
458E, 1N4148,
OR EQUIVALENT
CL includes test-fixture and probe capacitance.
Figure 3. Receiver Propagation Delay Time and Enable Time (tPZH, tPZL) Test Circuit
TO OUTPUT
OF DEVICE
UNDER TEST
500 W
1.5 V
CL
CL includes test-fixture and probe capacitance.
Figure 4. Receiver Disable Time (tPHZ, tPLZ) Test Circuit
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SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY
vs
LOAD CAPACITANCE
4
t pd − Propagation Delay Time − ns
3.5
tPLH
3
tPHL
2.5
2
1.5
1
0.5
0
0
25
50
75 100 125 150 175 200 225
CL − Load Capacitance − pF
NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the
sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the 0
pF load condition. The incremental increase in delay between the 0 pF load condition and the actual total load capacitance
represents the extrinsic, or external delay contributed by the load.
Figure 5.
6
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TYPICAL CHARACTERISTICS (continued)
LOW-TO-HIGH PROPAGATION DELAY
vs
JUNCTION TEMPERATURE
HIGH-TO-LOW PROPAGATION DELAY
vs
JUNCTION TEMPERATURE
2.5
VCC = 5 V
Loaded per Figure 3
t PHL− High-to-Low Propagation Delay − ns
tPLH − Low-to-High Propagation Delay − ns
2.5
Max
2
Typ
1.5
Min
1
0.5
0
−50 −25
0
50 75 100 125
25
TJ − Junction Temperature − 5C
VCC = 5 V,
Loaded per Figure 3
Typ
1.5
Min
1
0.5
0
−50 −25
150 175
Max
2
0
25
50 75 100 125
TJ − Junction Temperature − 5C
Figure 6.
Figure 7.
MINIMUM VOH AND MAXIMUM VOL
vs
JUNCTION TEMPERATURE
TYPICAL AND MAXIMUM ICC
vs
JUNCTION TEMPERATURE
4
150 175
50
VCC = 5.5 V
45
3.5
VOH, min
40
3
ICC − Supply Current − mA
VO − Output Voltage − V
VOH, min
2.5
2
VCC = 4.5 V,
Loaded per Figure 3
1.5
1
35
30
VOL, max
25
20
15
10
VOL, max
0.5
0
−50 −25
0
25
50
75
5
100
125
150 175
0
−50 −25
TJ − Junction Temperature − 5C
Figure 8.
0
25
50 75 100 125
TJ − Junction Temperature − 5C
150 175
Figure 9.
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APPLICATION INFORMATION
Power Dissipation
The power dissipation rating, often listed as the
package dissipation rating, is a function of the
ambient temperature, TA, and the airflow around the
device. This rating correlates with the device's
maximum junction temperature, sometimes listed in
the absolute maximum ratings tables. The maximum
junction temperature accounts for the processes and
materials used to fabricate and package the device,
in addition to the desired life expectancy.
There are two common approaches to estimating the
internal die junction temperature, TJ. In both of these
methods, the device internal power dissipation PD
needs to be calculated This is done by totaling the
supply power(s) to arrive at the system power
dissipation:
ǒV Sn I SnǓ
ȍ
(1)
and then subtracting the total power dissipation of the
external load(s):
ȍ(V
I Ln)
Ln
(2)
The first TJ calculation uses the power dissipation
and ambient temperature, along with one parameter:
θJA, the junction-to-ambient thermal resistance, in
degrees Celsius per watt.
The product of PD and θJA is the junction temperature
rise above the ambient temperature. Therefore:
T J + T A ) ǒPD q JAǓ
(3)
140
which the device is mounted and on the airflow over
the device and PCB. JEDEC/EIA has defined
standardized test conditions for measuring θJA. Two
commonly used conditions are the low-K and the
high-K boards, covered by EIA/JESD51-3 and
EIA/JESD51-7 respectively. Figure 10 shows the
low-K and high-K values of θJA versus air flow for this
device and its package options.
The standardized θJA values may not accurately
represent the conditions under which the device is
used. This can be due to adjacent devices acting as
heat sources or heat sinks, to nonuniform airflow, or
to the system PCB having significantly different
thermal characteristics than the standardized test
PCBs. The second method of system thermal
analysis is more accurate. This calculation uses the
power dissipation and ambient temperature, along
with two device and two system-level parameters:
• θJC, the junction-to-case thermal resistance, in
degrees Celsius per watt
• θJB, the junction-to-board thermal resistance, in
degrees Celsius per watt
• θCA, the case-to-ambient thermal resistance, in
degrees Celsius per watt
• θBA, the board-to-ambient thermal resistance, in
degrees Celsius per watt.
In this analysis, there are two parallel paths, one
through the case (package) to the ambient, and
another through the device to the PCB to the
ambient. The system-level junction-to-ambient
thermal impedance, θJA(S), is the equivalent parallel
impedance of the two parallel paths:
T J + T A ) ǒPD
q JA(S)Ǔ
(4)
where
Thermal Impedance − C/W
120
D, Low−K
q JA(S) +
DW, Low−K
100
80
DW, High−K
D, High−K
60
40
0
100
200
300
400
500
ƪǒq JC)q CAǓ
ǒq JB)q BAǓƫ
ǒq JC)q CA)q JB)q BAǓ
(5)
The device parameters θJC and θJB account for the
internal structure of the device. The system-level
parameters θCA and θBA take into account details of
the PCB construction, adjacent electrical and
mechanical components, and the environmental
conditions including airflow. Finite element (FE), finite
difference (FD), or computational fluid dynamics
(CFD) programs can determine θCA and θBA. Details
on using these programs are beyond the scope of
this data sheet, but are available from the software
manufacturers.
Figure 10. Thermal Impedance vs Air Flow
Note that θJA is highly dependent on the PCB on
8
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TB5R3D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TB5R3DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TB5R3DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TB5R3DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TB5R3DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TB5R3DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TB5R3DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TB5R3DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
TB5R3LD
ACTIVE
SOIC
D
16
40
TBD
CU SNPB
Level-1-220C-UNLIM
TB5R3LDR
ACTIVE
SOIC
D
16
2500
TBD
CU SNPB
Level-1-220C-UNLIM
TB5R3LDW
ACTIVE
SOIC
DW
16
40
TBD
CU SNPB
Level-1-220C-UNLIM
TB5R3LDWR
ACTIVE
SOIC
DW
16
2000
TBD
CU SNPB
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TB5R3DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TB5R3DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TB5R3DR
TB5R3DWR
SOIC
D
16
2500
346.0
346.0
33.0
SOIC
DW
16
2000
346.0
346.0
33.0
Pack Materials-Page 2
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Amplifiers
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amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
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