AIC1570 5-bit DAC, Synchronous PWM Power Regulator with LDO and Linear Controller FEATURES Compatible with HIP6018. Provides 3 Regulated Voltages for Micro- processor Core, Clock and GTL Power. DESCRIPTION The AIC1570 combines a synchronous voltage mode controller with a low dropout linear regulator and a linear controller as well as the monitoring and Simple Voltage-Mode PWM Control. Dual N-Channel MOSFET Synchronous Driver. Operates from +3.3V, +5V and +12V Inputs. Fast Transient Response. Full 0% to 100% Duty Ratios. ±1.0% Output Voltage for VCORE and ±2.0% protection functions in this chip. The PWM controller regulates the microprocessor core voltage with a synchronous rectified buck converter. The linear controller regulates power for the GTL Output Voltage Reference for VCLK and VGTL. bus and the linear regulator provides power for the clock driver circuit. TTL Compatible 5-bit Digital-to-Analog Core An integrated 5 bit D/A converter that adjusts the Output Voltage Selection. Range from 1.3V to core PWM output voltage from 2.1V to 3.5V in 0.1V 3.5V. increments and from 1.3V to 2.05V in 0.05V 0.1V Steps from 2.1V to 3.5V. increments. The linear regulator uses an internal 0.05V Steps from 1.3V to 2.05V. driver device to provide 2.5V±2.5%. The linear Adjustable Current Limit without External Sense controller drives with an external N-channel Resistor. MOSEFET to provide 1.5V±2.5%. Microprocessor Core Voltage Protection against This chip monitors all the output voltages. Power Shorted MOSFET. Good signal is issued when the core voltage is Power Good Output Voltage Monitor. within ±10% of the DAC setting and the other levels Over-Voltage and Over-Current Fault Monitors. are above their under-voltage levels. Over-voltage 200KHz Free-Running Oscillator Programmable protection for the core output uses the lower N- up to 350KHz. channel MOSFET to prevent output voltage above 115% of the DAC setting. The PWM over-current function monitors the output APPLICATIONS Full Motherboard Power current by using the voltage drop across the upper Regulation for current sensing resistor. Computers. DS-1570-00 MOSFET’s RDS(on), eliminating the need for a www.analog.com.tw 1 AIC1570 ORDERING INFORMATION ORDER NUMBER AIC1570-XX PACKAGING TYPE S: SMALL OUTLINE AIC1570CS (SO24) TEMPERATURE RANGE C: 0°C~+70°C PIN CONFIGURATION VCC 1 24 UGATE VID4 2 23 PHASE VID3 3 22 LGATE VID2 4 21 PGND VID1 5 20 OCSET VID0 6 19 VSEN PGOOD 7 FAULT 8 SS 9 RT 10 FB2 11 VIN2 12 18 FB1 17 COMP1 16 FB3 15 GATE3 14 GND 13 VOUT2 ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC ...............…………….....………….........…..……..................... +15V PGOOD, FAULT and GATE Voltage .....…….....………..….... GND -0.3V to VCC +0.3V Input, Output , or I/O Voltage ......…...……………………..……............ GND -0.3V to 7V Recommended Operating Conditions Supply Voltage; VCC ……...............…................... +12V±10% Ambient temperature Range ……..……………................. 0°C~70°C Junction Temperature Range ……......……….................. 0°C~100°C Thermal Information Thermal Resistance, θJA SOIC package …………………………………..…............... 100°C/W SOIC package (with 3in2 of copper) …...……….......…......... 90°C/W Maximum Junction Temperature (Plastic Package) ………………..……...... 150°C Maximum Storage Temperature Range …………………………….... -65°C ~ 150°C Maximum Lead Temperature (Soldering 10 sec) ………………………..…... 300°C TEST CIRCUIT Refer to APPLICATION CIRCUIT. 2 AIC1570 ELECTRICAL CHARACTERISTICS (Vcc=12V, TJ=25°°C, Unless otherwise specified) PARAMETER TEST CONDITIONS SYMBOL UGATE, LGATE, GATE3 and VOUT2 open ICC MIN. TYP. MAX. UNIT 1.8 5 mA VCC SUPPLY CURRENT Supply Current POWER ON RESET Rising VCC Threshold VOCSET=4.5V VCCTHR 8.6 9.5 10.4 V Falling VCC Threshold VOCSET=4.5V VCCTHF 8.2 9.2 10.2 V Rising VIN2 Under-Voltage Threshold VIN2THR 2.5 2.6 2.7 V VIN2 Under-Voltage Hysteresis VIN2HYS 130 mV Rising VOCSET1 Threshold VOCSETH 1.3 V OSCILLATOR Free Running Frequency RT=Open F Ramp. Amplitude RT=open ∆VOSC 170 200 230 1.3 KHz VP-P REFERENCE AND DAC DAC (VID0~VID4) Input Low Voltage VIDL DAC (VID0~VID4) Input High Voltage VIDH DACOUT Voltage Accuracy VDAC=1.8V~3.5V 0.8 V V 2 -1.0 +1.0 % FB2 Reference Voltage VREF2 1.240 1.265 1.290 V FB3 Reference Voltage VREF3 1.250 1.275 1.300 V +1 % 82 % LINEAR REGULATOR Regulation 10mA<IOUT2<150mA Under-Voltage Level FB2 falling Over-Current Protection Over-Current Protection During Start-up -1 FB2UV 70 430 570 mA 750 mA 3 AIC1570 ELECTRICAL CHARACTERISTICS PARAMETER TEST CONDITIONS (Continued) SYMBOL MIN. TYP. MAX. UNIT +2.5 % 80 % LINEAR CONTROLLER Regulation 0 < IGATE3 < 10mA Under-Voltage Level FB3 falling -2.5 FB3UV 70 PWM CONTROLLER ERROR AMPLIFIER DC GAIN Gain Bandwidth Product Slew Rate COMP1=10pF 76 dB GBWP 11 MHz SR 6 V/µS PWM CONTROLLER GATE DRIVER Upper Drive Source VCC=12V, VUGATE=11V RUGH 5.2 6.5 Ω Upper Drive Sink VCC=12V, VUGATE =1V RUGL 3.3 5 Ω Lower Drive Source VCC=12V, VLGATE=11V RLGH 4.1 6 Ω Lower Drive Sink VCC=12V, VLGATE=1V RLGL 3 5 Ω VOUT1 Voltage Over-Voltage Trip VSEN Rising OVP 112 115 118 % OCSET Current Source VOCSET=4.5VDC IOCSET 170 200 230 µA FAULT Sourcing Current VFAULT=10V IOVP 10 16 mA 11 µA PROTECTION Soft-Start Current ISS Chip Shutdown Soft Start Threshold 1.0 V POWER GOOD VOUT1 Upper Threshold VSEN Rising 109 110.5 112 % VOUT1 Under-Voltage VSEN Falling 90.5 92 93.5 % VOUT1 Hysteresis (VSEN/DACOUT) Upper and Lower Threshold PGOOD Voltage Low IPGOOD=-4mA 3 VPGOOD % 0.5 V 4 AIC1570 TYPICAL PERFORMANCE CHARACTERISTICS UGATE UGATE LGATE LGATE FIG.1 The gate drive waveforms 60 50 10000 CUGATE=CLGATE=CGATE VCC=12V CGATE=5000pF Resistance (kΩ) 1000 40 ICC (mA) 30 CGATE=2000pF 20 0 100 150 200 250 300 350 100 10 CGATE=660pF 10 RT Pull Down to GND RT Pull Up to +12V 400 Switching Frequency (KHz) FIG. 2 Bias Supply Current VS. Frequency PGOOD (5V/div) 1 100 150 200 250 300 350 400 450 Switching Frequency (KHz) FIG. 3 RT Resistance VS. Frequency SS SS (2V/div) VOUT1 (1V/div) VOUT2 (1V/div) VOUT3 (1V/div) FIG.4 Soft Start Interval with 3 Outputs and PGOOD VDAC=3.5V VDAC=2V VDAC=1.3V FIG. 5 Soft Start Initiates PWM Output 5 AIC1570 FAULT 0 to 400mA Load Step SS Over Load Applied Inductor Current VOUT2 10A/div FIG. 6 Over-Current Operation on Inductor FIG. 7 Transient Response of Linear Regulator VOUT1 VOUT3 (2mV/div) 2.0VDC 5A to 12A Load Step 1A to 2A Load Step FIG. 8 Transient Response of PWM Output 90 FIG. 9 Transient Response of Linear Controller 100 DACOUT=2.0V TA=25°C 80 Power MOSFET : CEB6030L 95 70 Efficiency (%) Number of Parts 90 60 50 40 30 Vo=2.8V 85 80 75 20 70 10 0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FIG. 9 DACOUT Voltage Accuracy (%) 65 Vo=2V VIN=5V Switching Frequency = 200KHz 0 2 4 6 8 10 12 Vo=1.3V 14 16 18 20 FIG.10 Efficiency vs. Load Current (A) 6 AIC1570 TYPICAL PERFORMANCE CHARACTERISTICS 215 0.6 DACOUT Voltage Drift (%) 0.8 Switching Frequency (KHz) 220 210 205 200 195 190 RT=OPEN 180 -20 0 20 40 60 80 0.2 0.0 -0.2 210 9.55 205 9.50 200 195 190 185 10 20 30 40 50 60 70 80 90 100 FIG.12 Temperature Drift of 24 Different Parts SS Charge Current (uA) OCSET Current (µA) DACOUT=2.0V 0.4 -0.6 -20 -10 0 100 FIG.11 Oscillator Frequency vs. Temperature (°C) 9.45 9.40 9.35 9.30 180 -20 0 20 40 60 80 9.25 -20 -10 100 FIG.13 OCSET Current vs.Temperature (°C) 0 10 20 30 40 50 60 70 80 90 100 FIG.14 SS Current vs. Temperature (°C) 0.3 1.0 DACOUT=2.0V VIN=5V NO LOAD NO LOAD 0.2 Vcore Drift (mV) 0.5 0.0 -0.5 -1.0 0.1 0.0 -0.1 -1.5 -2.0 10 (CONTINUED) -0.4 185 VCORE Drift Voltage (mV) 11 12 13 14 FIG.15 Vcore Drift vs. VCC (V) 15 16 17 18 -0.2 4.0 4.5 5.0 5.5 6.0 6.5 7.0 FIG.16 Vcore Drift vs. VIN (V) 7 AIC1570 BLOCK DIAGRAM PGOOD VSEN FB3 110% + GATE3 VCC + + 0.3V VIN2 + + - 90% 1.26V VOUT2 + VCC VIN2 OCSET INHiBIT POWER ON RESET 200µA 115% LUV 0.5A OCSET + + OC1 + PHASE OC2 FB2 VCC OV FAULT LOGIC & LATCH VCC OFF SOFT START FAULT 70K 4V 70K 5V GATE CONTROL + PWM COMP + 5 BIT TTL D/A CONVERTER (DAC) 10µA UGATE VCC LGATE ERROR AMP OSCILLATOR 70K PGND GND 70K 70K SS VID0 VID1 VID2 VID3 VID4 FB1 COMP1 RT PIN DESCRIPTIONS Pin 1: VCC: Pin 2: Pin 3: Pin 4: Pin 5: Pin 6: VID4: VID3: VID2: VID1: VID0: The chip power supply pin. It also provides the gate bias charge for all the MOSFETs controlled by the IC. Recommended supply voltage is 12V. 5bit DAC voltage select pin. TTL inputs used to set the internal voltage reference VDAC. When left open, these pins are internally pulled up to 5V and provide logic ones. The level of VDAC sets the converter output voltage as well as the PGOOD and OVP thresholds. Table 1 specifies the VDAC voltage for the 32 combinations of DAC inputs. Pin 7: PGOOD: Power good indicator pin. PGOOD is an open drain output. This pin is pulled low when the converter output is ±10% out of the VDAC reference voltage and 8 AIC1570 the other outputs are below their under-voltage thresholds. The PGOOD output is open for VID codes that inhibit operation. See Table 1. Pin 8: FAULT: Pin 9: SS: Pin 10: RT: This pin is low during normal operation, but it is pulled to VCC in the event of an over-voltage or over-current condition. Soft-start pin. Connect a capacitor from this pin to ground. This capacitor, along with an internal 10µA (typically) current source, sets the soft-start interval of the converter. Pulling this pin low will shut down the IC. Frequency adjustment pin. Connecting a resistor (RT) from this pin to GND, increasing the frequency. Connecting a resistor (RT) from this pin to VCC, decreasing the frequency by the following figure (Fig.3). Pin 11: FB2: Connect this pin to a resistor divider to set the linear regulator output voltage. Pin 12: VIN2: This pin supplies power to the internal regulator. Connect this pin to a suitable 3.3V source. Additionally, this pin is used to monitor the 3.3V supply. If, following a start-up cycle, the voltage drops below 2.6V (typically), the chip shuts down. A new soft-start cycle is initiated upon return of the 3.3V supply above the under-voltage threshold. Pin 13: VOUT2: Output of the linear regulator. Supplies current up to 500mA. Pin 14: GND: Signal GND for IC. All voltage levels are measured with respect to this pin. Pin 15: GATE3: Linear Controller output drive pin. This pin can drive either a Darlington NPN transistor or a N-channel MOSFET. Pin 16: FB3: Negative feedback pin for the linear controller error amplifier connect this pin to a resistor divider to set the linear controller output voltage. Pin 17: COMP1: External compensation pin. This pin is connected to error amplifier output and PWM comparator. An RC network is connected to FB1 in to compensate the voltage control feedback loop of the converter. Pin 18: FB1: The error amplifier inverting input pin. the FB1 pin and COMP1 pin are used to compensate the voltage-control feedback loop. Pin 19: VSEN: Converter output voltage sense pin. Connect this pin to the converter output. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection function. Pin 20: OCSET: Current limit sense pin. Connect a resistor ROCSET from this pin to the drain of the external highside N-MOSFET. ROCSET, an internal 200µA current source (IOCSET), and the upper NMOSFET on-resistance (RDS(ON)) set the over-current trip point according to the following equation: IPEAK = IOCSET × ROCSET RDS(ON) 9 AIC1570 Pin 21: PGND: Driver power GND pin. PGND should be connected to a low impedance ground plane in close to lower N-MOSFET source. source of the external high-side N-MOSFET. This pin detects the voltage drop across the highside N-MOSFET RDS(ON) for overcurrent protection. Pin 22: LGATE: Lower N-MOSFET gate drive pin. Pin 24: UGATE: External high-side N-MOSFET gate drive pin. Connect UGATE to gate of the external high-side N-MOSFET. Pin 23: PHASE: Over-current detection pin. Connect the PHASE pin to DESCRIPTION The AIC1570 is designed for microprocessor computer applications with 3.3V and 5V power, and 12V bias input. This IC has one PWM controller, a linear regulator, and a linear controller. The PWM controller is designed to regulate the microprocessor core voltage (VOUT1) by driving 2 MOSFETs (Q1 and Q2) in a synchronous rectified buck converter configuration. The core voltage is regulated to a level programmed by the 5 bit D/A converter. An integrated linear regulator supplies the 2.5V clock power (VOUT2). The linear controller drive an external MOSFET(Q3) to supply the GTL bus power(VOUT3) The Power-On Reset (POR) function continually monitors the input supply voltage +12V at VCC pin, the 5V input voltage at OCSET pin, and the 3.3V input at VIN2 pin. The POR function initiates softstart operation after all three input supply voltage exceed their POR thresholds. Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on SS pin rapidly increases to approximate 1V. Then an internal 10µA current source charges an external capacitor (CSS) on the SS pin to 4V. As the SS pin voltage slews from 1V to 4V, the PWM error amplifier reference input (Non-inverting terminal) and output (COMP1 pin) is clamped to a level proportional to the SS pin voltage. As the SS pin voltage slew from 1V to 4V, the output clamp generates PHASE pulses of increasing width that charge the output capacitors. Additionally both linear regulators’ reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a controlled output voltage smooth rise. Fig.4 and Fig.5 show the soft-start sequence for the typical application. The internal oscillator’s triangular waveform is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse width on PHASE pin increases. The interval of increasing pulse width continues until output reaches sufficient voltage to transfer control to the input reference clamp. Each linear output (VOUT2 and VOUT3) initially follows a ramp. When each output reaches sufficient voltage the input reference clamp slows the rate of output voltage rise. The PGOOD signal toggles ‘high’ when all output voltage levels have exceeded their under-voltage levels. Fault Protection All three outputs are monitored and protected against extreme overload. A sustained overload on any output or over-voltage on PWM output disable all converters and drive the FAULT pin to VCC. 10 AIC1570 OVER CURRENT LATCH LUV S OC1 R 0.2V INHIBIT Q S COUNTER R + FAULT LATCH VCC S SS + POR R Q FAULT 3.6V OV Fig. 10 Simplified Schematic of Fault Logic A simplified schematic is shown in figure 10. An over-voltage detected on VSEN immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. An undervoltage event on either linear output (FB2 or FB3) is ignored until the soft-start interval. Cycling the bias input voltage (+12V) off then on reset the counter and the fault latch. Over-Voltage Protection During operation, a short on the upper PWM MOSFET (Q1) causes VOUT1 to increase. When the output exceed the over-voltage threshold of 115% of DACOUT, the FAULT pin is set to fault latch and turns Q2 on as required in order to regulate VOUT1 to 115% of DACOUT. The fault latch raises the FAULT pin close to VCC potential. A separate over-voltage circuit provides protection during the initial application of power. For voltage on VCC pin below the power-on reset (and above 4V), should VSEN exceed 0.7V, the lower MOSFET (Q2) is driven on as needed to regulate VOUT1 to 0.7V. Over-Current Protection All outputs are protected against excessive overcurrent. The PWM controller uses upper MOSFET’s on-resistance, RDS(ON) to monitor the current for protection against shorted outputs. The linear regulator monitors the current limit in excess of 500mA. Additionally, both the linear regulator and controller monitor FB2 and FB3 for under-voltage to protect against excessive current. When the voltage across Q1 (ID•RDS(ON)) exceeds the level (200µA•ROCSET), this signal inhibit all outputs. Discharge soft-start capacitor (Css) with 10µA current sink, and increments the counter. Css recharges and initiates a soft-start cycle again until the counter increments to 3. This sets the fault latch to disable all outputs. Fig. 6 illustrates the over-current protection until an over load on OUT1. Should excessive current cause FB2 or FB3 to fall below the linear under-voltage threshold, the LUV signal sets the over-current latch if Css is fully charged. Cycling the bias input power off then on reset the counter and the fault latch. The over-current function for PWM controller will trip at a peak inductor current (IPEAK) determined by: IPEAK = IOCSET × ROCSET RDS(ON) 11 AIC1570 The OC trip point varies with MOSFET’s temperature. To avoid over-current tripping in the normal operating load range, determine the ROCSET resistor from the equation above with: 1. The maximum RDS(ON) at the highest junction. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK > IOUT(MAX) + (inductor ripple current) /2. PWM OUT1 Voltage Program The output voltage of the PWM converter is programmed to discrete levels between 1.3V to 3.5V. The VID pins program an internal voltage reference (DACOUT) through a TTL compatible 5 bit digital to analog converter. The VID pins can be left open for a logic 1 input, because they are internally pulled up to 5V by a 70kΩ resistor. Changing the VID inputs during operation is not recommended. All VID pin combinations resulting in an INHIBIT disable the IC and the open collector at the PGOOD pin. Shutdown Holding the SS pin low with an open drain or collector signal turns off all three regulators. The VID codes resulting in an INHIBIT as shown in Table 1 also shut down the IC. Table 1 VOUT1 Voltage Program (0=connected to GND, 1=open or connected to 5V) VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN NAME VID3 VID2 VID1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 For all package version PIN NAME DACOUT VOLTAGE VID4 VID3 VID2 VID1 1.30V 1 1 1 1 1.35V 1 1 1 1 1.40V 1 1 1 0 1.45V 1 1 1 0 1.50V 1 1 0 1 1.55V 1 1 0 1 1.60V 1 1 0 0 1.65V 1 1 0 0 1.70V 1 0 1 1 1.75V 1 0 1 1 1.80 V 1 0 1 0 1.85 V 1 0 1 0 1.90 V 1 0 0 1 1.95 V 1 0 0 1 2.00 V 1 0 0 0 2.05 V 1 0 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DACOUT VOLTAGE INHIBIT 2.1 V 2.2 V 2.3 V 2.4 V 2.5 V 2.6 V 2.7 V 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V 3.4 V 3.5 V 12 AIC1570 Layout Considerations Any inductance in the switched current path ground plane area. The GND pin should be generates a large voltage spike during the connected to the groundside of the output switching interval. The voltage spikes can capacitors. Under no circumstances should degrade efficiency, radiate noise into the circuit, GND be returned to a ground inside the CIN, and lead to device over-voltage stress. Careful Q1, Q2 loop. The GND and PGND pins component selection and tight layout of critical should be shorted right at the IC. This help to components, minimize internal ground disturbances in the and short, wide metal trace minimize the voltage spike. IC and prevents differences in ground 1) A ground plane should be used. Locate the input capacitors (CIN) close to the power potential from disrupting internal circuit operation. switches. Minimize the loop formed by CIN, 5) The wiring traces from the control IC to the the upper MOSFET (Q1) and the lower MOSFET gate and source should be sized to MOSFET (Q2) as possible. Connections carry 1A current. The traces for OUT2 need should be as wide as short as possible to only be sized for 0.5A. Locate COUT2 close to minimize loop inductance. the AIC1570 IC. 2) The connection between Q1, Q2 and output 6) The Vcc pin should be decoupled directly to inductor should be as wide as short as GND by a 1uF ceramic capacitor, trace practical. Since this connection has fast lengths should be as short as possible. voltage transitions will easily induce EMI. 3) The output capacitor (COUT) should be located as close the load as possible. Because minimize the transient load magnitude for high slew rate requires low inductance and resistance in circuit board 4) The AIC1570 is best placed over a quiet 13 AIC1570 + +12V VCC +3.3V IN GND VIN2 OCSET GATE3 UGATE +5VIN + Q3 + Q1 VOUT3 CIN PHASE + LOUT COUT3 VOUT + LGATE VOUT2 + COUT2 COUT Q2 PGND SS Css Power Plane Layer Circuit Plane Layer Via Connection to Ground Plane Fig. 11 Printed circuit board power planes and islands A multi-layer printed circuit board is recommended. Figure 11 shows the connections of the critical components in the converter. The CIN and COUT could each represent numerous following equation: ∆VOUT = ESR × ∆IOUT + ESL × ∆IOUT , where ∆T ∆IOUT is transient load current step. physical capacitors. Dedicate one solid layer for a ground plane and make all critical component After the initial transient, the ESL dependent term ground connections with vias to this layer. drops off. Because the strong relationship PWM Output Capacitors The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demand. The ESR (equivalent series resistance) and ESL (equivalent series inductance) parameters rather between output capacitor ESR and output load transient, the output capacitor is usually chosen for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage. than actual capacitance determine the buck A common way to lower ESR and raise ripple capacitor values. For a given transient load current capability is to parallel several capacitors. magnitude, the output voltage transient change In most case, multiple electrolytic capacitors of due to the output capacitor can be note by the small case size are better than a single large 14 AIC1570 The inductor must be able to withstand peak case capacitor. Output Inductor Selection Inductor value and type should be chosen based on output slew rate requirement, output ripple current without saturation, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss requirement and expected peak current. Inductor value is primarily controlled by the required current response time. The AIC1570 will provide either 0% or 100% duty cycle in response to a load transient. The response time to a transient is different for the application of load and remove of load. Most of the input supply current is supplied by the input bypass capacitor, the resulting RMS current flow in the input capacitor will heat it up. Use a mix of input bulk capacitors to control the voltage overshoot across the upper MOSFET. The L × ∆IOUT tRISE = , VIN − VOUT L × ∆IOUT tFALL = . VOUT Input Capacitor Selection ceramic capacitance for the high frequency decoupling should be placed very close to the Where ∆IOUT is transient load current step. upper MOSFET to suppress the voltage induced in the parasitic circuit impedance. The buck capacitors to supply the RMS current is approximate equal to: In a typical 5V input, 2V output application, a 3µH inductor has a 1A/µS rise time, resulting in a 5µS IRMS = (1− D) × D × I2 OUT + 1 VIN × D ×ç ÷ 12 f ×L 2 delay in responding to a 5A load current step. To optimize performance, different combinations of , where D = input and output voltage and expected loads may require different inductor value. A smaller value of inductor will improve the transient response at the expense of increase output ripple voltage and VOUT VIN The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. inductor core saturation rating. Peak current in the inductor will be equal to the PWM MOSFET Selection maximum output load current plus half of inductor ripple current. The ripple current is approximately equal to: (VIN − VOUT) × VOUT IRIPPLE = ; f × L × VIN f = AIC1570 oscillator frequency. In high current PWM application, the MOSFET power dissipation, package type and heatsink are the dominant design factors. The conduction loss is the only component of power dissipation for the lower MOSFET, since it turns on into near zero voltage. The upper MOSFET has conduction loss 15 AIC1570 and switching loss. The gate charge losses are on required efficiency or allowable thermal proportional to the switching frequency and are dissipation. dissipated by the AIC1570. However, the gate charge increases the switching interval, tSW which increase the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance Rectifier Schottky diode is a clamp that prevent the loss parasitic MOSFET body diode from conducting during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode’s rated reverse breakdown voltage must be greater than twice the maximum input voltage. specifications. Linear Controller MOSFET Selection PUPPER = IOUT 2 × RDS(ON) × D + IOUT × VIN × tSW × f 2 The equations above do not model power loss due to the reverse recovery of the lower junction temperature below the maximum rating while operation at the highest expected ambient temperature. MOSFET’s body diode. The RDS(ON) is different for the two previous equations even if the type devices is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Logic level MOSFETs should be selected based on on-resistance considerations, RDS(ON) should be chosen base on input and output voltage, allowable power dissipation and required PLINEAR = IOUT2 × (VIN2 − VOUT2) Select a package and heatsink that maintains PLOWER = IOUT 2 × RDS(ON) × (1 − D) maximum The power dissipated in a linear regulator is : output current. Power Linear Output Capacitor The output capacitors for the linear regulator and linear controller provide dynamic load current. The linear controller uses dominant pole compensation integrated in the error amplifier and is insensitive to output capacitor selection. COUT3 should be selected for transient load regulation. The output capacitor for the linear regulator provides loop stability. dissipation should be calculated based primarily 16 AIC1570 APPLICATION CIRCUIT C18 +12VIN R15 VCC 10 1000pF R2 1 20 C16 1µF 24 23 +3.3VIN + C19 1000µF VIN2 Q3 GATE3 VOUT3 1.5V R11 FB3 21 16 19 + 1µH C1-C7 6 x 1000µF 1uF PHASE 3.5µH Q2 LGATE +5VIN GND VOUT1 L2 + C24-36 15 1.87K R12 10K + C43-46 4 x 1000µF C15 Q1 UGATE 12 22 L1 OCSET 2.2K D5820 PGND R4 4.99K 7 x 1000µF VSEN C40 0.68µF VOUT2 VOUT2 R8 2.21K FB1 13 18 2.5V + C47 270uF R13 10K FB2 R10 160K C41 10pF 11 R9 732K C42 R14 10K 17 7 PGOOD FAULT VID0 6 8 VID1 5 10 VID2 4 VID3 3 VID4 2 9 14 2.2nF COMP1 RT SS C48 40nF 17 AIC1570 PHYSICAL DIMENSIONS 24 LEAD PLASTIC SO (300 mil) (unit: mm) D E H e B A SYMBOL MIN MAX A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 15.20 15.60 E 7.40 7.60 e A1 C L 1.27(TYP) H 10.00 10.65 L 0.40 1.27 UNIT: mm 18