TI SN74ACT86D

SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
D
D
D
Inputs Are TTL-Voltage Compatible
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPS
SN54ACT86 . . . J OR W PACKAGE
SN74ACT86 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
description
A common application is as a true/complement
element. If one of the inputs is low, the other input
is reproduced in true form at the output. If one of
the inputs is high, the signal on the other input is
reproduced inverted at the output.
The SN54ACT86 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The SN74ACT86 is characterized for
operation from – 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
SN54ACT86 . . . FK PACKAGE
(TOP VIEW)
1B
1A
NC
VCC
4B
14
2
1Y
NC
2A
NC
2B
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
The ’ACT86 are quadruple 2-input exclusive-OR
gates. The devices perform the Boolean functions
Y = A B or Y = AB + AB in positive logic.
1
NC – No internal connection
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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• DALLAS, TEXAS 75265
1
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
logic symbol†
1A
1B
2A
2B
3A
3B
4A
4B
1
=1
3
2
4
6
5
1Y
2Y
9
8
10
12
11
13
3Y
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE-OR
=1
These five equivalent exclusive-OR symbols are valid for an ’ACT86 gate in positive logic; negation may
be shown at any two ports.
LOGIC-IDENTITY ELEMENT
EVEN-PARITY ELEMENT
=
2k
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
2
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
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ODD-PARITY ELEMENT
2k + 1
The output is active (high)
if an odd number of inputs
(i.e., only 1 of the 2) are
active.
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . 1.25 W
DB package . . . . . . . . . . . . . . . . . . 0.5 W
N package . . . . . . . . . . . . . . . . . . . 1.1 W
PW package . . . . . . . . . . . . . . . . . . 0.5 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
recommended operating conditions (see Note 3)
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t /∆v
Low-level output current
High-level input voltage
2
2
0.8
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
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UNIT
V
V
0.8
V
VCC
VCC
V
– 24
– 24
mA
24
24
mA
VCC
VCC
0
0
V
0
8
0
8
ns / V
– 55
125
– 40
85
°C
3
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = – 50 µA
VOH
IOH = – 24 mA
IOH = – 50 mA†
IOH = – 75 mA†
TA = 25°C
TYP
MAX
SN54ACT86
MIN
MAX
IOL = 50 mA†
IOL = 75 mA†
MIN
4.49
4.4
5.5 V
5.4
5.49
5.4
5.4
4.5 V
3.86
3.7
3.76
5.5 V
4.86
4.7
4.76
MAX
V
3.85
3.85
4.5 V
0.001
0.1
0.1
5.5 V
0.001
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
0.1
VI = VCC or GND
VI = VCC or GND,
∆ICC‡
One input at 3.4 V,
Other inputs at GND or VCC
IO = 0
V
1.65
5.5 V
II
ICC
UNIT
4.4
5.5 V
IOL = 24 mA
SN74ACT86
4.4
5.5 V
IOL = 50 µA
VOL
MIN
1.65
5.5 V
±0.1
±1
±1
µA
5.5 V
4
80
40
µA
1.6
1.5
mA
5.5 V
0.6
Ci
VI = VCC or GND
5V
2.6
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
"
switching characteristics over recommended operating free-air temperature range,
0.5 V (unless otherwise noted) (see Figure 1)
VCC = 5 V
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
TA = 25°C
MIN
TYP
MAX
SN54ACT86
MIN
SN74ACT86
MAX
MIN
MAX
1.5
8.5
9.5
1
10
1
10
1.5
7
9.5
1
10.5
1
10.5
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
POST OFFICE BOX 655303
TEST CONDITIONS
TYP
UNIT
CL = 50 pF, f = 1 MHz
25
pF
• DALLAS, TEXAS 75265
SN54ACT86, SN74ACT86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCAS534A – AUGUST 1995 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
TEST
S1
tPLH/tPHL
Open
From Output
Under Test
CL = 50 pF
(see Note A)
S1
Open
1.5 V
1.5 V
0V
tPHL
tPLH
2 × VCC
500 Ω
3V
Input
(see Note B)
In-Phase
Output
50% VCC
tPLH
tPHL
500 Ω
Out-of-Phase
Output
LOAD CIRCUIT
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr
C. The outputs are measured one at a time with one input transition per measurement.
v 2.5 ns, tf v 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
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5
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