ALD ALD1726SA

ADVANCED
LINEAR
DEVICES, INC.
ALD1726E/ALD1726
EPAD™ ULTRA MICROPOWER OPERATIONAL AMPLIFIER
KEY FEATURES
BENEFITS
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• Eliminates manual and elaborate
system trimming procedures
• Remote controlled automated trimming
• In-System Programming capability
• No external components
• No internal chopper clocking noise
• No chopper dynamic power dissipation
• Simple and cost effective
• Small package size
• Extremely small total functional
volume size
• Low system implementation cost
• Micropower and Low Voltage
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•
EPAD ( Electrically Programmable Analog Device)
User programmable VOS trimmer
Computer-assisted trimming
Rail-to-rail input/output
Compatible with standard EPAD Programmer
High precision through in-system circuit precision trimming
Reduces or eliminates VOS, PSRR, CMRR and TCVOS errors
System level “calibration” capability
Application-Specific Programming mode
In-System Programming mode
Electrically programmable to compensate for
external component tolerances
Achieves 0.01pA input bias current and 50µV
input offset voltage simultaneously
Compatible with industry standard pinout
GENERAL DESCRIPTION
APPLICATIONS
The ALD1726E/ALD1726 is a monolithic rail-to-rail ultra-micropower
precision CMOS operational amplifier with integrated user programmable
EPAD (Electrically Programmable Analog Device) based offset voltage
adjustment. The ALD1726E/ALD1726 is a direct replacement of the
ALD1706 operational amplifier, with the added feature of user-programmable offset voltage trimming resulting in significantly enhanced total
system performance and user flexibility. EPAD technology is an exclusive
ALD design which has been refined for analog applications where precision voltage trimming is necessary to achieve a desired performance. It
utilizes CMOS FETs as in-circuit elements for trimming of offset voltage
bias characteristics with the aid of a personal computer under software
control. Once programmed, the set parameters are stored indefinitely
within the device even after power-down. EPAD offers the circuit designer
a convenient and cost-effective trimming solution for achieving the very
highest amplifier/system performance.
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The ALD1726E/ALD1726 operational amplifier features rail-to-rail input
and output voltage ranges, tolerance to over-voltage input spikes of
300mV beyond supply rails, extremely low input currents of 0.01pA typical,
high open loop voltage gain, useful bandwidth of 200KHz, slew rate of 0.17
V/µs, and low typical supply current of 25µA.
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Sensor interface circuits
Transducer biasing circuits
Capacitive and charge integration circuits
Biochemical probe interface
Signal conditioning
Portable instruments
High source impedance electrode
amplifiers
Precision Sample and Hold amplifiers
Precision current to voltage converter
Error correction circuits
Sensor compensation circuits
Precision gain amplifiers
Periodic In-system calibration
System output level shifter
PIN CONFIGURATION
8
VE2
7
V+
3
6
OUT
4
5
N/C
VE1
1
-IN
2
+IN
V-
ORDERING INFORMATION
Operating Temperature Range
-55°C to +125°C
0°C to +70°C
0°C to +70°C
8-Pin
CERDIP
Package
8-Pin
Small Outline
Package (SOIC)
8-Pin
Plastic Dip
Package
ALD1726E DA
ALD1726 DA
ALD1726E SA
ALD1726 SA
ALD1726E PA
ALD1726 PA
2
TOP VIEW
DA, PA, SA PACKAGE
* Contact factory for industrial temperature range
© 1998 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com
FUNCTIONAL DESCRIPTION
The ALD1726E/ALD1726 uses EPADs as in-circuit elements for trimming of offset voltage bias characteristics.
Each ALD1726E/ALD1726 has a pair of EPAD-based circuits connected such that one circuit is used to adjust VOS
in one direction and the other circuit is used to adjust VOS in
the other direction.
Functional Description of ALD1726E
While each of the EPAD devices is a monotonically adjustable programmable device, the VOS of the ALD1726E can be
adjusted many times in both directions. Once programmed,
the set V OS levels are stored permanently, even when the
device power is removed.
The ALD1726E provides the user with an operational amplifier that can be trimmed with user application-specific programming or in-system programming conditions. User application-specific circuit programming refers to the situation
where the Total Input Offset Voltage of the ALD1726E (VOST)
can be trimmed with the actual intended operating conditions.
The ALD1726E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage
program range, which is ideal for applications that require
electrical offset voltage programming.
For example, an application circuit may have +6V and -2.5V
power supplies, and the operational amplifier input is biased
at +0.7V, and the average operating temperature is at 55°C.
The circuit can be wired up to these conditions within an
environmental chamber, and the ALD1726E can be inserted
into a test socket connected to this circuit while it is being
electrically trimmed. Any error in V OS due to these bias
conditions can be automatically zeroed out. The Total V OS
error is now limited only by the adjustable range and the
stability of V OS, and the input noise voltage of the operational
amplifier. Therefore, this Total V OS error now includes V OS
as VOS is traditionally specified; plus the VOS error contributions from PSRR, CMRR, TCVOS, and noise. Typically this
total V OS error term (VOST ) is approximately ±50µV for the
ALD1726E.
The VOS contribution due to PSRR, CMRR, TCVOS and
external components can be large for operational amplifiers
without trimming. Therefore the ALD1726E with EPAD trimming is able to provide much improved system performance
by reducing these other sources of error to provide significantly reduced VOST.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD1726E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD1726E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD1726E offset voltage
from operating bias conditions accounted for, any residual
errors introduced by other circuit components, such as resis-
2
tor or sensor induced voltage errors, can also be corrected.
In this way, the “in-system” circuit output can be adjusted to
a desired level eliminating other trimming components.
Functional Description of ALD1726
The ALD1726 is pre-programmed at the factory under standard operating conditions for minimum equivalent input offset
voltage. The ALD1726 offers similar programmable features
as the ALD1726E, but with more limited offset voltage program range. It is intended for standard operational amplifier
applications where little or no electrical programming by the
user is necessary.
USER PROGRAMMABLE VOS FEATURE
Each ALD1726E/ALD1726 has two pins named VE1 and
VE2 which are internally connected to an internal offset bias
circuit. VE1/VE2 have initial typical values of 1.0 to 1.5 Volt.
The voltage on these pins can be programmed using the ALD
E100 EPAD Programmer and the appropriate Adapter Module. The useful programming range of VE1 and VE2 is 1.2
Volt to 3.0 Volts. VE1 and VE2 pins are programming pins,
used during programming mode. The Programming pin is
used during electrical programming to inject charge into the
internal EPADs. Increases of VE1 decrease the offset voltage while increases of VE2 increase the offset voltage of the
operational amplifier. The injected charge is permanently
stored and determines the offset voltage of the operational
amplifier. After programming, VE1 and VE2 terminals must
be left open to settle on a voltage determined by internal bias
currents.
During programming, the voltages on VE1 or VE2 are increased incrementally to set the offset voltage of the operational amplifier to the desired Vos. Note that desired VOS can
be any value within the offset voltage programmable ranges,
and can be either zero, a positive value or a negative value.
This VOS value can also be reprogrammed to a different
value at a later time, provided that the useful VE1 or VE2
programming voltage range has not been exceeded. VE1 or
VE2 pins can also serve as capacitively coupled input pins.
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
While programming, V+, VE1 and VE2 pins may be alternately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires the
ALD1726E/ALD1726 application circuit to accommodate
these programming pulses. This can be accomplished by
adding resistors at certain appropriate circuit nodes. For
more information, see Application Note AN1700.
Advanced Linear Devices
ALD1726E/ALD1726
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+
Differential input voltage range
Power dissipation
Operating temperature range PA,SA package
DA package
Storage temperature range
Lead temperature, 10 seconds
13.2V
-0.3V to V+ +0.3V
600 mW
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25 oC V S = ±2.5V unless otherwise specified
Parameter
Symbol
Min
Supply Voltage
VS
V+
1726E
Typ
1726
Typ
Max
Min
Max
Unit
Test Conditions
±1.0
±5.0
±1.0
±5.0
V
2.0
10.0
2.0
10.0
V
Single Supply
150
µV
RS ≤ 100KΩ
Initial Input Offset Voltage1
VOS i
Offset Voltage Program Range 2
∆VOS
Programmed Input Offset
Voltage Error 3
VOS
50
100
75
150
µV
At user specified
target offset voltage
Total Input Offset Voltage 4
VOST
50
100
75
150
µV
At user specified
target offset voltage
Input Offset Current 5
IOS
10
0.01
50
±10
100
±20
0.01
75
±1
±5
240
Input Bias Current 5
IB
Input Voltage Range 6
VIR
Input Resistance
RIN
Input Offset Voltage Drift 7
TCVOS
7
7
Initial Power Supply
PSRR i
80
Initial Common Mode
Rejection Ratio 8
CMRR i
83
Large Signal Voltage Gain
AV
Output Voltage Range
VO low
VO high
4.99
VO low
VO high
2.40
0.01
-0.3
-2.8
10
5.3
+2.8
0.01
-0.3
-2.8
1014
mV
10
pA
240
pA
TA = 25°C
0°C ≤ TA ≤ +70°C
10
pA
TA = 25°C
V
V
V+ = +5V
VS = ±2.5V
5.3
+2.8
Ω
1014
µV/°C
RS ≤ 100KΩ
80
dB
RS ≤ 100KΩ
83
dB
RS ≤ 100KΩ
V/mV
V/mV
RL =1MΩ
0°C ≤ TA ≤ +70°C
Rejection Ratio 8
Output Short Circuit Current
32
20
100
32
20
0.001
4.999
0.01
-2.48
-2.40
2.48
ISC
4.99
2.40
200
100
0.001
4.999
0.01
V
V
R L =1MΩ V+ = 5V
0°C ≤ TA ≤ +70°C
-2.48
-2.40
V
R L =100KΩ
2.48
V
0°C ≤ TA ≤ +70°C
200
µA
\* NOTES 1 through 9, see section titled "Definitions and Design Notes".
ALD1726E/ALD1726
Advanced Linear Devices
3
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
TA = 25oC VS = ±2.5V unless otherwise specified
Parameter
Symbol
Supply Current
IS
Power Dissipation
PD
Input Capacitance
CIN
Maximum Load Capacitance
Min
1726E
Typ
Max
25
40
Min
1726
Typ
25
200
Max
Unit
Test Conditions
40
µA
VIN = 0V
No Load
200
µW
VS = ±2.5V
1
1
pF
CL
25
25
pF
Equivalent Input Noise Voltage
en
55
55
nV/√Hz
f = 1KHz
Equivalent Input Current Noise
in
0.6
0.6
fA/√Hz
f =10Hz
Bandwidth
BW
400
400
KHz
Slew Rate
SR
0.17
0.17
V/µs
AV = +1
RL = 1MΩ
Rise time
tr
1.0
1.0
µs
RL = 1MΩ
20
20
%
RL = 1MΩ,
CL = 25pF
10
10
µs
0.1%
AV = 1,RL=1MΩ
CL = 25pF
Overshoot Factor
Settling Time
ts
T A = 25 oC VS = ±2.5V unless otherwise specified
1726E
Parameter
Symbol
Average Long Term Input Offset
Voltage Stability 9
∆ VOS
∆ time
Initial VE Voltage
VE1 i, VE2 i
Programmable VE Range
∆VE1, ∆VE2
Programmed VE Voltage Error
e(VE1-VE2)
VE Pin Leakage Current
ieb
4
Min
Typ
1.0
1726
Max
Min
Typ
Max
Unit
µV/
1000 hrs
0.02
0.02
1.0
1.5
V
2.0
0.5
V
0.1
0.1
%
-5
-5
µA
Advanced Linear Devices
Test Conditions
ALD1726E/ALD1726
VS = ±2.5V -55°C ≤ T A ≤ +125°C unless otherwise specified
1726E
Min
Typ
1726
Parameter
Symbol
Max
Min
Initial Input offset Voltage
VOS i
Input Offset Current
I OS
2.0
2.0
nA
Input Bias Current
IB
2.0
2.0
nA
Initial Power Supply
Rejection Ratio 8
PSRR i
75
75
dB
RS ≤ 1MΩ
Initial Common Mode
RejectionRatio 8
CMRR i
83
83
dB
RS ≤ 1MΩ
Large Signal Voltage Gain
AV
15
50
V/mV
RL = 1MΩ
Output Voltage Range
VO low
VO high
2.30
V
V
R L = 1MΩ
Unit
Test Conditions
0.7
Max
0.7
50
-2.40
2.40
Typ
15
-2.30
2.30
-2.40
2.40
-2.30
Unit
Test Conditions
mV
RS ≤ 100KΩ
TA = 25oC VS = ±1.0V unless otherwise specified
1726E
Min
Typ
1726
Parameter
Symbol
Initial Power Supply
8
Rejection Ratio
PSRR i
70
70
dB
RS ≤ 1MΩ
Initial Common Mode
Rejection Ratio 8
CMRRi
70
70
dB
RS ≤ 1MΩ
Large Signal Voltage Gain
AV
50
50
V/mV
RL = 1MΩ
Output Voltage Range
VO low
VO high
V
R L = 1MΩ
-0.95
0.9
0.95
Max
Min
-0.9
Typ
-0.95
0.90
Max
-0.90
0.95
Bandwidth
BW
0.3
0.3
MHz
Slew Rate
SR
0.17
0.17
V/µs
ALD1726E/ALD1726
Advanced Linear Devices
AV = +1, C L = 50pF
5
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
OUTPUT VOLTAGE SWING AS A FUNCTION
OF SUPPLY VOLTAGE
1000
±25°C ≤ TA ≤ +125°C
RL = 100KΩ
±5
OPEN LOOP VOLTAGE
GAIN (V/mV)
OUTPUT VOLTAGE SWING (V)
±6
±4
±3
±2
100
10
±55°C ≤ TA ≤ +125°C
RL = 100KΩ
±1
1
0
±1
±2
±3
±4
±5
±6
±7
±4
±6
SUPPLY VOLTAGE (V)
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
100
SUPPLY CURRENT (µA)
VS = ±2.5V
100
10
1.0
0.1
INPUTS GROUNDED
OUTPUT UNLOADED
-25°C +25°C
80
TA = -55°C
60
40
20
+70°C
AMBIENT TEMPERATURE (°C)
±2
±3
±4
SUPPLY VOLTAGE (V)
ADJUSTMENT IN INPUT OFFSET VOLTAGE
AS A FUNCTION OF CHANGE IN VE1 AND VE2
OPEN LOOP VOLTAGE GAIN AS
A FUNCTION OF FREQUENCY
-50
-25
0
25
50
75
100
125
0
±1
±5
±6
120
6
OPEN LOOP VOLTAGE
GAIN (db)
10
8
VE2
4
2
0
-2
-4
VE1
-6
-8
-10
VS = ±2.5V
TA = 25°C
100
80
60
0
40
45
20
90
0
135
180
-20
0.0
0.1
0.2
0.3
0.4
0.5
0.6
CHANGE IN VE1 AND VE2 (V)
Advanced Linear Devices
1
10
100
1K
10K 100K
FREQUENCY (Hz)
1M
PHASE SHIFT IN DEGREES
CHANGE IN INPUT OFFSET
VOLTAGE ∆VOS (mV)
+125°C
0
0.01
6
±8
SUPPLY VOLTAGE (V)
1000
INPUT BIAS CURRENT (pA)
±2
0
10M
ALD1726E/ALD1726
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
LARGE - SIGNAL TRANSIENT
RESPONSE
±7
COMMON MODE INPUT
VOLTAGE RANGE (V)
±6
2V/div
VS = ±1.0V
TA = 25°C
RL = 100KΩ
CL= 25pF
500mV/div
10µs/div
TA = 25°C
±5
±4
±3
±2
±1
0
0
±1
±2
±3
±4
±5
±6
±7
SUPPLY VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN AS AFUNCTION
OF LOAD RESISTANCE
SMALL - SIGNAL TRANSIENT
RESPONSE
1000
VS = ±2.5V
TA = 25°C
RL = 100KΩ
CL= 25pF
OPEN LOOP VOLTAGE
GAIN (V/mV)
100mV/div
100
10
VS = ±2.5V
TA = 25°C
1
10K
100K
1M
50mV/div
10µs/div
10M
LOAD RESISTANCE (Ω)
LARGE - SIGNAL TRANSIENT
RESPONSE
100
VS = ±2.5V
TA = 25°C
RL = 100KΩ
CL= 25pF
PERCENTAGE OF UNITS (%)
5V/div
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
80
EXAMPLE A:
VOST AFTER EPAD
PROGRAMMING
VOST TARGET = 0.0µV
EXAMPLE B:
VOST AFTER EPAD
PROGRAMMING
VOST TARGET = -750µV
60
VOST BEFORE EPAD
PROGRAMMING
40
20
2V/div
10µs/div
0
-2500
-2000
-1500
-1000
-500
0
500
1000
1500
2000
2500
TOTAL INPUT OFFSET VOLTAGE (µV)
ALD1726E/ALD1726
Advanced Linear Devices
7
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE (µV)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500
PSRR = 80 dB
400
EXAMPLE A:
VOS EPAD PROGRAMMED
AT VSUPPLY = +5V
300
EXAMPLE B:
VOS EPAD
PROGRAMMED
AT VSUPPLY = +8V
200
100
0
1
0
2
3
4
5
6
7
8
9
10
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
SUPPLY VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500
VSUPPLY = ±5V
CMRR = 80dB
400
300
EXAMPLE B:
VOS EPAD
PROGRAMMED
AT VIN = -4.3V
200
EXAMPLE A:
VOS EPAD PROGRAMMED
AT VIN = 0V
100
EXAMPLE C:
VOS EPAD PROGRAMMED
AT VIN = +5V
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE (µV)
COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50
COMMON MODE VOLTAGE RANGE OF 0.5V
40
30
VOS EPAD
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
20
CMRR = 80dB
10
0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
COMMON MODE VOLTAGE (V)
8
Advanced Linear Devices
ALD1726E/ALD1726
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
2500
2500
2000
2000
TOTAL INPUT OFFSET VOLTAGE (µV)
TOTAL INPUT OFFSET VOLTAGE (µV)
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
1500
1000
VOS BUDGET AFTER
EPAD PROGRAMMING
500
0
-500
+
X
-1000
-1500
-2000
VOS BUDGET BEFORE
EPAD PROGRAMMING
1500
VOS BUDGET AFTER
EPAD PROGRAMMING
1000
500
+
0
X
-500
-1000
-1500
VOS BUDGET BEFORE
EPAD PROGRAMMING
-2000
-2500
-2500
EXAMPLE B
2500
2500
2000
2000
TOTAL INPUT OFFSET VOLTAGE (µV)
TOTAL INPUT OFFSET VOLTAGE (µV)
EXAMPLE A
1500
1000
VOS BUDGET BEFORE
EPAD PROGRAMMING
500
0
-500
-1000
+
X
-1500
-2000
VOS BUDGET AFTER
EPAD PROGRAMMING
1500
1000
500
+
0
X
-500
-1000
-1500
-2000
-2500
VOS BUDGET AFTER
EPAD PROGRAMMING
VOS BUDGET BEFORE
EPAD PROGRAMMING
-2500
EXAMPLE C
EXAMPLE D
Device input VOS
PSRR equivalent VOS
+
Total Input VOS
after EPAD
Programming
CMRR equivalent VOS
TA equivalent VOS
X
Noise equivalent VOS
External Error equivalent VOS
ALD1726E/ALD1726
Advanced Linear Devices
9
DEFINITIONS AND DESIGN NOTES:
ADDITIONAL DESIGN NOTES:
1. Initial Input Offset Voltage is the initial offset voltage of the
ALD1726E/ALD1726 operational amplifier when shipped from
the factory. The device has been pre-programmed and tested
for programmability.
A. The ALD1726E/ALD1726 is internally compensated for unity
gain stability using a novel scheme which produces a single pole
role off in the gain characteristics while providing more than 60
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1726E/ALD1726 will typically drive 25pF of
external load capacitance.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjustment in either the positive or the negative direction of the input
offset voltage from an initial input offset voltage. The input
offset programming pins, VE1 or VE2, change the input offset
voltage in the negative or positive direction, respectively. User
specified target offset voltage can be any offset voltage within
this programming range.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usually this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCVOS and noise. It can also include errors
introduced by external components, at a system level. Programmed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
6. Input Voltage Range is determined by two parallel complementary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD1726E/
ALD1726, the switching point between the two stages occur at
approximately 1.5V below positive supply voltage.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
the offset voltage from PSRR and CMRR is set to zero under the
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125°C
extrapolated to TA = 25 °C, assuming activation energy of
1.0eV. This parameter is sample tested.
10
B. The ALD1726E/ALD1726 has complementary p-channel
and n-channel input differential stages connected in parallel to
accomplish rail-to-rail input common mode voltage range. The
switching point between the two differential stages is 1.5V below
positive supply voltage. For applications such as inverting
amplifier or non-inverting amplifier with a gain larger than 2.5
(5V operation), the common mode voltage does not make
excursions below this switching point. However, this switching
does take place if the operational amplifier is connected as a railto-rail unity gain buffer and the design must allow for input offset
voltage variations.
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the railto-rail input and output feature, makes the ALD1726E/ALD1726
an effective analog signal buffer for high source impedance
sensors, transducers, and other circuit networks.
D. The ALD1726E/ALD1726 has static discharge protection.
Care must be exercised when handling the device to avoid
strong static fields that may degrade a diode junction, causing
increased input leakage currents. The user is advised to power
up the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages not to exceed 0.3V of the
power supply voltage levels.
E. VE1 and VE2 are high impedance terminals, as the internal
bias currents are set very low to a few microamperes to
conserve power. For some applications, these terminals may
need to be shielded from external coupling sources. For example, digital signals running nearby may cause unwanted
offset voltage fluctuations. Care during the printed circuit board
layout to place ground traces around these pins and to isolate
them from digital lines will generally eliminate such coupling
effects. In addition, optional decoupling capacitors of 1000pF or
greater value can be added to VE1 and VE2 terminals.
F. The ALD1726E/ALD1726 is designed for use in low voltage,
micropower circuits. The maximum operating voltage during
normal operation should remain below 10 Volts at all times. Care
should be taken to insure that the application in which the device
is used do not experience any positive or negative transient
voltages that will cause any of the terminal voltages to exceed
this limit.
G. All inputs or unused pins except VE1 and VE2 pins should be
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins
is very high. If any of these pins are left undefined, they may
cause unwanted oscillation or intermittent excessive current
drain. As these devices are built with CMOS technology, normal
operating and storage temperature limits, ESD and latchup
handling precautions pertaining to CMOS device handling
should be observed.
Advanced Linear Devices
ALD1726E/ALD1726