SCES414G − NOVEMBER 2002 − REVISED SEPTEMBER 2003 D Available in the Texas Instruments DBV OR DCK PACKAGE (TOP VIEW) NanoStar and NanoFree Packages D D D D D D D D Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 6.3 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) In1 GND In0 1 6 2 5 3 4 In2 VCC Y YEA, YEP, YZA OR YZP PACKAGE (BOTTOM VIEW) In0 GND In1 3 4 2 5 1 6 Y VCC In2 description/ordering information This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G57 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All inputs can be connected to VCC or GND. This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT−) signals. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar − WCSP (DSBGA) 0.17-mm Small Bump − YEA SN74LVC1G57YEAR NanoFree − WCSP (DSBGA) 0.17-mm Small Bump − YZA (Pb-free) −40°C to 85°C NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP TOP-SIDE MARKING‡ SN74LVC1G57YZAR Tape and reel _ _ _CL_ SN74LVC1G57YEPR NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) SN74LVC1G57YZPR SOT (SOT-23) − DBV Tape and reel SN74LVC1G57DBVR CA7_ SOT (SC-70) − DCK Tape and reel SN74LVC1G57DCKR CL_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES414G − NOVEMBER 2002 − REVISED SEPTEMBER 2003 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS In0 OUTPUT Y L L H L H L L H L H In2 In1 L L L H H L H L L L H L H L H H L H H H H H logic diagram (positive logic) In0 3 4 In1 In2 2 1 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y SCES414G − NOVEMBER 2002 − REVISED SEPTEMBER 2003 FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND 1 2-input AND with both inputs inverted 4 2-input NAND with inverted input 2, 3 2-input OR with inverted input 2, 3 2-input NOR 4 2-input NOR with both inputs inverted 1 2-input XNOR 5 logic configurations VCC A Y B A VCC A A Y B Y B 1 6 2 5 3 4 A B A Y Y B Figure 1. 2-Input AND Gate 1 6 2 5 3 4 B Y Figure 2. 2-Input NAND Gate With Inverted A Input VCC A VCC A B B A B Y Y Y A 1 6 2 5 3 4 B A Y Y A B Figure 3. 2-Input NAND Gate With Inverted B Input 1 6 2 5 3 4 B Y Figure 4. 2-Input NOR Gate VCC A Y B A 1 6 2 5 3 4 B Y Figure 5. 2-Input XNOR Gate POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES414G − NOVEMBER 2002 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) Operating VCC Supply voltage VI VO Input voltage Data retention only Output voltage VCC = 1.65 V VCC = 2.3 V IOH MAX 5.5 VCC = 3 V VCC = 2.3 V 0 5.5 V 0 VCC −4 V −8 mA −24 −32 4 8 16 Low-level output current UNIT V 1.5 −16 High-level output current VCC = 4.5 V VCC = 1.65 V IOL MIN 1.65 VCC = 3 V 24 VCC = 4.5 V 32 mA TA Operating free-air temperature −40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES414G − NOVEMBER 2002 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 1.65 V 0.79 1.16 2.3 V 1.11 1.56 3V 1.5 1.87 4.5 V 2.16 2.74 5.5 V 2.61 3.33 1.65 V 0.39 0.62 2.3 V 0.58 0.87 3V 0.84 1.14 4.5 V 1.41 1.79 5.5 V 1.87 2.29 1.65 V 0.37 0.62 2.3 V 0.48 0.77 3V 0.56 0.87 4.5 V 0.71 1.04 0.71 1.11 VT+ Positive-going input threshold voltage VT− Negative-going input threshold voltage ∆VT Hysteresis (VT+ − VT−) 5.5 V IOH = −100 mA IOH = −4 mA VOH 1.65 V to 5.5 V 1.65 V VCC−0.1 1.2 2.3 V 1.9 IOH = −8 mA IOH = −16 mA IOL = 100 mA IOL = 4 mA 1.65 V 0.45 2.3 V 0.3 0.4 3V VI = 5.5 V or GND VI or VO = 5.5 V ICC ∆ICC VI = 5.5 V or GND, One input at VCC − 0.6 V, 0 1.65 V to 5.5 V 3 V to 5.5 V Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. V 0.55 0 to 5.5 V IO = 0 Other inputs at VCC or GND V 0.55 4.5 V IOL = 32 mA V 3.8 0.1 IOL = 24 mA V V 1.65 V to 5.5 V IOL = 8 mA IOL = 16 mA UNIT 2.3 4.5 V IOH = −32 mA II Ioff MAX 2.4 3V IOH = −24 mA VOL TYP† VCC 3.3 V ±1 mA ±10 mA 10 mA 500 mA 3.5 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6) PARAMETER tpd FROM (INPUT) TO (OUTPUT) Any In Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 3.2 14.4 2 8.3 1.5 6.3 1.1 5.1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns 5 SCES414G − NOVEMBER 2002 − REVISED SEPTEMBER 2003 operating characteristics, TA = 25°C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS f = 10 MHz POST OFFICE BOX 655303 VCC = 1.8 V TYP VCC = 2.5 V TYP 20 • DALLAS, TEXAS 75265 20 VCC = 3.3 V TYP 21 VCC = 5 V TYP 22 UNIT pF SCES414G − NOVEMBER 2002 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 6. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MECHANICAL DATA MPDS114 – FEBRUARY 2002 DCK (R-PDSO-G6) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 6 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-3/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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