5881 Data Sheet 26180.16 5881 BiMOS II DUAL 8-BIT LATCHED DRIVER BiMOS II DUAL 8-BIT LATCHED DRIVER WITH READ BACK With 16 CMOS data latches (two sets of eight), CMOS control circuitry for each set of latches, and a bipolar saturated driver for each latch, the UCN5881EP provides low-power interface with maximum flexibility. The driver includes thermal shutdown circuitry to protect against damage from high junction temperatures and clamp diodes for inductive load transient suppression. T C U Y D L O N R O P E D C E N U E N ER I T N EF O R C R S I O D F — The CMOS inputs cause minimal circuit loading and are compatible with standard CMOS, PMOS, and NMOS circuits. TTL or DTL circuits may require the use of appropriate pull up resistors. When reading back, each data input will sink 8 mA (if its corresponding latch is low) or source 400 µA (if its corresponding latch is high). The read back feature is for error checking. It allows the system to verify that data has been received and latched. Dwg. No. A-14,225 The bipolar outputs are suitable for use with low-power relays, solenoids, and stepping motors. The very-low output saturation voltage makes this device well-suited for driving LED arrays. The output transistors are capable of sinking 50 mA and will maintain at least 20 V in the OFF state. Outputs may be paralleled for higher current capability. The UCN5881EP dual 8-bit latched sink driver is rated for operation over the temperature range of -20°C to +85°C and is supplied in a plastic 44-lead chip carrier conforming to the JEDEC MS-007AB outline. FEATURES ABSOLUTE MAXIMUM RATINGS Output Voltage, VOUT . . . . . . . . . . . . . . 20 V Output Sustaining Voltage, VCE(sus) . . . 15 V Output Current, IOUT . . . . . . . . . . . . 50 mA Input Voltage Range, VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V Logic Supply Voltage, VDD . . . . . . . . . . 15 V Package Power Dissipation, PD . . . . . . . . . . . . . . . . . . . See Graph Operating Temperature Range, TA . . . . . . . . . . . . . . . . -20 °C to +85°C Storage Temperature Range, TS . . . . . . . . . . . . . . . -55°C to +150°C ■ ■ ■ ■ ■ ■ 4.4 MHz Minimum Data-Input Rate Low-Power CMOS Logic 20 V, 50 mA (Max.) Outputs Transient-Protected Outputs Thermal Shutdown Protection Low-Profile Leaded Chip Carrier Caution: CMOS devices have input static protection, but are susceptible to damage when exposed to extremely high static electrical charges. Always order by complete part number: UCN5881EP . 5881 BiMOS II DUAL 8-BIT LATCHED DRIVER FUNCTIONAL BLOCK DIAGRAM (1 of 16 Channels) Dwg. No. A-14,227 TRUTH TABLE ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS 3.0 Read/ln Strobe Clear X 0 1 X X n 2.5 2.0 1.5 X 1 1 0 X X X 0 0 0 1 0 Output Enable 1 0 0 0 X X Latch Read/Write Contents X 1 1 1 X 0 n = Present Latch Contents n-1 = Previous Latch Contents X = Irrelevant RθJA = 46°C/W 1.0 0.5 0 25 50 75 100 125 AMBIENT TEMPERATURE IN °C 150 Dwg. GP-025-1A 115 Northeast Cutoff, Box 15036 W Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1985, 1995, Allegro MicroSystems, Inc. X 0 1 n-1 0 n Output OFF OFF ON n-1 OFF n 5881 BiMOS II DUAL 8-BIT LATCHED DRIVER ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 5 V (unless otherwise noted). Characteristic Symbol Output Leakage Current Output Saturation Voltage Output Sustaining Voltage Input Voltage Input Current Readback Output Voltage Logic Supply Current Test Conditions Min. Limits Max. Units ICEX VOUT = 20 V — 50 µA VCE(SAT) IOUT = 10 mA — 0.1 V IOUT = 25 mA — 0.5 V IOUT = 25 mA, L = 2 mH 15 — V VIN(0) -0.3 0.8 V VIN(1) 3.5 5.3 V VCE(sus) IIN(0) VIN = 0.8 V — -10 µA IIN(1) VIN = 5 V — 10 µA VOUT(1) IOUT = -400 µA 3.5 — V VOUT(0) IOUT = 5.0 mA — 0.8 V lDD All Drivers ON — 14 mA All Drivers OFF — 3.0 mA Clamp Diode Leakage Current IR VR = 20 V — 50 µA Clamp Diode Forward Voltage VF IF = 50 mA — 1.5 V Dwg. No. A-14,228 TIMING CONDITIONS (VDD = 5.0 V, Logic Levels are VDD and Ground) A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns B. Minimum Data Active Time After Strobe Disabled (Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ns C. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 ns D. Typical Time Between Strobe Activation and Output ON to OFF Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 µs E. Typical Time Between Strobe Activation and Output OFF to ON Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns F. Minimum Clear Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns G. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ns A high on the READ/WRITE input allows the circuit to accept data in. Information then present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. A low on the READ/WRITE input will allow the latched data to be read back on the data input lines. Allow a minimum of 750 ns delay (will increase with capacitive loading) before reading back the state of the latches. The read back feature is for error checking applications and allows the system to verify that data has been received and latched. 5881 BiMOS II DUAL 8-BIT LATCHED DRIVER Dimensions in Inches (controlling dimensions) 18 28 29 17 0.032 0.026 0.319 0.291 0.695 0.685 0.021 0.013 0.656 0.650 0.319 0.291 0.050 INDEX AREA BSC 39 7 40 0.020 44 1 2 6 0.656 0.650 MIN 0.695 0.685 0.180 0.165 Dwg. MA-005-44A in Dimensions in Millimeters (for reference only) 18 28 29 17 0.812 0.661 8.10 7.39 17.65 17.40 0.533 0.331 16.662 16.510 8.10 7.39 INDEX AREA 1.27 BSC 7 39 40 0.51 MIN 4.57 4.20 44 1 2 6 16.662 16.510 17.65 17.40 Dwg. MA-005-44A mm NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000