ALSC AS7C3513-20TC

March 2001
AS7C513
AS7C3513
®
5V/3.3V 32K×16 CMOS SRAM
Features
• AS7C513 (5V version)
• AS7C3513 (3.3V version)
• Industrial and commercial temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins
• High speed
- 12/15/20 ns address access time
- 6,7,8 ns output enable access time
• Low power consumption: ACTIVE
- 800 mW (AS7C513) / max @ 12 ns
- 432 mW (AS7C3513) / max @ 12 ns
• Low power consumption: STANDBY
- 28 mW (AS7C513) / max CMOS
- 18 mW (AS7C3513) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
- 400 mil SOJ
- 400 mil TSOP II
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
A0
A3
A4
A5
A6
32K × 16
Array
GND
NC
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A14
A13
A12
A11
NC
A7
I/O
buffer
A14
A13
A12
A11
A9
Column decoder
A8
WE
Control circuit
A10
I/O0–I/O7
I/O8–I/O15
UB
OE
LB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AS7C513
AS7C3513
A2
44-Pin SOJ, TSOP II (400 mil)
VCC
Row decoder
A1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A5
A6
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A7
A8
A9
A10
NC
CE
Selection guide
AS7C513-12
AS7C3513-12
AS7C513-15
AS7C3513-15
AS7C513-20
AS7C3513-20
Unit
Maximum address access time
12
15
20
ns
Maximum output enable access time
5
7
9
ns
AS7C513
160
150
140
mA
AS7C3513
120
110
100
mA
AS7C513
5
5
5
mA
AS7C3513
5
5
5
mA
Maximum operating current
Maximum CMOS standby current
Shaded areas indicate advance information.
3/23/01; v.1.0
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C513
AS7C3513
®
Functional description
The AS7C513 and the AS7C3513 are high performance CMOS 524,288-bit Static Random Access Memory (SRAM) devices organized as
32,768 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal for high
performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high, the devices enter standby mode. The AS7C513 and AS7C3513 are guaranteed not to exceed 28/18 mW power
consumption in CMOS standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0-I/O7,
and/or I/O8–I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible. The AS7C513 and AS7C3513 are packaged in common industry standard packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
Max
Unit
AS7C513
Vt1
–0.50
+7.0
V
AS7C3513
Vt1
–0.50
+5.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.0
W
Storage temperature (plastic)
Tstg
–65
+150
o
C
C
Voltage on VCC relative to GND
Ambient temperature with VCC applied
Tbias
–55
+125
o
DC current into outputs (low)
IOUT
–
50
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
UB
I/O0–I/O7
I/O8–I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (ISB, ISBI)
L
H
L
L
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
H
L
H
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
H
L
L
L
DOUT
DOUT
Read I/O0–I/O15 (ICC)
L
L
X
L
L
DIN
DIN
Write I/O0–I/O15 (ICC)
L
L
X
L
H
DIN
High Z
Write I/O0–I/O7 (ICC)
L
L
X
H
L
High Z
DIN
Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (ICC)
Key: X = Don’t care; L = Low; H = High
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AS7C513
AS7C3513
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
†
Device
Symbol
Min
Typical
Max
Unit
AS7C513
VCC
4.5
5.0
5.5
V
AS7C3513
VCC
3.0
3.3
3.6
V
AS7C513
VIH
2.2
–
VCC + 0.5
V
AS7C3513
VIH
2.0
–
VCC + 0.5
–
0.8
V
†
VIL
–0.5
commercial
TA
0
–
70
°C
industrial
TA
–40
–
05
°C
VIL min = –3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
-12
Parameter
Symbol
Test conditions
Device
-15
-20
Min Max Min Max Min Max Unit
Input leakage current
| ILI |
VCC = Max
VIN = GND to VCC
–
1
–
1
–
1
µA
Output leakage current
| ILO |
VCC = Max
VOUT = GND to VCC
–
1
–
1
–
1
µA
AS7C513
–
160
–
150
–
140
AS7C3513
–
120
–
110
–
100
AS7C513
–
40
–
40
–
40
AS7C3513
–
40
–
40
–
40
AS7C513
–
3
–
3
–
3
AS7C3513
–
3
–
3
–
3
–
0.4
–
0.4
–
0.4
V
2.4
–
2.4
–
2.4
–
V
Operating power supply
ICC
current
VCC = Max, CE ≤ VIL
f = fMax , IOUT = 0mA
ISB
VCC = Max, CE ≤ VIL
f = fMax , IOUT = 0mA
ISB1
VCC = Max, CE ≥ VCC–0.2V
VIN ≤ GND + 0.2V or
VIN ≥ VCC –0.2V, f = 0
VOL
IOL = 8 mA, VCC = Min
Standby power supply
current
Output voltage
VOH
Shaded areas indicate advance information.
IOH = –4 mA, VCC = Min
mA
mA
mA
Capacitance (f = 1MHz, Ta = 25o C, VCC = NOMINAL)2
Parameter
Symbol
Signals
Test conditions
Max Unit
Input capacitance
CIN
A, CE, WE, OE, LB, UB
Vin = 0V
5
pF
I/O capacitance
CI/O
I/O
Vin = Vout = 0V
7
pF
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AS7C513
AS7C3513
®
Read cycle (over the operating range) 3,9
-12
-15
-20
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
tRC
12
–
15
–
20
–
ns
Address access time
tAA
–
12
–
15
–
20
ns
3
Chip enable (CE) access time
tACE
–
12
–
15
–
20
ns
3
Output enable (OE) access time
tOE
–
6
–
7
–
8
ns
Output hold from address change
tOH
3
–
4
–
4
–
ns
5
CE Low to output in low Z
tCLZ
0
–
0
–
0
–
ns
4, 5
CE High to output in high Z
tCHZ
–
6
–
7
–
8
ns
4, 5
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
ns
4, 5
Byte select access time
tBA
–
6
–
7
–
8
ns
Byte select Low to low Z
tBLZ
0
–
0
–
0
–
ns
4,5
Byte select High to high Z
tBHZ
–
6
–
7
–
9
ns
4,5
OE High to output in high Z
tOHZ
–
6
–
7
–
9
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
ns
4, 5
Power down time
tPD
–
12
–
15
–
20
ns
4, 5
Shaded areas indicate advance information.
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
tOH
Data OUT
tOH
Previous data valid
Data valid
Read waveform 2 (CE, OE, UB, LB controlled)3,6,8,9
tRC
Address
tAA
OE
tOE
tOH
tOLZ
CE
tOHZ
tACE
tLZ
tHZ
LB, UB
tBA
tBHZ
tBLZ
Data OUT
3/23/01; v.1.0
Data valid
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AS7C513
AS7C3513
®
Write cycle (over the operating range)11
-12
-15
-20
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
9
–
10
–
12
–
ns
Address setup to write end
tAW
8
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
ns
Write pulse width
tWP
8
–
10
–
12
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
ns
Data valid to write end
tDW
6
–
8
–
10
–
ns
Data hold time
tDH
0
–
0
–
0
–
ns
5
Write enable to output in high Z
tWZ
–
6
–
7
–
9
ns
4, 5
Output active from write end
tOW
3
–
3
–
3
–
ns
4, 5
Byte select Low to end of write
tBW
8
–
9
–
12
–
ns
Shaded areas indicate advance information.
Write waveform 1(WE controlled)10,11
tWC
Address
tBW
LB, UB
tAW
tAS
tWP
WE
tDW
tDH
Data valid
Data IN
tWZ
Data OUT
tOW
Data undefined
High-Z
Write waveform 2 (CE controlled)10,11
tWC
Address
tAS
tAH
tCW
CE
tAW
tBW
LB, UB
tWP
WE
tDH
tDW
Data valid
Data IN
tCLZ
Data OUT
3/23/01; v.1.0
High-Z
tWZ
Data undefined
Alliance Semiconductor
tOW
High-Z
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AS7C513
AS7C3513
®
Data retention characteristics (over the operating range)13
Parameter
Symbol
VCC for data retention
VDR
Data retention current
ICCDR
Chip deselect to data retention time
tCDR
Operation recovery time
tR
Input leakage current
| ILI |
Test conditions
VCC = 2.0V
CE ≥ VCC–0.2V
VIN ≥ VCC–0.2V or
VIN ≤ 0.2V
Min
Max
Unit
2.0
–
V
–
500
µA
0
–
ns
tRC
–
ns
–
1
µA
Data retention waveform
Data retention mode
VCC
VDR ≥ 2.0V
VCC
VCC
tCDR
tR
VDR
VIH
CE
VIH
AC test conditions
-
Output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168Ω
Dout
+1.728V (5V and 3.3V)
+5V
+3.3V
480Ω
+3.0V
GND
90%
10%
90%
2 ns
10%
Figure A: Input pulse
Dout
255Ω
C(14)
GND
Figure B: 5V Output load
320Ω
Dout
350Ω
C(14)
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
2V data retention applies to the commercial operating range only.
C=30pF, except on High Z and Low Z parameters, where C=5pF.
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AS7C513
AS7C3513
®
Typical DC and AC characteristics
1.4
1.0
0.8
0.6
ISB
0.4
0.2
0.6
ISB
0.4
0.0
–55
MAX
Normalized access time
Ta = 25°C
1.3
1.2
1.1
1.0
0.9
0.8
MIN
NOMINAL
Supply voltage (V)
Output source current IOH
vs. output voltage VOH
140
Output sink current (mA)
VCC = VCC(NOMINAL)PL
100
Ta = 25°C
80
60
40
20
0
VCC
Output voltage (V)
3/23/01; v.1.0
0.2
-10
35
80
125
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.2
1.3
1.2
1.1
1.0
0.9
VCC = VCC(NOMINAL)
Ta = 25°C
1.0
0.8
0.6
0.4
0.2
0.0
–10
35
80
125
Ambient temperature (°C)
0
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
Output sink current IOL
vs. output voltage VOL
35
120
30
VCC = VCC(NOMINAL)
100
Ta = 25°C
80
60
40
20
VCC = VCC(NOMINAL)
25
20
15
10
5
0
0
1
1.4
VCC = VCC(NOMINAL)
140
120
5
-55
1.4
0.8
–55
MAX
VCC = VCC(NOMINAL)
25
–10
35
80
125
Ambient temperature (°C)
Normalized access time tAA
vs. ambient temperature Ta
1.5
1.4
625
0.04
Normalized ICC
NOMINAL
Supply voltage (V)
Normalized access time tAA
vs. supply voltage VCC
1.5
Normalized access time
0.8
0.2
0.0
MIN
Output source current (mA)
ICC
1.0
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.2
ICC
Normalized ICC, ISB
Normalized ICC, ISB
1.2
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Change in tAA (ns)
1.4
Normalized supply current ICC, ISB
vs. supply voltage VCC
0
0
VCC
Output voltage (V)
Alliance Semiconductor
0
250
500
750
Capacitance (pF)
1000
P. 7 of 10
AS7C513
AS7C3513
®
Package dimensions
44-pin TSOP II
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Min (mm)
Max (mm)
A
e He
44-pin TSOP II
1.2
A1
0.05
A2
0.95
1.05
b
0.25
0.45
c
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
d
l
A2
A
d
18.28
18.54
e
10.06
10.26
He
11.56
11.96
E
0–5°
A1
0.15 (typical)
0.80 (typical)
l
0.40
0.60
E
b
e
44-pin SOJ
Pin 1
A
A1
A2
B
b
c
D
E
E1
E2
e
E1 E2
B
c
A
A1
b
44-pin SOJ
400 mil
Min
Max
0.128
0.148
0.025
1.105
1.115
0.026
0.032
0.015
0.020
0.007
0.013
1.120
1.130
0.370 NOM
0.395
0.405
0.435
0.445
0.050 NOM
D
A2
E2
Seating
Plane
Ordering codes
Package\Access time
Plastic SOJ, 400 mil
TSOP II, 18.4×10.2 mm
Volt/Temp
12 ns
15 ns
20 ns
5V commercial
AS7C513-12JC
AS7C513-15JC
AS7C513-20JC
3.3V commercial
AS7C3513-12JC
AS7C3513-15JC
AS7C3513-20JC
5V commercial
AS7C513-12TC
AS7C513-15TC
AS7C513-20TC
3.3V commercial
AS7C3513-12TC
AS7C3513-15TC
AS7C3513-20TC
NA: not available.
Part numbering system
AS7C
X
Voltage:Blank = 5V CMOS
SRAM prefix
3 = 3.3V CMOS
3/23/01; v.1.0
513
–XX
Device number Access time
X
Package: J = SOJ 400 mil
T = TSOP II,
18.4×10.2 mm
Alliance Semiconductor
C
Commercial temperature
range: 0 oC to 70 0C
Industrial temperature
range: -40C to 85C
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AS7C513
AS7C3513
®
3/23/01; v.1.0
Alliance Semiconductor
P. 9 of 10
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may
be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If
the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use
of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
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intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected
to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against
all claims arising from such use
AS7C513
AS7C3513
®
3/23/01; v.1.0
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