January 2001 Advance Information AS7C256 AS7C3256 ® 5V/3.3V 32K X 8 CMOS SRAM (Common I/O) Features - 7.2 mW (AS7C3256) / max CMOS I/O • AS7C256 (5V version) • AS7C3256 (3.3V version) • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • High speed • 2.0V data retention • Easy memory expansion with CE and OE inputs • TTL-compatible, three-state I/O • 28-pin JEDEC standard packages - 300 mil PDIP - 300 mil SOJ - 8 × 13.4 TSOP - 12/15/20 ns address access time - 5/6/7/9 ns output enable access time • Very low power consumption: ACTIVE • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA - 660mW (AS7C256) / max @ 12 ns - 216mW (AS7C3256) / max @ 12 ns • Very low power consumption: STANDBY - 22 mW (AS7C256) / max CMOS I/O Logic block diagram Pin arrangement 28-pin TSOP I (8×13.4) VCC 28-pin DIP, SOJ (300 mil) Input buffer I/O7 Row decoder 256 X 128 X 8 Sense amp A0 A1 A2 A3 A4 A5 A6 A14 Array (262,144) I/O0 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (22) (23) (24) (25) (26) (27) (28) AS7C256 (1) AS7C3256 (2) (3) (4) (5) (6) (7) (21) 28 (20) 27 (19) 26 (18) 25 (17) 24 (16) 23 (15) 22 (14) 21 (13) 20 (12) 19 (11) 18 (10) 17 (9) 16 (8) 15 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 Note: This part is compatible with both pin numbering conventions used by various manufacturers. WE Column decoder Control circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AS7C256 AS7C3256 GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OE CE A 7 A 8 A A A A A 9 10 11 12 13 Selection guide AS7C256-10 AS7C3256-10 AS7C256-12 AS7C3256-12 AS7C256-15 AS7C3256-15 AS7C256-20 AS7C3256-20 Unit 10 12 15 20 ns 5 6 7 ns AS7C256 120 115 110 mA AS7C3256 60 55 50 mA AS7C256 4 4 4 mA AS7C3256 2 2 2 mA Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current 1/10/2001 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 AS7C256 AS7C3256 ® Functional description The AS7C(3)256 is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes ≤3.6 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of the AS7C256 offer 2.0V data retention. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 5/6/7/9 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C(3)256A is packaged in high volume industry standard packages. Absolute maximum ratings Parameter Device Symbol Min Max Unit AS7C256 Vt1 –0.5 +7.0 V AS7C3256 Vt1 –0.5 +5.0 V Voltage on any pin relative to GND Vt2 –0.5 VCC + 0.5 V Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 o C C Voltage on VCC relative to GND Ambient temperature with VCC applied Tbias –55 +125 o DC current into outputs (low) IOUT – 20 mA Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (ISB, ISB1) L H H High Z Output disable (ICC) L H L DOUT Read (ICC) L L X DIN Write (ICC) Key: X = Don’t care, L = Low, H = High 1/10/2001 Alliance Semiconductor P. 2 of 9 AS7C256 AS7C3256 ® Recommended operating conditions Parameter Device Supply voltage Input voltage Symbol Min Typical Max Unit AS7C256 VCC 4.5 5.0 5.5 V AS7C3256 VCC 3.0 3.3 3.6 V AS7C256 VIH 2.2 – VCC+0.5 V AS7C3256 VIH 2.0 – VCC+0.5 V – 0.8 V — Ambient operating temperature * VIL * * -0.5 commercial TA industrial TA 0 – 70 oC –40 – 85 o C VIL min = –2.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range)1 -10 Parameter Sym Test conditions Input leakage current |ILI| Device Min Max VCC = Max, Vin = GND to VCC Output leakage V = Max, |ILO| CC current VOUT = GND to VCC Operating power supply current Standby power supply current Output voltage -12 -15 -20 Min Max Min Max Min Max Unit – 1 – 1 – 1 µA – 1 – 1 – 1 µA VCC = Max, CE ≤ VIL f = fMax, IOUT = 0mA AS7C256 – 120 – 115 – 110 ICC AS7C3256 – 60 – 55 – 50 ISB VCC = Max, CE ≤ VIL f = fMax, IOUT = 0mA AS7C256 – 40 – 35 – 30 AS7C3256 – 20 – 20 – 20 VCC = Max, CE > VCC–0.2V AS7C256 ISB1 VIN < GND + 0.2V or AS7C3256 VIN > VCC–0.2V, f = 0 – 4.0 – 4.0 – 4.0 – 2.0 – 2.0 – 2.0 VOL IOL = 8 mA, VCC = Min – 0.4 – 0.4 – 0.4 V 2.4 – 2.4 – 2.4 – V VOH IOH = –4 mA, VCC = Min mA mA mA Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE, WE, OE Vin = 0V 5 pF I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF 1/10/2001 Alliance Semiconductor P. 3 of 9 AS7C256 AS7C3256 ® Read cycle (over the operating range)3,9 -10 Parameter Symbol Read cycle time Min -12 Max -15 -20 Min Max Min Max Min Max Unit Notes tRC 12 – 15 – 20 – ns Address access time tAA – 12 – 15 – 20 ns 3 Chip enable (CE) access time tACE – 12 – 15 – 20 ns 3 Output enable (OE) access time tOE – 5 – 6 – 7 ns Output hold from address change tOH 3 – 3 – 3 – ns 5 CE LOW to output in low Z tCLZ 3 – 3 – 3 – ns 4, 5 CE HIGH to output in high Z tCHZ – 3 – 4 – 5 ns 4, 5 OE LOW to output in low Z tOLZ 0 – 0 – 0 – ns 4, 5 OE HIGH to output in high Z tOHZ – 3 – 4 – 5 ns 4, 5 Power up time tPU 0 – 0 – 0 – ns 4, 5 Power down time tPD – 12 – 15 – 20 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined output/don’t care Read waveform 1 (address controlled)3,6,7,9 tRC Address tAA tOH Dout Data valid Read waveform 2 (CE controlled)3,6,8,9 tRC1 CE tOE OE tOLZ tOHZ tCHZ tACE Dout Data valid tCLZ Supply current 1/10/2001 tPU tPD 50% 50% Alliance Semiconductor ICC ISB P. 4 of 9 AS7C256 AS7C3256 ® Write cycle (over the operating range)11 -10 -12 -15 -20 Parameter Symbol Min Max Min Max Min Max Unit Notes Write cycle time tWC 12 – 15 – 20 – ns Chip enable to write end tCW 8 – 10 – 12 – ns Address setup to write end tAW 8 – 10 – 12 – ns Address setup time tAS 0 – 0 – 0 – ns Write pulse width tWP 8 – 9 – 12 – ns Address hold from end of write tAH 0 – 0 – 0 – ns Data valid to write end tDW 6 – 8 – 10 – ns Data hold time tDH 0 – 0 – 0 – ns 4, 5 Write enable to output in high Z tWZ – 5 – 5 – 5 ns 4, 5 Output active from write end tOW 3 – 3 – 3 – ns 4, 5 Shaded areas contain advance information. Write waveform 1 (WE controlled)10,11 tWC tAW tAH Address tWP WE tAS tDW Din tDH Data valid tWZ tOW Dout Write waveform 2 (CE controlled)10,11 tWC tAW tAH Address tAS tCW CE tWP WE tWZ Din tDW tDH Data valid Dout 1/10/2001 Alliance Semiconductor P. 5 of 9 AS7C256 AS7C3256 ® Data retention characteristics (over the operating range)13 Parameter Symbol VCC for data retention VDR Data retention current ICCDR Test conditions VCC = 2.0V CE ≥ VCC–0.2V VIN ≥ VCC–0.2V or VIN ≤ 0.2V Chip enable to data retention time tCDR Operation recovery time tR Input leakage current | ILI | Min Max Unit 2.0 – V – 500 µA – – µA 0 – ns tRC – ns – 1 µA Data retention waveform Data retention mode VCC VCC VDR ≥ 2.0V VCC tCDR CE tR VDR VIH VIH AC test conditions - Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent 168Ω Dout +1.72V (5V and 3.3V) +3.3V +5V 320Ω 480Ω +3.0V GND 90% 10% 90% 2 ns Figure A: Input pulse 10% Dout 255Ω C(14) GND Figure B: Output load Dout 350Ω C(14) GND Figure C: Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, C. These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is High for read cycle. CE and OE are Low for read cycle. Address valid prior to or coincident with CE transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. 2V data retention applies to the commercial operating range only. C=30pF, except on High Z and Low Z parameters, where C=5pF. 1/10/2001 Alliance Semiconductor P. 6 of 9 AS7C256 AS7C3256 ® Typical DC and AC characteristics 1.4 1.0 0.8 0.6 ISB 0.4 0.2 0.6 ISB 0.4 0.0 –55 MAX Normalized access time Ta = 25°C 1.3 1.2 1.1 1.0 0.9 0.8 MIN NOMINAL Supply voltage (V) Output source current IOH vs. output voltage VOH 140 Output sink current (mA) VCC = VCC(NOMINAL)PL 100 Ta = 25°C 80 60 40 20 0 VCC Output voltage (V) 1/10/2001 0.2 -10 35 80 125 Ambient temperature (°C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.2 1.3 1.2 1.1 1.0 0.9 VCC = VCC(NOMINAL) Ta = 25°C 1.0 0.8 0.6 0.4 0.2 0.0 –10 35 80 125 Ambient temperature (°C) 0 25 50 75 Cycle frequency (MHz) 100 Typical access time change ∆tAA vs. output capacitive loading Output sink current IOL vs. output voltage VOL 35 120 30 VCC = VCC(NOMINAL) 100 Ta = 25°C 80 60 40 20 VCC = VCC(NOMINAL) 25 20 15 10 5 0 0 1 1.4 VCC = VCC(NOMINAL) 140 120 5 -55 1.4 0.8 –55 MAX VCC = VCC(NOMINAL) 25 –10 35 80 125 Ambient temperature (°C) Normalized access time tAA vs. ambient temperature Ta 1.5 1.4 625 0.04 Normalized ICC NOMINAL Supply voltage (V) Normalized access time tAA vs. supply voltage VCC 1.5 Normalized access time 0.8 0.2 0.0 MIN Output source current (mA) ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta Change in tAA (ns) 1.4 Normalized supply current ICC, ISB vs. supply voltage VCC 0 0 VCC Output voltage (V) Alliance Semiconductor 0 250 500 750 Capacitance (pF) 1000 P. 7 of 9 AS7C256 AS7C3256 ® Package diagrams A D B S E1 E α L e A1 b c eA Seating Plane Pin 1 D e A A1 Seating Plane b Pin 1 c A2 E e c A2 L D Hd pin 1(22) - 0.140 0.025 - 0.095 0.105 0.028 TYP 0.018 TYP 0.010 TYP - 0.730 0.245 0.285 0.295 0.305 0.327 0.347 0.050 BSC A1 pin 8(21) pin 1(7) pin 5(8) 28-pin 1/10/2001 A A A1 A2 B b c D E E1 E2 e 28-pin 8×13.4 Min Max α E 28-pin SOJ Min Max B E1 E2 b A A1 B b c D E E1 e eA L α S 28-pin PDIP Min Max 0.175 0.010 0.058 0.064 0.016 0.022 0.008 0.014 1.400 0.295 0.320 0.278 0.298 0.100 BSC 0.330 0.370 0.120 0.140 0° 15° 0.055 Note: This part is compatible with both pin numbering conventions used by various manufacturers. Alliance Semiconductor A A1 – 1.20 0.10 0.20 A2 0.95 1.05 b c D e 0.15 0.25 0.10 0.20 11.60 11.80 0.55 nominal P. 8 of 9 AS7C256 AS7C3256 ® Ordering information Package / Access time Plastic DIP, 300 mil Plastic SOJ, 300 mil TSOP 8x13.4 Volt/Temp 10 ns 12 ns 15 ns 20 ns 5V commercial AS7C256-10PC AS7C256-12PC AS7C256-15PC AS7C256-20PC 3.3V commercial AS7C3256-10PC AS7C3256-12PC AS7C3256-15PC AS7C3256-20PC 5V commercial AS7C256-10JC AS7C256-12JC AS7C256-15JC AS7C256-20JC 3.3V commercial AS7C3256-10JC AS7C3256-12JC AS7C3256-15JC AS7C3256-20JC 5V industrial AS7C256-10JI AS7C256-12JI AS7C256-15JI AS7C256-20JI 3.3V industrial AS7C3256-10JI AS7C3256-12JI AS7C3256-15JI AS7C3256-20JI 5V commercial AS7C256-10TC AS7C256-12TC AS7C256-15TC AS7C256-20TC 3.3V commercial AS7C3256-10TC AS7C3256-12TC AS7C3256-15TC AS7C3256-20TC 5V industrial AS7C256-10TI AS7C256-12TI AS7C256-15TI AS7C256-20TI 3.3V industrial AS7C3256-10TI AS7C3256-12TI AS7C3256-15TI AS7C3256-20TI Part numbering system AS7C SRAM prefix 3 256 –XX 3 = 3.3V supply Device number Access time X Package: J T = SOJ 300 mil = TSOP 8x13.4 C or I Commercial temperature range: 0 oC to 70 0C Industrial temperature range: -40C to 85C 1/10/2001 Alliance Semiconductor P. 9 of 9 © Copyright Alliance Semiconductor Corporation. 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