ETC AS7C34096

March 2001
AS7C4096
AS7C34096
®
5V/3.3V 512K × 8 CMOS SRAM
Features
• AS7C4096 (5V version)
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• 2.0V data retention
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 400 mil 36-pin SOJ
- 400 mil 44-pin TSOP II
- 1375 mW (AS7C4096) / max @ 12 ns
- 468 mW (AS7C34096) / max @ 12 ns
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
36-pin SOJ (400 mil)
44-pin TSOPII(400 mil)
VCC
GND
Input buffer
524,288 × 8
Array
(4,194,304)
Sense amp
I/O1
Row decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O8
WE
OE
CE
Control
Circuit
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
Column decoder
A0
A1
A2
A3
A4
CE
/O1
/O2
VCC
GND
/O3
/O4
WE
A5
A6
A7
A8
A9
NC
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
Selection guide
Maximum address
access time
Maximum output
enable access time
Maximum operating
current
Maximum CMOS standby
current
3/23/01; v.1.1
AS7C4096
AS7C34096
AS7C4096
AS7C34096
AS7C34096
–10
AS7C4096
AS7C34096
–12
AS7C4096
AS7C34096
–15
AS7C4096
AS7C34096
–20
Unit
10
12
15
20
ns
5
6
7
9
ns
–
160
–
20
250
130
20
20
220
110
20
20
180
100
20
20
mA
mA
mA
mA
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4096
AS7C34096
®
Functional description
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory
systems.
When CE is high the device enters standby mode. The AS7C4096 is guaranteed not to exceed 110 mW power consumption in
CMOS standby mode. Both devices offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written
on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins
only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single supply voltage. Both devices are available in the
industry standard 400-mil 36-pin SOJ and 44-pin TSOP II packages.
Absolute maximum ratings
Parameter
Voltage on VCC relative to GND
Device
AS7C4096
AS7C34096
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with VCC applied
DC current unto output (low)
Symbol
Vt1
Vt1
Vt2
PD
Tstg
Tbias
IOUT
Min
–1
–0.5
–0.5
–
–65
–55
–
Max
+7.0
+5.0
VCC +0.5
1.0
+150
+125
20
Unit
V
V
V
W
°C
°C
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
DOUT
DIN
Mode
Standby (ISB, ISB1)
Output disable (ICC)
Read (ICC)
Write (ICC)
Key: X = Don’t care, L = Low, H = High
3/23/01; v.1.1
Alliance Semiconductor
P. 2 of 10
AS7C4096
AS7C34096
®
Recommended operating condition
Parameter
Device
AS7C4096
AS7C34096
AS7C34096
AS7C4096
AS7C34096
Supply voltage
Input voltage
Ambient operating
temperature
†
commercial
industrial
Symbol
VCC(12/15/20)
VCC (–10)
VCC(12/15/20)
VIH
VIH
VIL
TA
TA
Min
4.5
3.15
3.0
2.2
2.0
–0.5†
0
–40
Nominal
5.0
3.30
3.3
–
–
–
–
–
Max
5.5
3.6
3.6
VCC + 0.5
VCC + 0.5
0.8
70
85
Unit
V
V
V
V
V
V
°C
°C
VIL min = –3.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
Parameter Symbol
Input leakage
|ILI|
current
Output
leakage
|ILO|
current
Operating
power supply
ICC
current
Standby
power supply
current
Output
voltage
Test conditions
VCC = Max, VIN = GND to VCC
–
1
–
1
–
1
–
1
µA
VCC = Max, CE = VIH
VOUT= GND to VCC
–
1
–
1
–
1
–
1
µA
AS7C4096
–
–
–
250
–
220
–
180 mA
AS7C34096
–
160
–
130
–
110
–
100
AS7C4096
AS7C34096
AS7C4096
–
–
–
–
60
–
–
–
–
60
60
20
–
–
–
60
60
20
–
–
–
60
60
20
20
–
20
–
20
–
20
VCC = Max, CE < VIL
f = fMax, IOUT = 0mA
VCC = Max, CE = VIH
f = fMax, IOUT = 0mA
ISB
ISB1
VOL
VOH
Device
–10
–12
–15
–20
Min Max Min Max Min Max Min Max Unit
VCC = Max,
CE ≥ VCC – 0.2V, VIN ≤ 0.2V or VIN ≥
AS7C34096 –
VCC – 0.2V, f = 0
IOL = 8 mA, VCC = Min
–
IOH = –4 mA, VCC = Min
2.4
0.4 – 0.4 –
– 2.4 – 2.4
mA
mA
0.4 – 0.4
– 2.4 –
Capacitance (f = 1MHz, Ta = 25° C, VCC = NOMINAL)2
Parameter
Input capacitance
I/O capacitance
3/23/01; v.1.1
Symbol
CIN
CI/O
Signals
A, CE, WE, OE
I/O
Alliance Semiconductor
Test conditions
VIN = 0V
VIN = VOUT = 0V
Max
5
7
Unit
pF
pF
P. 3 of 10
V
V
AS7C4096
AS7C34096
®
Read cycle (over the operating range)3,9
–10
Parameter
Symbol
Read cycle time
tRC
Address access time
tAA
tACE
Chip enable (CE) access time
Output enable (OE) access time
tOE
Output hold from address change tOH
tCLZ
CE Low to output in low Z
CE High to output in high Z
tCHZ
OE Low to output in low Z
tOLZ
OE High to output in high Z
tOHZ
Power up time
tPU
Power down time
tPD
Min
10
–
–
–
3
3
–
0
–
0
–
–12
Max
–
10
10
5
–
–
5
–
5
–
10
Min
12
–
–
–
3
3
–
0
–
0
–
–15
Max
–
12
12
6
–
–
6
–
6
–
12
Min
15
–
–
–
3
0
–
0
–
0
–
–20
Max
–
15
15
7
–
–
7
–
7
–
15
Min
20
–
–
–
3
0
–
0
–
0
–
Max
–
20
20
8
–
–
9
–
9
–
20
Unit Notes
ns
ns
3
ns
3
ns
ns
5
ns
4, 5
ns
4, 5
ns
4, 5
ns
4, 5
ns
4, 5
ns
4, 5
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE, OE controlled)3,6,8,9
tRC1
CE
tOE
OE
tOLZ
tOHZ
tACE
tCHZ
DOUT
Data valid
tCLZ
Supply
current
tPU
tPD
50%
ICC
ISB
50%
Write cycle (over the operating range)11
–10
Parameter
Write cycle time
Chip enable (CE) to write end
3/23/01; v.1.1
Symbol
tWC
tCW
Min
10
7
–12
Max
–
–
Min
12
8
–15
Max
–
–
Alliance Semiconductor
Min
15
10
–20
Max
–
–
Min
20
12
Max
–
–
Unit Notes
ns
ns
P. 4 of 10
AS7C4096
AS7C34096
®
–10
Parameter
Symbol
Address setup to write end
tAW
Address setup time
tAS
Write pulse width (OE = high)
tWP1
tWP2
Write pulse width (OE = low
Address hold from end of write
tAH
Data valid to write end
tDW
Data hold time
tDH
Write enable to output in high Z
tWZ
Output active from write end
tOW
Min
7
0
7
10
0
5
0
0
3
–12
Max
–
–
–
–
–
–
–
5
–
Min
8
0
8
12
0
6
0
0
3
–15
Max
–
–
–
–
–
–
–
6
–
Min
10
0
10
15
0
7
0
0
3
–20
Max
–
–
–
–
–
–
–
7
–
Min
12
0
12
20
0
9
0
0
3
Max
–
–
–
–
–
–
–
9
–
Unit Notes
ns
ns
ns
ns
ns
ns
ns
4, 5
ns
4, 5
ns
4, 5
Write waveform 1 (WE controlled)10,11
tWC
tAW
tAH
Address
tWP
WE
tAS
tDW
DIN
tDH
Data valid
tWZ
tOW
DOUT
Write waveform 2 (CE controlled)10,11
tAW
tWC
tAH
Address
tAS
tCW
CE
tWP
WE
tWZ
tDW
DIN
tDH
Data valid
DOUT
Data retention characteristics (over the operating range)13
Parameter
VCC for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
3/23/01; v.1.1
Symbol
VDR
ICCDR
tCDR
tR
|ILI|
Test conditions
VCC = 2.0V
CE ≥ VCC – 0.2V
VIN ≥ VCC – 0.2V or
VIN ≤ 0.2V
Alliance Semiconductor
Min
2.0
–
0
tRC
–
Max
–
500
–
–
1
Unit
V
µA
ns
ns
µA
P. 5 of 10
AS7C4096
AS7C34096
®
Data retention waveform
Data retention mode
VCC
VDR ≥ 2.0V
VCC
VCC
tCDR
tR
VDR
VIH
CE
VIH
AC test conditions
-
Output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figures A, B, and C.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168W
DOUT
+1.728V
+5V
+3.3V
480W
+3.0V
GND
90%
90%
10%
2 ns
Figure A: Input pulse
10%
DOUT
255W
C(14)
GND
Figure B: 5V Output load
320W
DOUT
350W
C(14)
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
2V data retention applies to commercial temperature range operation only.
C = 30pF, except at high Z and low Z parameters, where C = 5pF.
3/23/01; v.1.1
Alliance Semiconductor
P. 6 of 10
AS7C4096
AS7C34096
®
Typical DC and AC characteristics 12
1.4
1.0
0.8
0.6
ISB
0.4
0.2
NOMINAL
Supply voltage (V)
0.6
ISB
0.4
1.2
1.1
1.0
0.9
1.3
1.2
1.1
1.0
0.9
0.8
MIN
NOMINAL
Supply voltage (V)
Output source current IOH
vs. output voltage VOH
120
VCC = VCC(NOMINAL)
100
Ta = 25° C
80
60
40
20
0
Output voltage (V)
3/23/01; v.1.1
VCC
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
VCC = VCC(NOMINAL)
1.0
Ta = 25° C
0.8
0.6
0.4
0.0
0
120
VCC = VCC(NOMINAL)
100
Ta = 25° C
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
35
VCC = VCC(NOMINAL)
30
80
60
40
20
25
20
15
10
5
0
0
–10
35
80
125
Ambient temperature (°C)
1.2
–10
35
80
125
Ambient temperature (°C)
Output sink current IOL
vs. output voltage VOL
140
Output sink current (mA)
140
0.2
0.2
0.8
–55
MAX
1
1.4
Normalized ICC
Normalized access time
Ta = 25° C
5
–55
VCC = VCC(NOMINAL)
1.4
1.3
VCC = VCC(NOMINAL)
25
–10
35
80
125
Ambient temperature (°C)
Normalized access time tAA
vs. ambient temperature Ta
1.5
1.4
625
0.04
0.0
–55
MAX
Normalized access time tAA
vs. supply voltage VCC
1.5
Normalized access time
0.8
0.2
0.0
MIN
Output source current (mA)
ICC
1.0
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.2
ICC
Normalized ICC, ISB
Normalized ICC, ISB
1.2
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Change in tAA (ns)
1.4
Normalized supply current ICC, ISB
vs. supply voltage VCC
0
0
Output voltage (V)
Alliance Semiconductor
VCC
0
250
500
750
Capacitance (pF)
1000
P. 7 of 10
AS7C4096
AS7C34096
®
Package dimensions
c
4443424140393837363534333231 3029 282726252423
A
A1
A2
b
c
d
E1
E
e
L
E1 E
44-pin TSOP II
1 2 3 4 5 6 7 8 9 10111213141516 17181920 2122
d
L
A2
A
44-pin TSOP II
Min(mm) Max(mm)
1.2
0.05
0.15
0.95
1.05
0.30
0.45
0.15 (typical)
18.28
18.54
10.03
10.16
11.56
11.96
0.80 (typical)
0.40
0.60
0–5°
A1
e
b
e
D
b
E1 E2
36-pin SOJ
A
A1
b1
Pin 1
Seating
Plane
c
A2
E
A
A1
A2
b
b1
c
D
e
E
E
36-pin SOJ 400
Min(mils) Max(mils)
.128
0.148
0.027
–
0.102 NOM
0.015
0.020
0.026
0.032
0.007
0.013
.920
.930
0.045
0.055
0.400 NOM
0.435
0.445
Ordering codes
Package
SOJ
TSOP II
Version
5V commercial
5V industrial
3.3V commercial
3.3V industrial
5V commercial
5V industrial
3.3V commercial
3.3V industrial
10 ns
NA
NA
AS7C4096-10JC
NA
NA
NA
AS7C4096-10TC
NA
12 ns
AS7C4096-12JC
AS7C4096-12JI
AS7C34096-12JC
AS7C34096-12JI
AS7C4096-12TC
AS7C4096-12TI
AS7C34096-12TC
AS7C34096-12TI
15 ns
AS7C4096-15JC
AS7C4096-15JI
AS7C34096-15JC
AS7C34096-15JI
AS7C4096-15TC
AS7C4096-15TI
AS7C34096-15TC
AS7C34096-15TI
20 ns
AS7C4096-20JC
AS7C4096-20JI
AS7C34096-20JC
AS7C34096-20JI
AS7C4096-20TC
AS7C4096-20TI
AS7C34096-20TC
AS7C34096-20TI
NA: not available.
3/23/01; v.1.1
Alliance Semiconductor
P. 8 of 10
®
AS7C4096
AS7C34096
Part numbering system
AS7C
X
4096
–XX
SRAM
prefix
Blank: 5V CMOS
3: 3.3V CMOS
Device
number
Access
time
3/23/01; v.1.1
J, T
Package:
J: 400-mil SOJ
T: 400-mil TSOP II
Alliance Semiconductor
X
Temperature ranges:
C: Commercial, 0° C to 70° C
I: Industrial, -40° C to 85° C
P. 9 of 10
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names
may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors
that may appear in this document. The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without
notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information
for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the
application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works
rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or
failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and
agrees to indemnify Alliance against all claims arising from such use.
AS7C4096
AS7C34096
®
3/23/01; v.1.1
Alliance Semiconductor
P. 10 of 10