ALSC ASM3P2111B

ASM3P2111B
May 2005
rev 0.1
Peak EMI Reducing Solution
Features
allows significant system cost savings by reducing the
number of circuit board layers and shielding that are
ƒ
Generates an EMI optimized clock at the output.
required to pass EMI regulations. The ASM3P2111B
ƒ
Input frequency: 25 MHz.
modulates the output of PLL in order to spread the
ƒ
Frequency outputs:
bandwidth of a synthesized clock, thereby decreasing the
o
60 MHz (unmodulated)
peak amplitudes of its harmonics. This results in
o
2 x 48 MHz (unmodulated)
significantly lower system EMI compared to the typical
o
66.6 MHz (modulated): -1.7% down spread
narrow band signal produced by oscillators and most
ƒ
Modulation rate: 30 KHz.
clock generators. Lowering EMI by increasing a signal’s
ƒ
Supply voltage range: 3.3V ± 0.3V.
bandwidth is called spread spectrum clock generation.
ƒ
Available in 8-pin SOIC Package.
ƒ
Commercial and Industrial Temperature range.
ƒ
RoHS Compliant
Applications
ASM3P2111B is targeted towards EMI management for
Product Description
high speed digital applications such as PC peripheral
devices, consumer electronics and embedded controller
The ASM3P2111B is a versatile spread spectrum
frequency
modulator
that
reduces
systems.
electromagnetic
interference (EMI) at the clock source. The ASM3P2111B
Block Diagram
VDD
XIN /CLKIN
XOUT
60 MHz
Crystal
Oscillator
PLL1
48 MHz_1
48 MHz_2
48 MHz_1
PLL2
66.6 MHz
Modulated
VSS
Alliance Semiconductor
2575 Augustine Drive • Santa Clara CA • Tel: 408-855-4900 • Fax: 408-855-4999 • www.alsc.com
ASM3P2111B
May 2005
rev 0.1
Pin Configuration
XIN/ CLKIN
1
8
VSS
7
66.6 MHz
XOUT
2
VDD
3
6
48 MHz_1
4
5
48 MHz_2
60 MHz
ASM3P2111B
Pin Description
Description
Pin #
Pin Name
Type
1
XIN / CLKIN
I
Connection to crystal
2
XOUT
O
Connection to crystal
3
VDD
P
Power supply for the analog and digital blocks (+3.3V)
4
60 MHz
O
Clock output-1 60 MHz un-modulated
5
48 MHz_2
O
Clock output-2 48 MHz_2 un-modulated
6
48 MHz_1
O
Clock output-3 48 MHz_1 un-modulated
7
66.6 MHz
O
Clock output-4 66.6 MHz modulated
8
VSS
P
Ground to entire chip. Connect to System Ground
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ASM3P2111B
May 2005
rev 0.1
Absolute Maximum Ratings
Symbol
VDD, VIN
TSTG
Parameter
Rating
Unit
Voltage on any pin with respect to Ground
-0.5 to +7.0
V
Storage temperature
-65 to +125
°C
0 to 70
°C
TA
Operating temperature
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
150
°C
2
KV
TDV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
Parameter
Symbol
Condition / Description
Min
Typ
Max
Unit
Supply Voltage
VDD
3.3V ± 0.3V
3
3.3
3.6
V
Crystal Resonator Frequency
FXIN
25
-
-
MHz
CL
-
-
15
pF
Output Driver Load Capacitance
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ASM3P2111B
May 2005
rev 0.1
DC Electrical Characteristics
Parameter
Symbol
Conditions / Description
Min
Typ
Max
Unit
IDD
VDD=3.3V, FCLK =25MHz, CL=15pF
41
48
62
mA
IDDL
VDD = 3.3V, Clock Input = 0
20
25
35
mA
VIH
VDD=3.3V
2.0
-
VDD+0.3
V
VIL
VDD=3.3V
VSS-0.3
-
0.8
V
IIH
-1
-
1
µA
IIL
-20
-36
-80
µA
Overall
Supply Current,
Dynamic
Supply Current,
Static
All input pins
High-Level Input
Voltage
Low-Level Input
Voltage
High-Level Input
Current
Low-Level Input
Current (pull-up)
High-Level Output
Source Current
Low-Level Output
Sink Current
IxOH
VDD=V (XIN) = 3.3V, VO=0.4V
-
3
-
mA
IxOL
VDD=3.3V, V (XIN)=VO=2.5V
-
3
-
mA
IOH
VO=2.5V
-
-20
-
mA
IOL
VO=0.4V
-
23
-
mA
ZOH
VO=0.5VDD; output driving high
-
29
-
ZOL
Vo=0.5VDD; output driving low
-
27
-
Ω
Clock Outputs
High-Level Output
Source Current
Low-Level Output
Sink Current
Output Impedance
AC Electrical Characteristics
Parameter
Symbol
Rise Time
tr
Fall Time
tf
Clock Duty
Cycle
Conditions/ Description
VO = 0.8V to 2.0V;
CL = 15pF
VO = 2.0V to 0.8V;
CL = 15pF
Min
Typ
Max
Unit
300
800
900
pS
360
800
900
pS
45
-
55
%
Ratio of pulse width (as measured from
rising edge to next falling edge at VDD /2) to
one clock period
* CL = 15 pF, Input clock frequency = 25 MHz
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ASM3P2111B
May 2005
rev 0.1
Typical Crystal Oscillator Circuit
Crystal
R1 = 510Ω
C1 = 27 pF
C2 = 27 pF
Typical Crystal Specifications
Fundamental AT cut parallel resonant crystal
Nominal frequency
25 MHz
Frequency tolerance
± 50 ppm or better at 25°C
Operating temperature range
-25°C to +85°C
Storage temperature
-40°C to +85°C
Load capacitance
18pF
Shunt capacitance
7pF maximum
ESR
25 Ω
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ASM3P2111B
May 2005
rev 0.1
Package Information
8-Pin SOIC Package
H
E
D
A2
A
C
A1
D
θ
e
L
B
Dimensions
Symbol
Min
Max
Millimeters
Min
Max
A1
0.004
0.010
0.10
0.25
A
0.053
0.069
1.35
1.75
A2
0.049
0.059
1.25
1.50
B
0.012
0.020
0.31
0.51
C
0.007
0.010
0.18
0.25
Inches
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L
0.016
0.050
0.41
1.27
θ
0°
8°
0°
8°
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ASM3P2111B
May 2005
rev 0.1
Ordering Codes
Part number
Marking
ASM3P2111BF-08ST
3P2111BF
8-pin SOIC TUBE, Pb Free
Commercial
ASM3P2111BF-08SR
3P2111BF
8-pin SOIC TAPE & REEL, Pb Free
Commercial
ASM3I2111BF-08ST
3I2111BF
8-pin SOIC TUBE, Pb Free
Industrial
ASM3I2111BF-08SR
3I2111BF
8-pin SOIC TAPE & REEL, Pb Free
Industrial
ASM3P2111BG-08ST
3P2111BG
8-pin SOIC TUBE, Green
Commercial
ASM3P2111BG-08SR
3P2111BG
8-pin SOIC TAPE & REEL, Green
Commercial
ASM3I2111BG-08ST
3I2111BG
8-pin SOIC TUBE, Green
Industrial
ASM3I2111BG-08SR
3I2111BG
8-pin SOIC TAPE & REEL, Green
Industrial
Package Configuration
Temperature Range
Ordering Information
A S M 3 P 2 1 1 1 B F - 0 8
S R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C)
(-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
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ASM3P2111B
May 2005
rev 0.1
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM3P2111B
Document Version: v0.1
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
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assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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