ASM5I9775A June 2005 rev 0.3 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer General Features 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Output frequency range: 8.3MHz to 200MHz Input frequency range: 4.2MHz to 125MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 1 Feedback clock output 2 LVCMOS reference clock inputs 150 pS max output-output skew Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Table. These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28. PLL bypass mode ‘SpreadTrak’ Output enable/disable Industrial temperature range: –40°C to +85°C 52 Pin 1.0 mm TQFP Package RoHS Compliance The PLL is ensured stable, given that the VCO is configured to run between 200 MHz and 500 MHz. This allows a wide range of output frequencies from 8.3 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the Functional Description input reference clock set by the feedback divider, see The ASM5I9775A is a low-voltage high-performance bypassed and the reference clock directly feeds the 200 MHz PLL-based zero delay buffer designed for high- output dividers. This mode is fully static and the minimum speed clock distribution applications. The ASM5I9775A input clock frequency specification does not apply. Frequency Table. When PLL_EN is LOW, PLL is features two reference clock inputs and provides Block Diagram . VCO_SEL (1, 0) PLL_EN TCLK_SEL TCLK0 TCLK1 FB_IN +2 PLL 200500MHZ +2/+4 +4 CLK STOP QA0 QA1 QA2 QA3 QA4 SELA +2/+4 CLK STOP +4/+6 CLK STOP SELB QB0 QB1 QB2 QB3 QB4 QC0 QC1 SELC QC2 QC3 CLK_STP# +4/+6/+8/+12 FB_OUT FB_SEL(1.0) MR#/OE Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM5I9775A June 2005 rev 0.3 VSS 1 MR#/OE CLK_STP# QB0 VDDQB NC VSS QC3 VDDQC QC2 VSS QC1 VDDQC QC0 VSS VCO_SEL Pin Configuration 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VSS 2 38 QB1 3 37 VDDQB SELB 4 36 QB2 SELC 5 35 VSS PLL_EN 6 34 QB3 ASM5I9775A SELA 7 33 VDDQB TCLK_SEL 8 32 QB4 TCLK0 9 31 FB_IN TCLK1 10 30 VSS VCO_SEL1 11 29 FB_OUT VDD 12 28 VDDFB AVDD 13 27 NC VDDQA QA0 VSS QA1 VDDQA QA2 FB_SEL1 QA3 VSS VDDQA QA4 AVSS FB_SEL0 14 15 16 17 18 19 20 21 22 23 24 25 26 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 12 ASM5I9775A June 2005 rev 0.3 Pin Description1 Pin Name I/O Type 9 TCLK0 I, PD LVCMOS LVCMOS/LVTTL reference clock input 10 TCLK1 I, PU LVCMOS LVCMOS/LVTTL reference clock input QA(4:0) O LVCMOS Clock output bank A QB(4:0) O LVCMOS Clock output bank B 44, 46, 48, 50 QC(3:0) O LVCMOS Clock output bank C 29 FB_OUT O LVCMOS Feedback clock output. Connect to FB_IN for normal operation. 31 FB_IN I, PU LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 2 MR#/OE I, PU LVCMOS Output enable/disable input. See Table 2. 3 CLK_STP# I, PU LVCMOS Clock stop enable/disable input. See Table 2. 6 PLL_EN I, PU LVCMOS PLL enable/disable input. See Table 2. 8 TCLK_SEL I, PD LVCMOS Reference select input. See Table 2. 11, 52 VCO_SEL(1,0) I, PD LVCMOS VCO divider select input. See Tables 2, 3 and 4. 7, 4, 5 SEL(A:C) I, PD LVCMOS Frequency select input, Bank (A:C). See Table 3. 20, 14 FB_SEL(1,0) I, PD LVCMOS Feedback dividers select inputs. See Table 4. VDDQA Supply VDD 2.5V or 3.3V Power supply for bank A output clocks VDDQB Supply VDD 2.5V or 3.3V Power supply for bank B output clocks2,3 45, 49 VDDQC Supply VDD 2.5V or 3.3V Power supply for bank C output clocks2,3 28 VDDFB Supply VDD 2.5V or 3.3V Power supply for feedback output clock2,3 13 AVDD Supply VDD 2.5V or 3.3V Power supply for PLL2,3 12 VDD Supply VDD 2.5V or 3.3V Power supply for core and inputs2,3 15 AVSS Supply Ground Analog Ground 1, 19, 24, 30, 35, 39, 43, 47, 51 VSS Supply Ground Common Ground 27, 42 NC 16, 18, 21, 23, 25 32, 34, 36, 38, 40 17, 22, 26 33, 37, 41 Description 2,3 No Connection Notes: 1. PU = Internal pull-up, PD = Internal pull-down 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply pins. 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 12 ASM5I9775A June 2005 rev 0.3 ‘SpreadTrak’ Many systems being designed now utilize a technology When a zero delay buffer is not designed to pass the called Spread Spectrum Frequency Timing Generation. Spread Spectrum feature through, the result is a significant ASM5I9975A is designed so as not to filter off the Spread amount of tracking skew which may cause problems in the Spectrum feature of the Reference Input, assuming it systems requiring synchronization. exists. Table 1. Frequency Table Feedback Output Divider VCO Input Frequency Range (AVDD = 3.3V) Input Frequency Range (AVDD = 2.5V) ÷8 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 50 MHz ÷12 Input Clock * 12 16.6 MHz to 41.6 MHz 16.6 MHz to 33.3 MHz ÷16 Input Clock * 16 12.5 MHz to 31.25 MHz 12.5 MHz to 25 MHz ÷24 Input Clock * 24 8.3 MHz to 20.8 MHz 8.3 MHz to 16.6 MHz ÷32 Input Clock * 32 6.25 MHz to 15.625 MHz 6.25 MHz to 12.5 MHz ÷48 Input Clock * 48 4.2 MHz to 10.4 MHz 4.2 MHz to 8.3 MHz ÷4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz ÷6 Input Clock * 6 33.3 MHz to 83.3 MHz 33.3 MHz to 66.6 MHz ÷8 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 50 MHz ÷12 Input Clock * 12 16.6 MHz to 41.6 MHz 16.6 MHz to 33.3 MHz Table 2. Function Table (Configuration controls) Control Default TCLK_SEL 0 TCLK0 VCO_SEL0 0 VCO÷2 (mid input frequency range) VCO÷4 (low input frequency range) VCO_SEL1 0 Gated by VCO_SEL0 VCO (high input frequency range) PLL_EN 1 Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power-on reset (POR) circuitry during power-up. QA, QB, and QC outputs disabled in LOW state. FB_OUT is not affected by CLK_STP. PLL enabled. The VCO output connects to the output dividers MR/OE CLK_STP 1 1 0 1 TCLK1 Outputs enabled Outputs enabled 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 12 ASM5I9775A June 2005 rev 0.3 Table 3. Function Table (Bank A, B, and C) VCO_SEL1 VCO_SEL0 SELA QA(4:0) SELB QB(4:0) SELC QC(3:0) 0 0 0 ÷4 0 ÷4 0 ÷8 0 0 1 ÷8 1 ÷8 1 ÷12 0 1 0 ÷8 0 ÷8 0 ÷16 0 1 1 ÷16 1 ÷16 1 ÷24 1 x 0 ÷2 0 ÷2 0 ÷4 1 x 1 ÷4 1 ÷4 1 ÷6 Table 4. Function Table (FB_OUT) VCO_SEL1 VCO_SEL0 FB_SEL1 FB_SEL0 FB_OUT 0 0 0 0 ÷8 0 0 0 1 ÷16 0 0 1 0 ÷12 0 0 1 1 ÷24 0 1 0 0 ÷16 0 1 0 1 ÷32 0 1 1 0 ÷24 0 1 1 1 ÷48 1 x 0 0 ÷4 1 x 0 1 ÷8 1 x 1 0 ÷6 1 x 1 1 ÷12 Absolute Maximum Conditions Parameter Description VDD VDD VIN VOUT VTT LU RPS TS TA TJ ØJC ØJA ESDH FIT DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Condition Functional Relative to VSS Relative to VSS Functional Ripple Frequency < 100 kHz Non Functional Functional Functional Functional Functional Min -0.3 2.375 -0.3 -0.3 200 -65 -40 2000 Manufacturing test 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. Max 5.5 3.465 VDD+ 0.3 VDD+ 0.3 VDD ÷2 150 +150 +85 150 23 55 10 Unit V V V V V mA mVp-p °C °C °C °C/W °C/W Volts ppm 5 of 12 ASM5I9775A June 2005 rev 0.3 DC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description Condition Min Typ Max Unit VIL Input Voltage, Low LVCMOS - - 0.8 V VIH Input Voltage, High LVCMOS 2.0 - VDD+0.3 V VOL Output Voltage, Low4 IOL= 24 mA - - 0.55 IOL= 12 mA - - 0.30 VOH Output Voltage, High4 V IOH= –24 mA 2.4 - - V IIL 5 Input Current, Low VIL= VSS - - -100 µA IIH Input Current, High5 VIL= VDD - - 100 µA IDDA PLL Supply Current AVDD only - 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD - - 1 mA IDD Dynamic Supply Current Outputs loaded @ 100 MHz - 225 - Outputs loaded @ 200 MHz - 290 - CIN Input Pin Capacitance - 4 - pF ZOUT Output Impedance 12 15 18 Ω mA DC Electrical Specifications (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description Condition Min. Typ. Max Unit VIL Input Voltage, Low LVCMOS - - 0.7 V VIH Input Voltage, High VOL VOH IIL LVCMOS 1.7 - VDD+0.3 V 4 IOL= 15 mA - - 0.6 V 4 Output Voltage, Low Output Voltage, High IOH= –15 mA 1.8 - - V 5 VIL= VSS - - -100 µA 5 Input Current, Low IIH Input Current, High VIL= VDD - - 100 µA IDDA PLL Supply Current AVDD only - 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD - - 1 mA IDD Dynamic Supply Current Outputs loaded @ 100 MHz - 135 - Outputs loaded @ 200 MHz - 160 - CIN Input Pin Capacitance - 4 - pF ZOUT Output Impedance 14 18 22 Ω mA Notes: 4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 5. Inputs have pull-up or pull-down resistors that affect the input current. 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 12 ASM5I9775A June 2005 rev 0.3 AC Electrical Specifications6 (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency frefDC Input Duty Cycle tr, tf TCLK Input Rise/Fall Time fMAX Maximum Output Frequency DC Output Duty Cycle tr, tf tsk(O) Output Rise/Fall times Propagation Delay (static phase offset) Output-to-Output Skew tsk(B) Bank-to-Bank Skew tPLZ, HZ Condition Min Typ Max Unit 200 - 400 MHz ÷4 Feedback 50 - 100 ÷6 Feedback 33.3 - 66.6 ÷8 Feedback 25 - 50 ÷12 Feedback 16.7 - 33.3 ÷16 Feedback 12.5 - 25 ÷24 Feedback 8.3 - 16.7 ÷32 Feedback 6.3 - 12.5 ÷48 Feedback 4.2 - 8.3 Bypass mode (PLL_EN = 0) 0 - 200 25 - 75 % 0.7V to 1.7V - - 1.0 nS ÷2 Output 100 - 200 ÷4 Output 50 - 100 ÷6 Output 33.3 - 66.6 ÷8 Output 25 - 50 MHz MHz ÷12 Output 16.7 - 33.3 ÷16 Output 12.5 - 25 ÷24 Output 8.3 - 16.7 45 - 55 % 0.7V to 1.8V TCLK to FB_IN, does not include jitter Skew within Bank 0.1 - 1.0 nS -100 - 100 pS - - 150 pS Banks at same frequency - - 150 Banks at different frequency - - 225 Output Disable Time - - 10 nS tPZL, ZH Output Enable Time - - 10 nS BW PLL Closed Loop Bandwidth (–3 dB) VCO_SEL = 0 - 0.5 - 1.0 - VCO_SEL = 1 - 1.0 - 2.0 - tJIT(CC) Cycle-to-Cycle Jitter Same frequency - - 150 Multiple frequencies - - 300 tJIT(PER) Period Jitter - - 100 pS tJIT(φ) I/O Phase Jitter - - 150 pS tLOCK Maximum PLL Lock Time - - 1 mS t(φ) pS MHz pS Note: 6. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 7 of 12 ASM5I9775A June 2005 rev 0.3 AC Electrical Specifications 6 (VDD= 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency frefDC Input Duty Cycle tr, tf TCLK Input Rise/Fall Time fMAX Maximum Output Frequency DC Output Duty Cycle tr, tf Output Rise/Fall times t(φ) Propagation Delay (static phase offset) tsk(O) Output-to-Output Skew tsk(B) Bank-to-Bank Skew Condition Min Typ Max Unit 200 - 500 MHz ÷4 Feedback 50 - 125 ÷6 Feedback 33.3 - 83.3 ÷8 Feedback 25 - 62.5 ÷12 Feedback 16.7 - 41.6 ÷16 Feedback 12.5 - 31.3 ÷24 Feedback 8.3 - 20.8 ÷32 Feedback 6.3 - 15.6 ÷48 Feedback Bypass mode (PLL_EN = 0) 4.2 - 10.4 0 - 200 MHz 25 - 75 % 0.8V to 2.0V - - 1.0 nS ÷2 Output 100 - 200 ÷4 Output 50 - 125 ÷6 Output 33.3 - 83.3 ÷8 Output 25 - 62.5 ÷12 Output 16.7 - 41.6 ÷16 Output 12.5 - 31.3 ÷24 Output 8.3 - 20.8 45 - 55 % 0.8V to 2.4V TCLK to FB_IN, same VDD, does not include jitter Skew within Bank Banks at same voltage, same frequency Banks at same voltage, different frequency Banks at different voltage 0.1 - 1.0 nS -100 - 100 pS - - 150 pS - - 150 - - 225 - - 250 MHz pS tPLZ, HZ Output Disable Time - - 10 nS tPZL, ZH Output Enable Time - - 10 nS BW PLL Closed Loop Bandwidth (–3dB) VCO_SEL = 0 - 0.5 - 1.0 - VCO_SEL = 1 - 1.0 - 2.0 - tJIT(CC) Cycle-to-Cycle Jitter Same frequency - - 150 Multiple frequencies - - 300 tJIT(PER) Period Jitter - - 100 - - 150 pS - - 1 mS tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time I/O at same VDD 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. MHz pS pS 8 of 12 ASM5I9775A June 2005 rev 0.3 Figure 1. AC Test Reference for VDD = 3.3V / 2.5V Figure 2. Propagation Delay t(φ), Static Phase Offset Figure 3. Output Duty Cycle (DC) Figure 4. Output-to-Output Skew, tsk(O) 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 12 ASM5I9775A June 2005 rev 0.3 Package Information 52-lead TQFP Package SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.4646 0.4803 11.8 12.2 D1 0.3898 0.3976 9.9 10.1 E 0.4646 0.4803 11.8 12.2 E1 0.3898 0.3976 9.9 10.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0102 0.0150 0.26 0.38 b1 0.0106 0.0130 0.27 0.33 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.0256 BASE 0.65 BASE 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 12 ASM5I9775A June 2005 rev 0.3 Ordering Information Part Number Marking Package Type Operating Range ASM5I9775A-52-ET ASM5I9775A 52-pin TQFP, Tray Industrial ASM5I9775A-52-ER ASM5I9775A 52-pin TQFP – Tape and Reel Industrial ASM5I9775AG-52-ET ASM5I9775AG 52-pin TQFP, Tray, Green Industrial ASM5I9775AG-52-ER ASM5I9775AG 52-pin TQFP – Tape and Reel, Green Industrial Device Ordering Information A S M 5 I 9 7 7 5 A G - 5 2 - E T R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 12 ASM5I9775A June 2005 rev 0.3 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM5I9775A Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 12