CYPRESS CY29352

CY29352
2.5V or 3.3V, 200-MHz, 11-Output
Zero Delay Buffer
Features
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Description
Output frequency range: 16.67 MHz to 200 MHz
Input frequency range: 16.67 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
±2% max Output duty cycle variation
11 Clock outputs: Drive up to 22 clock lines
LVCMOS reference clock input
125-ps max output-output skew
PLL bypass mode
Spread Aware
Output enable/disable
Pin compatible with MPC9352 and MPC952
Industrial temperature range: –40°C to +85°C
32-Pin 1.0mm TQFP package
The CY29352 is a low voltage high performance 200-MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in 3 banks of 5, 4, and 2
outputs. Bank A divides the VCO output by 4 or 6 while Bank
B divides by 4 and 2 and Bank C divides by 2 and 4 per
SEL(A:C) settings, see Function Table. These dividers allow
output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3.
Each LVCMOS compatible output can drive 50Ω series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:22.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider, see
Table 1.
When PLL_EN# is HIGH, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
VCO
200-500MHz
÷4 /
÷6
÷2
QA0
QA1
QA2
QA3
QA4
LPF
VCO_SEL
SELA
÷4 /
÷2
QB0
QB1
SELB
32
31
30
29
28
27
26
25
Phase
Detector
FB_IN
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
AVSS
FB_IN
QB2
CY29352
24
23
22
21
20
19
18
17
VSS
QB1
QB0
VDDQB
VDDQA
QA4
QA3
VSS
PLL_EN#
AVDD
VDD
QA0
VSS
QA1
QA2
VDDQA
QB3
÷2 /
÷4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REFCLK
VDDQC
QC1
QC0
VSS
VSS
QB3
QB2
VDDQB
PLL_EN#
QC0
QC1
SELC
MR/OE#
Cypress Semiconductor Corporation
Document #: 38-07476 Rev. **
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3901 North First Street
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San Jose, CA 95134
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408-943-2600
Revised March 19, 2003
CY29352
Pin Description[1]
Pin
Name
I/O
Type
Description
6
REFCLK
I, PD
LVCMOS
Reference clock input.
12, 14, 15,
18, 19
QA(0:4)
O
LVCMOS
Clock output bank A.
22, 23, 26, 27 QB(0:3)
O
LVCMOS
Clock output bank B.
30, 31
QC(0,1)
O
LVCMOS
Clock output bank C.
8
FB_IN
I, PD
LVCMOS
Feedback clock input. Connect to an output for normal operation. This
input should be at the same voltage rail as input reference clock. See
Table 1.
1
VCO_SEL
I, PD
LVCMOS
VCO divider select input. See Table 2.
5
MR/OE#
I, PD
LVCMOS
Master reset/output enable/disable input. See Table 2.
9
PLL_EN#
I, PD
LVCMOS
PLL enable/disable input. See Table 2.
2, 3, 4
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C). See Table 2.
16, 20
VDDQA
Supply
VDD
2.5V or 3.3V power supply for bank A output clocks.[2,3]
21, 25
VDDQB
Supply
VDD
2.5V or 3.3V power supply for bank B output clocks.[2,3]
32
VDDQC
Supply
VDD
2.5V or 3.3V power supply for bank C output clocks.[2,3]
10
AVDD
Supply
VDD
2.5V or 3.3V power supply for PLL.[2,3]
11
VDD
Supply
VDD
2.5V or 3.3V power supply for core and inputs.[2,3]
7
AVSS
Supply
Ground
Analog ground.
13, 17, 24,
28, 29
VSS
Supply
Ground
Common ground.
Table 1. Frequency Table
VCO_SEL
Feedback Output
Divider
Input Frequency Range
(AVDD = 3.3V)
VCO
Input Frequency Range
(AVDD = 2.5V)
0
÷2
Input Clock * 2
100 MHz to 200 MHz
100 MHz to 200 MHz
0
÷4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
0
÷6
Input Clock * 6
33.33 MHz to 83.33 MHz
33.33 MHz to 66.67 MHz
1
÷2
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
1
÷4
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
1
÷6
Input Clock * 12
16.67 MHz to 41.67 MHz
16.67 MHz to 33.33 MHz
Table 2. Function Table
Control
Default
0
1
VCO ÷ 2
VCO_SEL
0
VCO
PLL_EN#
0
PLL enabled. The VCO output connects Bypass mode, PLL disabled. The input clock
to the output dividers
connects to the output dividers
MR/OE#
0
Outputs enabled
Outputs disabled (three-state), VCO running at
its minimum frequency
SELA
0
QA = VCO ÷ 4
QA = VCO ÷ 6
SELB
0
QB = VCO ÷ 4
QB = VCO ÷ 2
SELC
0
QC = VCO ÷ 2
QC = VCO ÷ 4
Notes:
1. PD = Internal pull-down.
2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
Document #: 38-07476 Rev. **
Page 2 of 8
CY29352
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
DC Supply Voltage
–0.3
5.5
V
VDD
DC Operating Voltage
Functional
2.375
3.465
V
VIN
DC Input Voltage
Relative to VSS
–0.3
VDD + 0.3
V
DC Output Voltage
Relative to VSS
–0.3
VDD + 0.3
V
Functional
200
VOUT
VDD ÷ 2
VTT
Output termination Voltage
LU
Latch Up Immunity
V
RPS
Power Supply Ripple
Ripple Frequency < 100 kHz
150
mVp-p
TS
Temperature, Storage
Non Functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
155
°C
mA
ØJC
Dissipation, Junction to Case
Functional
42
°C/W
ØJA
Dissipation, Junction to Ambient
Functional
105
°C/W
ESDH
FIT
ESD Protection (Human Body Model)
Failure in Time
2000
Volts
Manufacturing test
10
ppm
DC Parameters (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
Condition
VIL
Input Voltage, Low
LVCMOS
VIH
Input Voltage, High
LVCMOS
VOL
Output Voltage, Low[4]
IOL = 15 mA
VOH
Output Voltage, High[4]
IOH = –15 mA
Min.
Typ.
1.7
Max.
Unit
0.7
V
VDD + 0.3
V
0.6
V
1.8
V
IIL
Input Current, Low
VIL = VSS
–10
µA
IIH
Input Current, High[5]
VIL = VDD
100
µA
IDDA
PLL Supply Current
AVDD only
5
10
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
3
5
mA
IDD
Dynamic Supply Current
CIN
Input Pin Capacitance
ZOUT
Output Impedance
170
mA
4
pF
17 – 20
Ω
DC Parameters (VDD= 3.3V ± 5%, TA = –40°C to +85°C)
Parameter
Description
VIL
Input Voltage, Low
Condition
Min.
Typ.
LVCMOS
VIH
Input Voltage, High
LVCMOS
VOL
Output Voltage, Low[4]
IOL = 24 mA
VOH
Output Voltage, High[4]
IOH = –24 mA
2.0
IOL = 12 mA
Max.
Unit
0.8
V
VDD + 0.3
V
0.55
V
0.30
2.4
V
IIL
Input Current, Low
VIL = VSS
–10
µA
IIH
Input Current, High[5]
VIL = VDD
100
µA
IDDA
PLL Supply Current
AVDD only
5
10
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
3
5
mA
IDD
Dynamic Supply Current
CIN
Input Pin Capacitance
240
mA
4
pF
Output Impedance
14 – 17
Ω
ZOUT
Notes:
4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated
transmission lines.
5. Inputs have pull-down resistors that affect the input current.
Document #: 38-07476 Rev. **
Page 3 of 8
CY29352
AC Parameters[6] (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
fVCO
VCO Frequency
fin
Input Frequency
Condition
÷2 Feedback
Max.
200
400
MHz
200
MHz
50
100
33.33
66.67
÷8 Feedback
25
50
÷12 Feedback
16.67
33.33
Bypass mode (PLL_EN# = 1)
tr , tf
TCLK Input Rise/FallTime
0.7V to 1.7V
fMAX
Maximum Output Frequency
÷2 Output
0
200
25
75
1.0
ns
100
200
MHz
÷4 Output
50
100
÷6 Output
33.33
66.67
÷8 Output
25
50
÷12 Output
16.67
33.33
fMAX < 100 MHz
47
53
fMAX > 100 MHz
44
56
tr , tf
Output Rise/Fall times
0.6V to 1.8V
t(φ)
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD,
does not include jitter
tsk(O)
Output-to-Output Skew
tsk(B)
Bank-to-Bank Skew
Unit
100
÷6 Feedback
Input Duty Cycle
Output Duty Cycle
Typ.
÷4 Feedback
frefDC
DC
Min.
%
%
0.1
1.0
ns
-100
100
ps
Skew within Bank
125
ps
Banks at same voltage, same
frequency
175
ps
Banks at same voltage,
different frequency
225
tPLZ, HZ
Output Disable Time
8
ns
tPZL, ZH
Output Enable Time
10
ns
BW
PLL Closed Loop Bandwidth (-3dB) ÷2 Feedback
÷4 Feedback
tJIT(CC)
Cycle-to-Cycle Jitter
tJIT(PER)
Period Jitter
tJIT(φ)
I/O Phase Jitter
tLOCK
Maximum PLL Lock Time
2
÷6 Feedback
0.6
÷8 Feedback
0.75
÷12 Feedback
0.5
Same frequency
100
Multiple frequencies
300
Same frequency
100
Multiple frequencies
Document #: 38-07476 Rev. **
MHz
1 - 1.5
ps
ps
150
VCO < 300 MHz
150
VCO > 300 MHz
100
ps
1
ms
Page 4 of 8
CY29352
AC Parameters[6] (VDD = 3.3V ± 5%, TA = –40°C to +85°C)
Parameter
Description
fVCO
VCO Frequency
fin
Input Frequency
Condition
÷2 Feedback
÷8 Feedback
25
62.5
÷12 Feedback
16.67
41.67
0.8V to 2.0V
Maximum Output Frequency
÷2 Output
75
1.0
ns
100
200
MHz
50
125
33.33
83.33
÷8 Output
25
62.5
÷12 Output
16.67
41.67
fMAX < 100 MHz
48
52
fMAX > 100 MHz
44
56
Output Rise/Fall times
0.55V to 2.4V
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD,
does not include jitter
tsk(O)
Output-to-Output Skew
tsk(B)
Bank-to-Bank Skew
%
%
0.1
1.0
ns
–100
200
ps
Skew within each Bank
125
ps
Banks at same voltage, same
frequency
175
ps
Banks at same voltage,
different frequency
235
Banks at different voltage
425
tPLZ, HZ
Output Disable Time
tPZL, ZH
Output Enable Time
BW
PLL Closed Loop Bandwidth (-3dB) ÷2 Feedback
I/O Phase Jitter
200
÷6 Output
t(φ)
tJIT(φ)
0
25
÷4 Output
tr , tf
Period Jitter
MHz
MHz
125
TCLK Input Rise/FallTime
tJIT(PER)
500
200
83.33
fMAX
Cycle-to-Cycle Jitter
200
50
tr , tf
Unit
100
33.33
Bypass mode (PLL_EN# = 1)
tJIT(CC)
Max.
÷6 Feedback
Input Duty Cycle
Output Duty Cycle
Typ.
÷4 Feedback
frefDC
DC
Min.
8
10
2
÷4 Feedback
1 – 1.5
÷6 Feedback
0.6
÷8 Feedback
0.75
÷12 Feedback
0.5
100
Multiple frequencies
275
Same frequency
100
Multiple frequencies
150
VCO < 300 MHz
150
100
ns
MHz
Same frequency
VCO > 300 MHz
ns
ps
ps
ps
Maximum PLL Lock Time
1
ms
tLOCK
Note:
6. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at the same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
Document #: 38-07476 Rev. **
Page 5 of 8
CY29352
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R T = 50 ohm
R T = 50 ohm
VTT
VTT
Figure 1. AC Test Reference for VDD = 3.3V / 2.5V
VDD
LVCMOS_CLK
V DD /2
GND
V DD
FB_IN
V DD /2
t(φ)
GND
Figure 2. Propagation Delay t(φ), static phase offset
V DD
V DD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
tSK(O)
GND
Figure 4. Output-to-Output Skew, tsk(O)
Ordering Information
Part Number
Package Type
Product Flow
CY29352AI
32-pin TQFP
Industrial, –40°C to +85°C
CY29352AIT
32-pin TQFP – Tape and Reel
Industrial, –40°C to 85°C
Document #: 38-07476 Rev. **
Page 6 of 8
CY29352
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are trademarks of their respective holders.
Document #: 38-07476 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29352
Document History Page
Document Title:CY29352 2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
Document Number: 38-07476
REV.
ECN No.
Issue
Date
Orig. of
Change
**
124654
03/21/03
RGL
Document #: 38-07476 Rev. **
Description of Change
New Data Sheet
Page 8 of 8