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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
FEATURES
D High Speed 2x2 LVPECL Crosspoint Switch
D LVDS Crosspoint Switch Available in
SN65LVCP22
D 50 ps (Typ), of Peak-to-Peak Jitter
With PRBS = 223–1 Pattern
D Output (Channel-to-Channel) Skew Is 10 ps
(Typ), 50 ps (Max)
D Configurable as 2:1 Mux, 1:2 Demux,
Repeater or 1:2 Signal Splitter
D Inputs Accept LVDS, LVPECL, and CML
Signals
D
D
D
D
Fast Switch Time of 1.7 ns (Typ)
Fast Propagation Delay of 0.75 ns (Typ)
16 lead SOIC and TSSOP Packages
Operating Temperature: −40°C to 85°C
APPLICATIONS
D Gigabit Ethernet Redundant Transmission
Paths
D Gigabit Interface Converters (GBICs)
D Fibre Channel Redundant Transmission
DESCRIPTION
The SN65LVCP23 is a 2x2 LVPECL crosspoint switch.
The dual channels incorporate wide common-mode (0 V
to 4 V) receivers, allowing for the receipt of LVDS,
LVPECL, and CML signals. The dual outputs are LVPECL
drivers to provide high-speed operation. The
SN65LVCP23 provides a single device supporting 2:2
buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2
switching, and LVDS/CML to LVPECL level translation on
each channel. The flexible operation of the SN65LVCP23
provides a single device to support the redundant serial
bus transmission needs (working and protection switching
cards) of fault-tolerant switch systems found in optical
networking, wireless infrastructure, and data communications systems. TI offers an additional gigibit repeater/
translator in the SN65LVDS101.
The SN65LVCP23 uses a fully differential data path to
ensure low-noise generation, fast switching times, low
pulse width distortion, and low jitter. Output
channel-to-channel skew is less than 10 ps (typ) and 50 ps
(max) to ensure accurate alignment of outputs in all
applications. Both SOIC and TSSOP package options are
available.
OUTPUTS OPERATING SIMULTANEOUSLY
1.3 Gbps
223 −1 PRBS
Paths
D
D
D
D
D
D
HDTV Video Routing
Base Stations
VCC = 3.3 V
|VID| = 200 mV, VIC = 1.2 V
Vertical Scale = 400 mV/div
Protection Switching for Serial Backplanes
Network Switches/Routers
OUTPUT 1
OUTPUT 2
650 MHz
Optical Networking Line Cards/Switches
Clock Distribution
Horizontal Scale = 200 ps
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!" #!$% &"' &!
#" #" (" " " !" && )*'
&! #"+ &" ""%* %!&" "+ %% #""'
Copyright 2002−2003, Texas Instruments Incorporated
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE DESIGNATOR
PART NUMBER(1)
SYMBOLIZATION
SOIC
SN65LVCP23D
LVCP23
TSSOP
SN65LVCP23PW
LVCP23
(1) Add the suffix R for taped and reeled carrier
PACKAGE DISSIPATION RATINGS
CIRCUIT
BOARD MODEL
High-K(2)
PACKAGE
SOIC (D)
TA ≤ 25°C
POWER RATING
1361 mW
DERATING FACTOR(1)
ABOVE TA = 25°C
13.9 mW/°C
TA = 85°C
POWER RATING
544 mW
High-K(2)
TSSOP (PW)
1074 mW
10.7 mW/°C
430 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
θJB
θJC
TEST CONDITIONS
Junction-to-board thermal resistance
Junction-to-case thermal resistance
VALUE
UNITS
D
15.7
°C/W
PW
22.1
°C/W
D
26.1
°C/W
17.3
°C/W
165
mW
234
mW
PW
Typical
PD
Device power dissipation
VCC = 3.3−V, TA = 25°C, 2 Gbps
VCC = 3.6−V, TA = 85°C, 2 Gbps
Maximum
FUNCTION TABLE
SEL0
SEL1
OUT0
OUT1
FUNCTION
0
0
IN0
IN0
1:2 Splitter
0
1
IN0
IN1
Repeater
1
0
IN1
IN0
Switch
1
1
IN1
IN1
1:2 Splitter
FUNCTIONAL BLOCK DIAGRAM
OUT 0
OUT 1
EN 0
EN 1
SEL 1
SEL 0
IN 0
IN 1
2
0
1
0
1
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUTS
IN +
VCC
IN −
400 Ω
SEL, EN
7V
7V
300 kΩ
7V
OUTPUTS
VCC
VCC
R
R
VCC
R
OUT +
VCC
7V
OUT −
7V
3
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
Supply voltage(2) range, VCC
−0.5 V to 4 V
CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1)
−0.5 V to 4 V
Receiver Input voltage (IN+, IN−)
−0.7 V to 4.3 V
LVPECL driver output voltage (OUT+, OUT−)
Output current
−0.5 V to 4 V
Continuous
50 mA
Surge
100 mA
Storage temperature range
−65°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Continuous power dissipation
Electrostatic discharge
Human body model(3)
Charged-device mode(4)
235°C
See Dissipation Rating Table
All pins
±5 kV
All pins
±500 V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
Supply voltage, VCC
3
3.3
Receiver input voltage
0
Junction temperature
Operating free-air temperature, TA(1)
−40
Magnitude of differential input voltage |VID|
0.1
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
4
MAX UNIT
3.6
V
4
V
125
°C
85
°C
3
V
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
INPUT ELECTRICAL CHARACTERISTICS
over recommended operatingconditions unless otherwise noted
PARAMETER
TEST CONDITIONS
TYP(1)
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
VIH
VIL
High-level input voltage
2
Low-level input voltage
GND
IIH
High-level input current
VIN = 3.6 V or 2.0 V,
Vcc = 3.6 V
IIL
Low-level input current
VIN = 0.0 V or 0.8 V,
Vcc = 3.6 V
VCL
Input clamp voltage
LVPECL OUTPUT SPECIFICATIONS (OUT0, OUT1)
ICL = −18 mA
VOH
VOL
Output high voltage
VOD
Differential output voltage
RL = 50 Ω to VTT;
VTT = VCC − 2.0 V,
See Figure 2
Output low voltage
CO
Differential output capacitance
RECEIVER DC SPECIFICATIONS (IN0, IN1)
VI = 0.4 sin(4E6πt) + 0.5 V
VTH
VTL
Positive-going differential input voltage threshold
See Figure 1 and Table 1
Negative-going differential input voltage threshold
See Figure 1 and Table 1
Common-mode voltage range
IIN
Input current
CIN
Differential input capacitance
SUPPLY CURRENT
ICCD
DC supply current
(1) All typical values are at 25°C and with a 3.3 V supply.
V
±3
±20
µA
±1
±10
µA
−0.8
−1.5
V
VCC − 0.85
VCC − 1.65
V
VCC − 1.3
VCC − 2.2
600
800
1000
3
−100
mV
mV
mV
25
VID = 100 mV,
VCC = 3.0 V to 3.6 V
VIN = 4 V, VCC = 3.6 V or 0.0
V
pF
100
VID(HYS) Differential input voltage hysteresis
VCMR
VCC
0.8
0.05
mV
3.95
±1
±10
VIN = 0V, VCC = 3.6V or 0.0
VI = 0.4 sin (4E6πt) + 0.5 V
±1
±10
No load
50
1
V
µA
pF
65
mA
5
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tSET
tHOLD
TEST CONDITIONS
MIN
TYP
Input to SEL setup time
Figure 5
1
0.5
Input to SEL hold time
Figure 5
1.1
0.5
MAX
UNIT
ns
ns
tSWITCH SEL to switched output
tPHKL
Disable time, high-level-to-known LOW
Figure 5
1.7
2.5
ns
Figure 4
2
2.5
ns
tPKLH
tLHT
Enable time, known LOW-to-high-level output
Figure 4
2
2.5
ns
Differential output signal rise time (20%−80%)(1)
Differential output signal fall time (20%−80%)(1)
Figure 3
80
110
220
ps
Figure 3
80
110
220
ps
15
30
ps
50
100
ps
0.3
0.5
psRMS
400
750
1100
ps
400
750
1100
ps
20
100
ps
10
50
ps
tHLT
tJIT
VID = 200 mV, 50% duty cycle, VCM = 1.2 V,
650 MHz
VID = 200 mV, PRBS = 223−1 data pattern
and K28.5 (0011111010),
VCM = 1.2 V at 1.3 Gbps
VID = 200 mV, 50% duty cycle, VCM = 1.2 V,
650 MHz
Added peak−to-peak jitter
tJrms
Added random jitter (rms)
tPLHD
tPHLD
Propagation delay time, low-to-high-level output(1)
Propagation delay time, high-to-low-level output(1)
tskew
tCCS
Pulse skew (|tPLHD − tPHLD|)(2)
VCC = 3.3 V, TA = 25°C, See Figure 3
VCC = 3.3 V, TA = 25°C, See Figure 3
Figure 3
Output channel-to-channel skew, splitter mode.
Figure 3
fMAX
Maximum operating frequency(3)
1
GHz
(1) Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps
(2) tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device.
(3) Signal generator conditions: 50% duty cycle, tr or tf 100 ps
(10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD 300 mV.
PIN ASSIGNMENTS
D or PW PACKAGE
(TOP VIEW)
SEL1
SEL0
IN0+
IN0−
VCC
IN1+
IN1−
VCC
6
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN0
EN1
OUT0+
OUT0−
GND
OUT1+
OUT1−
GND
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
IIN+
OUT +
IN+
IN+ +IN−
VIN+
VIC
VID
IN−
VIN−
2
VOD
VOY
OUT −
VOUT++VOUT−
2
VOZ
IIN−
Figure 1. Voltage and Current Definitions
Y
Driver
Device
Receiver
Device
VOD
Z
50 Ω
50 Ω
VTT = VCC −2 V
Figure 2. Typical Termination for LVPECL Output Driver
OUT+
IN+
1 pF
VID
VIN+
IN−
VOD
VOUT+
VTT
50 Ω
OUT−
VIN−
50 Ω
VOUT−
VTT
VIN+
1.4 V
VIN−
1V
0.4 V
0V
−0.4 V
VID
tPHLD
+VOD
tPLHD
80%
0V
Vdiff = (OUT+) − (OUT−)
20%
−VOD
tHLT
tLHT
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse-repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ±10 ns; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
7
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
OUT+
1 V or 1.4 V
1 pF
1.2 V
50 Ω
VOUT+
OUT−
EN
50 Ω
VOUT−
VTT
VTT
3V
1.5 V
0V
EN
+VOD
0V
−VOD
Vdiff = (OUT+) − (OUT−)
tPHKL
tPKLH
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse
width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
Table 1. Receiver Input Voltage Threshold Test
APPLIED VOLTAGES
RESULTING COMMONMODE INPUT VOLTAGE
VIC
1.2 V
OUTPUT
VIA
1.25 V
VIB
1.15 V
VID
100 mV
1.15 V
1.25 V
−100 mV
1.2 V
L
4.0 V
3.9 V
100 mV
3.95 V
H
3.9 V
4. 0 V
−100 mV
3.95 V
L
0.1 V
0.0 V
100 mV
0.05 V
H
0.0 V
0.1 V
−100 mV
0.05 V
L
1.7 V
0.7 V
1000 mV
1.2 V
H
0.7 V
1.7 V
−1000 mV
1.2 V
L
4.0 V
3.0 V
1000 mV
3.5 V
H
3.0 V
4.0 V
−1000 mV
3.5 V
L
1.0 V
0.0 V
1000 mV
0.5 V
H
0.0 V
1.0 V
−1000 mV
0.5 V
L
H = high level, L = low level
8
RESULTING DIFFERENTIAL
INPUT VOLTAGE
H
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
IN0
IN1
SEL
tSET
tHOLD
OUT
IN0
IN1
tSWITCH
EN
IN0
IN1
SEL
tSET
OUT
tHOLD
IN1
IN0
tSWITCH
EN
NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
Figure 5. Input to Select for Both Rising and Falling Edge Setup and Hold Times
9
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREQUENCY
900
80
60
40
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|V ID| = 200 mV
Output = Loaded
0
500
1000
1500
2000
825
750
tPLH
tPHL
675
15
Figure 6
500 mV
10
300 mV
0
20
40
60
80
0
100
0
100
60
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
Input = Clock
Peak-to-Peak Jitter − ps
25
800 mV
40
300 mV
30
20
500 mV
15
10
5
0
0
500
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V
Input = PRBS 223-1
50
20
800 mV
500 mV
10
400
600
700
PEAK-TO-PEAK JITTER
vs
DATA RATE
30
VCC = 3.3 V,
TA = 25°C,
VIC = 400 mV,
Input = PRBS 223−1
300
Figure 8
PEAK-TO-PEAK JITTER
vs
FREQUENCY
60
200
f − Frequency − MHz
Figure 7
PEAK-TO-PEAK JITTER
vs
DATA RATE
50
800 mV
TA − Free-Air Temperature − °C
f − Frequency − MHz
Peak-to-Peak Jitter − ps
20
5
600
−60 −40 −20
2500
VCC = 3.3 V,
TA = 25°C,
VIC = 400 mV,
Input = Clock
25
Peak-to-Peak Jitter − ps
0
30
VCc = 3 − 3.6 V,
VIC = 1.2 V,
|V ID| = 300 mV
Input = 1 MHz
Peak-to-Peak Jitter − ps
t pd − Propagation Delay Time − ps
I CC − Supply Current − mA
100
20
PEAK-TO-PEAK JITTER
vs
FREQUENCY
800 mV
40
500 mV
30
20
300 mV
10
300 mV
200
400
600
800
1000 1200 1400
0
0
Data Rate − Mbps
100 200 300 400 500
f − Frequency − MHz
Figure 9
15
500 mV
10
5
300 mV
50
500 mV
40
30
800 mV
20
VCC = 3.3 V,
TA = 25°C,
VIC = 3.3 V,
Input = PRBS 223−1
10
800 mV
500 mV
0
0
100
200
300
400
500
f − Frequency − MHz
Figure 12
600
700
600
800
1000 1200 1400
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREQUENCY
0
0
200
400
600
800
1000 1200 1400
Data Rate − Mbps
Figure 13
V OD − Differential Output Voltage − mV
20
400
900
60
Peak-to-Peak Jitter − ps
25
200
Figure 11
70
VCC = 3.3 V,
TA = 25°C,
VIC = 3.3 V,
Input = Clock
0
Data Rate − Mbps
PEAK-TO-PEAK JITTER
vs
DATA RATE
30
Peak-to-Peak Jitter − ps
700
Figure 10
PEAK-TO-PEAK JITTER
vs
FREQUENCY
10
600
50
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|V ID| = 200 mV
820
40
740
30
660
20
Added Random Jitter
10
580
500
0
0
250 500 750 1000 1250 1500 1750 2000
f − Frequency − MHz
Figure 14
Period Jitter − ps
0
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PEAK-TO-PEAK JITTER
vs
DATA RATE
230
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
|V ID| = 200 mV
Input = PRBS 223−1
Peak-to-Peak Jitter − ps
200
170
140
110
80
50
20
0
500
1000 1500 2000 2500 3000 3500
Data Rate − Mbps
Figure 15
11
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, ETC.)
3.3 V or 5 V
50 Ω
3.3 V
SN65LVCP23
A
ECL
B
50 Ω
50 Ω
50 Ω
VTT = VCC −2 V
VTT
Figure 16. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
50 Ω
3.3 V
SN65LVCP23
3.3 V
A
CML
B
50 Ω
50 Ω
3.3 V
Figure 17. Current-Mode Logic (CML)
3.3 V
3.3 V
50 Ω
SN65LVCP23
A
ECL
B
50 Ω
1.1 kΩ
VTT
1.5 kΩ
VTT = VCC −2 V
3.3 V
Figure 18. Single-Ended (LVPECL)
3.3 V or 5 V
50 Ω
3.3 V
SN65LVCP23
A
100 Ω
LVDS
B
50 Ω
Figure 19. Low-Voltage Differential Signaling (LVDS)
12
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
IN0 +
OUT0 +
IN0 −
OUT0 −
IN1 +
OUT1 +
IN1 −
OUT1 −
Figure 20. 2 x 2 Crosspoint
OUT0 +
IN +
OUT0 −
(1 or 2)
IN −
OUT1 +
OUT1 −
Figure 21. 1:2 Spitter
IN0 +
OUT0 +
IN0 −
OUT0 −
IN1 +
OUT1 +
IN1 −
OUT1 −
Figure 22. Dual Repeater
IN0 +
OUT +
IN0 −
MUX
IN1 +
(1 or 2)
OUT −
IN1 −
Figure 23. 2:1 MUX
13
PACKAGE OPTION ADDENDUM
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4-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVCP23D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVCP23DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVCP23PW
ACTIVE
TSSOP
PW
16
90
None
CU NIPDAU
Level-1-220C-UNLIM
SN65LVCP23PWR
ACTIVE
TSSOP
PW
16
2000
None
CU NIPDAU
Level-1-220C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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