[ /Title (CD74 HC221 , CD74 HCT22 1) /Subject (High Speed CMOS Logic Dual Monos table Multi- CD54HC221, CD74HC221, CD74HCT221 Data sheet acquired from Harris Semiconductor SCHS166F High-Speed CMOS Logic Dual Monostable Multivibrator with Reset November 1997 - Revised October 2003 Features Description • Overriding RESET Terminates Output Pulse The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. • Triggering from the Leading or Trailing Edge • Q and Q Buffered Outputs • Separate Resets • Wide Range of Output-Pulse Widths • Schmitt Trigger on B Inputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Once triggered, the outputs are independent of further trigger inputs on A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing Edge triggering (A) and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs The minimum value of external resistance, RX, is typically 500Ω. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.7 RXCX at VCC = 4.5V. • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V Ordering Information • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH PART NUMBER CD54HC221F3A Pinout CD54HC221 (CERDIP) CD74HC221 (PDIP, SOIC, SOP, TSSOP) CD74HCT221 (PDIP, SOIC) TOP VIEW 1A 1 16 VCC 1B 2 15 1CXRX 1R 3 14 1CX 1Q 4 13 1Q 2Q 5 12 2Q 2CX 6 11 2R 2CXRX 7 10 2B GND 8 9 2A TEMP. RANGE (oC) © 2003, Texas Instruments Incorporated 16 Ld CERDIP CD74HC221E -55 to 125 16 Ld PDIP CD74HC221M -55 to 125 16 Ld SOIC CD74HC221MT -55 to 125 16 Ld SOIC CD74HC221M96 -55 to 125 16 Ld SOIC CD74HC221NSR -55 to 125 16 Ld SOP CD74HC221PW -55 to 125 16 Ld TSSOP CD74HC221PWR -55 to 125 16 Ld TSSOP CD74HC221PWT -55 to 125 16 Ld TSSOP CD74HCT221E -55 to 125 16 Ld PDIP CD74HCT221M -55 to 125 16 Ld SOIC CD74HCT221MT -55 to 125 16 Ld SOIC CD74HCT221M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright -55 to 125 PACKAGE 1 CD54HC221, CD74HC221, CD74HCT221 Functional Diagram 1CX 1RX VCC 14 15 1CX 1CXRX 13 1Q 1A 1 MONO 1 4 1B 1Q 2 1R 2R 3 11 5 9 2Q 2A MONO 2 10 12 2B 2Q 2CX 2CXRX 6 7 VCC 2CX 2RX TRUTH TABLE INPUTS OUTPUTS A B R Q Q H X H L H X L H L H L ↑ H ↓ H H X X L L H L H ↑ (Note 3) (Note 3) H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low Level, = One High Level Pulse, = One Low Level Pulse NOTE: 1. For this combination the reset input must be low and the following sequence must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1 (or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from lowto-high and the device will be triggered. 2 CD54HC221, CD74HC221, CD74HCT221 Logic Diagram VCC 16 C P RX N A B 1 (9) R 3 (11) 2 (10) P VCC R D RESET FF S C Q R P OP AMP R2 RXCX C VCC MIRROR VOLTAGE QM 15 (7) + QM R3 PP CX R MASK FF S Q MAIN FF R1 R4 Q N VCC 14 (6) PULLDOWN FF D CX Q N 8 C 4 (12) C (13) 5 Q GND R Q Q + OP AMP 3 CD54HC221, CD74HC221, CD74HCT221 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 2): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time, tr, tf on Inputs A and R 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) Input Rise and Fall Time, tr, tf on Input B 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VIH or VIL - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V 4 CD54HC221, CD74HC221, CD74HCT221 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA PARAMETER Input Leakage Current Quiescent Device Current MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 3) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All Inputs 0.3 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite For Switching Function 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tWL 2 70 - - 90 - 105 - ns 4.5 14 - - 18 - 21 - ns 6 12 - - 15 - 18 - ns HC TYPES Input Pulse Width A Input Pulse Width B tWH 2 70 - - 90 - 105 - ns 4.5 14 - - 18 - 21 - ns 6 12 - - 15 - 18 - ns 5 CD54HC221, CD74HC221, CD74HCT221 Prerequisite For Switching Function (Continued) 25oC PARAMETER Input Pulse Width Reset -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tWL 2 70 - - 90 - 105 - ns 4.5 14 - - 18 - 21 - ns 6 12 - - 15 - 18 - ns 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns Recovery Time R to A or B tSU 6 0 - - 0 - 0 - ns Output Pulse Width Q or Q CX = 0.1µF RX = 10kΩ tW 5 630 - 770 602 798 595 805 µs Output Pulse Width Q or Q CX = 28pF, RX = 2kΩ tW 4.5 - 140 - - - - - ns CX = 1000pF, RX = 2kΩ tW 4.5 - 1.5 - - - - - µs CX = 1000pF, RX = 10kΩ tW 4.5 - 7 - - - - - µs Input Pulse Width A tWL 4.5 14 - - 18 - 21 - ns Input Pulse Width B tWH 4.5 14 - - 18 - 21 - ns Input Pulse Width Reset tWL 4.5 18 - - 23 - 27 - ns Recovery Time R to A or B tSU 4.5 0 - - 0 - 0 - ns Output Pulse Width Q or Q CX = 0.1µF RX = 10kΩ tW 5 630 - 770 602 798 595 805 µs Output Pulse Width Q or Q CX = 28pF, RX = 2kΩ tW 4.5 - 140 - - - - - ns CX = 1000pF, RX = 2kΩ tW 4.5 - 1.5 - - - - - µs CX = 1000pF, RX = 10kΩ tW 4.5 - 7 - - - - - µs HCT TYPES Switching Specifications Input tr, tf = 6ns PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH CL = 50pF 2 - - 210 - 265 - 315 ns CL = 50pF 4.5 - - 42 - 53 - 63 ns CL = 50pF 6 - - 36 - 45 - 54 ns CL = 15pF 5 - 18 - - - - - ns CL = 50pF 2 - - 170 - 215 - 255 ns CL = 50pF 4.5 - - 34 - 43 - 51 ns CL = 50pF 6 - - 29 - 37 - 43 ns CL = 15pF 5 - 14 - - - - - ns HC TYPES Propagation Delay, Trigger A, B, R to Q Propagation Delay, Trigger A, B, R to Q tPHL 6 CD54HC221, CD74HC221, CD74HCT221 Switching Specifications Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH CL = 50pF 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns 6 - - 27 - 34 - 41 ns 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns 6 - - 31 - 38 - 46 ns 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - - - - 10 - 10 - 10 pF - 4.5 to 5.5 - ±2 - - - - - % CPD - 5 - 166 - - - - - pF Propagation Delay, Trigger A, B, R to Q tPLH CL = 50pF 4.5 - - 42 - - - 63 ns CL = 15pF 5 - 18 - - - - - ns Propagation Delay, Trigger A, B, R to Q tPHL CL = 50pF 4.5 - - 34 - 43 - 51 ns CL = 15pF 5 - 14 - - - - - ns Propagation Delay, R to Q tPLH CL = 50pF 4.5 - - 38 - - - 57 ns Propagation Delay, R to Q tPHL CL = 50pF 4.5 - - 37 - - - 56 ns tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - - - - 10 - 10 - 10 pF - 4.5 to 5.5 - ±2 - - - - - % - 5 - 166 - - - - - pF PARAMETER Propagation Delay, R to Q Propagation Delay, R to Q Output Transition Time Input Capacitance tPHL tTLH, tTHL CIN Pulse Width Match Between Circuits in the Same Package CX = 1000pF, RX = 10kΩ Power Dissipation Capacitance (Notes 4, 5) CL = 50pF CL = 50pF HCT TYPES Output Transition Time Input Capacitance CIN Pulse Width Match Between Circuits in the Same Package CX = 1000pF, RX = 10kΩ Power Dissipation Capacitance (Notes 4, 5) CPD NOTES: 4. CPD is used to determine the dynamic power consumption, per multivibrator. 5. PD = (CPD + CL) VCC2 fi + Σ where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. 7 CD54HC221, CD74HC221, CD74HCT221 Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL CLOCK 50% 50% 1.3V 0.3V FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns tf = 6ns tr = 6ns VCC 90% 50% 10% GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns 1.3V 1.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL 2.7V 0.3V GND tWL INPUT tfCL = 6ns I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8 CD54HC221, CD74HC221, CD74HCT221 Typical Performance Curves RX = 10K RX = 10K VCC = 5V TA = 25oC 680 0.9 K FACTOR tW, PULSE WIDTH (µs) 685 CX = 1µF 675 670 HCT 0.8 0.7 665 -75 -50 -25 0 25 50 75 100 125 150 0.6 175 0 2 4 6 VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (oC) FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs TEMPERATURE 10 FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE 106 106 VCC = 4.5V VCC = 2V 105 tW, PULSE WIDTH (µs) 105 tW, PULSE WIDTH (µs) 8 104 103 RX = 100K 102 RX = 50K 10 RX = 10K RX = 2K 1 104 103 102 RX = 100K 10 RX = 10K RX = 50K RX = 2K 1 0.1 0.1 10 102 103 104 105 106 107 108 10 CX, TIMING CAPACITANCE (pF) 102 103 104 105 106 107 CX, TIMING CAPACITANCE (pF) FIGURE 7. HC221 OUTPUT PULSE WIDTH vs CX FIGURE 8. HC/HCT221 OUTPUT PULSE WIDTH vs CX 9 108 CD54HC221, CD74HC221, CD74HCT221 10 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8780501EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC221F ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC221F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC221E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC221EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC221M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC221PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT221E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT221EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT221M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT221MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC221M96 Package Package Pins Type Drawing SOIC SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC221NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC221PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HCT221M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC221M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC221NSR SO NS 16 2000 346.0 346.0 33.0 CD74HC221PWR TSSOP PW 16 2000 346.0 346.0 29.0 CD74HCT221M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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