A61L73081 Series 128K X 8 BIT HIGH SPEED CMOS SRAM Document Title 128K X 8 BIT HIGH SPEED CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue July 14, 2000 Preliminary 1.0 Change ICC1 from 120mA to 220mA April 26, 2001 Final 100mA to 210mA Change ISB1 from 8mA to 12mA Change ICDR from 1mA to 5mA Final spec. release (April, 2001, Version 1.0) AMIC Technology, Inc. A61L73081 Series 128K X 8 BIT HIGH SPEED CMOS SRAM Features n n n n n n n n n Center power pinout Supply voltage: 3.3V±10% Access times: 12/15 ns (max.) Current: Operating: -12: 220mA (max.) -15: 210mA (max.) Standby: TTL: 25mA (max.) CMOS: 12mA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL compatible Common I/O using three-state output Data retention voltage: 2V (min.) Available in 32-pin 300mil / 400mil SOJ packages General Description The A61L73081 is a high-speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a 3.3V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when chip enable is disable, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ A0 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CE 5 28 OE 27 I/O 7 26 I/O 6 I/O 0 6 I/O 1 7 VCC 8 GND 9 I/O 2 10 I/O 3 11 WE A61L73081S(SW) (April, 2001, Version 1.0) 1 25 GND 24 VCC 23 I/O5 22 I/O 4 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 1 AMIC Technology, Inc. A61L73081 Series Block Diagram A0 ADDRESS 1,048,576-BIT DECODER MEMORY ARRAY A16 8 I/O0 - I/O 7 8 I/O CONTROL 8 WE CONTROL LOGIC OE CE Pin Descriptions – SOJ (April, 2001, Version 1.0) Pin No. Symbol 1-4, 13-21, 29-32 A0 - A16 Address Inputs 6-7, 10-11, 22-23, 26-27 I/O0 - I/O7 Data Inputs/Outputs 5 CE Chip Enable 28 OE Output Enable 12 WE Write Enable 8, 24 VCC Power Supply 9, 25 GND Ground 2 Description AMIC Technology, Inc. A61L73081 Series Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.5 V VIL Input Low (1) Voltage -0.5 0 +0.8 V CL Output Load - - 30 pF Absolute Maximum Ratings* *Comments VCC to GND . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V IN, IN/OUT Volt to GND . . . . . . . . . . -0.5V to VCC +0.5V Operating Temperature, Topr . . . . . . . . . . . 0°C to +70°C Storage Temperature, Tstg . . . . . . . . . . -55°C to +125°C Temperature Under Bias, Tbias . . . . . . . . -10°C to +85°C Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . . . 0.7W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol Parameter (TA = 0°C to + 70°C, VCC = 3.3V ± 10%, GND = 0V) A61L73081-12 A61L73081-15 Min. Max. Min. Max. Unit Conditions ILI Input Leakage - 2 - 2 µA VIN = GND to VCC ILO Output Leakage - 2 - 2 µA CE = VIH, OE = VIH VI/O = GND to VCC Dynamic Operating Current - 220 - 210 mA CE = VIL, II/O = 0 mA Min. Cycle, Duty = 100% - 25 - 25 mA CE = VIH - 12 - 12 mA CE ≥ VCC - 0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V ICC1 (2) ISB ISB1 Standby Power Supply Current VOL Output Low Voltage - 0.4 - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - 2.4 - V IOH = -4 mA Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns. (April, 2001, Version 1.0) 3 AMIC Technology, Inc. A61L73081 Series Truth Table CE OE WE I/O Operation Supply Current Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC1 Read L L H DOUT ICC1 Write L X L DIN ICC1 Mode Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 8 pF VIN = 0V CI/O* Input/Output Capacitance - 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%) Symbol Parameter A61L73081-12 A61L73081-15 Unit Min. Max. Min. Max. 12 - 15 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 12 - 15 ns tACE Chip Enable Access Time - 12 - 15 ns tOE Output Enable to Output Valid - 6 - 8 ns tCLZ Chip Enable to Output in Low Z 3 - 3 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - ns tCHZ Chip Disable Output in High Z 0 6 - 8 ns tOHZ Output Disable to Output in High Z 0 6 0 8 ns tOH Output Hold from Address Change 3 - 3 - ns (April, 2001, Version 1.0) 4 AMIC Technology, Inc. A61L73081 Series AC Characteristics (continued) Symbol A61L73081-12 Parameter A61L73081-15 Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 12 - 15 - ns tCW Chip Enable to End of Write 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - ns tAW Address Valid to End of Write 10 - 12 - ns tWP Write Pulse Width 10 - 12 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 6 0 8 ns tDW Data to Write Time Overlap 6 - 7 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - ns Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1) tRC Address tAA OE tOE tOH tOLZ5 CE tOHZ5 tCHZ5 tACE tCLZ5 DOUT (April, 2001, Version 1.0) 5 AMIC Technology, Inc. A61L73081 Series Timing Waveforms (continued) Read Cycle 2(1, 2, 4) tRC Address tAA tOH tOH DOUT Read Cycle 3(1, 3, 4,) CE tACE tCLZ5 tCHZ5 DOUT Notes: 1. 2. 3. 4. 5. WE is high for Read Cycle. Device is continuously enabled, CE = VIL. Address valid prior to or coincident with CE transition low. OE = VIL. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (April, 2001, Version 1.0) 6 AMIC Technology, Inc. A61L73081 Series Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address tAW tWR 3 tCW 5 CE (4) tAS1 tWP 2 WE tDW tDH DIN tWHZ 7 tOW 7 DOUT Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 CE tWR3 tCW5 (4) tWP2 WE tDW tDH DIN tWHZ DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE and a low WE . tWR is measured from the earliest of CE or WE going high to the end of the Write cycle If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. (April, 2001, Version 1.0) 7 AMIC Technology, Inc. A61L73081 Series AC Test Conditions Input Pulse Levels 0V to 3.0V Input Rise and Fall Time 3 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 3.3V 317Ω DATA OUT OUTPUT 351Ω 5pF* RL=50Ω ZO=50Ω VT=1.5V * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C) Symbol VDR Parameter VCC for Data Retention Min. Max. Unit 2 3.6 V ICCDR Data Retention Current - 5 mA tCDR Chip Disable to Data Retention Time 0 - ns tR Operation Recovery Time Conditions CE ≥ VCC - 0.2V VCC = 2.0V CE ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V See Retention Waveform TRC* - ms tRC = Read Cycle Time (April, 2001, Version 1.0) 8 AMIC Technology, Inc. A61L73081 Series Low VCC Data Retention Waveform DATA RETENTION MODE VCC 3.0V 3.0V tCDR tR VDR ³ > 2.0V VIH CE VIH CE ³ > VDR - 0.2V Ordering Information Part No. Access Time (ns) Operating Current Max. (mA) CMOS Standby Max. (mA) 12 220 12 A61L73081S-12 32L 300mil SOJ A61L73081SW-12 32L 400mil SOJ A61L73081S-15 32L 300mil SOJ 15 210 A61L73081SW-15 (April, 2001, Version 1.0) Package 12 32L 400mil SOJ 9 AMIC Technology, Inc. A61L73081 Series Package Information SOJ 32L(300mil) Outline Dimensions unit: inches/mm D 17 1 16 E1 32 b b1 S e D Seating Plane Symbol A y Min 0.025" y 0.004 Dimensions in inches A1 A2 C E E2 y Dimensions in mm Min Nom Max Min Nom Max A 0.128 0.132 0.140 3.25 3.35 3.56 A1 0.052 - - 2.08 - - A2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.020 0.41 0.46 0.51 b1 0.026 0.028 0.032 0.66 0.71 0.81 C 0.006 0.008 0.012 0.15 0.20 0.30 D 0.820 0.825 0.830 20.83 20.96 21.08 E 0.330 0.335 0.340 8.39 8.51 8.63 E1 0.295 0.300 0.305 7.49 7.62 7.75 E2 0.260 0.267 0.274 6.61 6.78 6.96 e - 0.050 - - 1.27 - S - - 0.048 - - 1.22 y - - 0.004 - - 0.10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. Package Information (April, 2001, Version 1.0) 10 AMIC Technology, Inc. A61L73081 Series SOJ 32L (400mil) Outline Dimensions unit: inches/mm D 17 1 16 E1 32 b b1 S e D Seating Plane Symbol 0.004 Dimensions in inches A θ y Min 0.025" y A1 A2 C E E2 y Dimensions in mm Min Nom Max Min Nom Max 3.68 A 0.131 0.138 0.145 3.33 3.51 A1 0.082 - - 2.08 - - A2 0.105 0.110 0.115 2.67 2.79 2.91 b 0.016 0.018 0.020 0.41 0.46 0.51 b1 0.026 0.028 0.032 0.66 0.71 0.81 C 0.006 0.008 0.011 0.15 0.20 0.28 D 0.820 0.825 0.830 20.83 20.96 21.08 E 0.435 0.440 0.445 11.05 11.18 11.31 E1 0.395 0.400 0.405 10.03 10.16 10.29 E2 0.360 0.370 0.380 9.15 9.40 9.65 e - 0.050 - - 1.27 - S - - 0.045 - - 1.14 y - - 0.004 - - 0.10 θ -5° 2° 6° -5° 2° 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (April, 2001, Version 1.0) 11 AMIC Technology, Inc.