LP62E16512-I Series Preliminary 512K X 16 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 16 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue April 26, 2002 Preliminary (April, 2002, Version 0.0) AMIC Technology, Inc. LP62E16512-I Series Preliminary 512K X 16 BIT LOW VOLTAGE CMOS SRAM Features General Description n Operating voltage: 1.65V to 2.2V n Access times: 70 ns (max.) n Current: Very low power version: Operating: 40mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min.) n Available in 48-ball CSP (8×10mm) packages The LP62E16512-I is a low operating current 8,388,608bit static random access memory organized as 524,288 words by 16 bits and operates on low power voltage from 1.65V to 2.2V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Product Family Product Family Operating Temperature VCC Range LP62E16512 -40°C ~ +85°C 1.65V~2.2V Power Dissipation Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC2, Typ.) 70ns 0.1µA 0.5µA 3mA Package Type 48 CSP 1. Typical values are measured at VCC = 1.8V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 1.2V. Pin Configurations n CSP (Chip Size Package) 48-pin Top View PRELIMINARY (April, 2002, Version 0.0) 1 2 3 4 A LB OE A0 B I/O9 HB A3 C I/O10 I/O11 D GND I/O12 E VCC I/O13 F I/O15 I/O14 G I/O16 NC A12 H A18 A8 A9 1 5 6 A1 A2 CS2 A4 CS1 I/O1 A5 A6 I/O2 I/O3 A17 A7 I/O4 VCC NC A16 I/O5 GND A14 A15 I/O6 I/O7 A13 WE I/O8 A10 A11 NC AMIC Technology, Inc. LP62E16512-I Series Block Diagram VCC A0 GND 1024 X 8192 DECODER MEMORY ARRAY A17 A18 I/O9 I/O1 INPUT COLUMN I/O INPUT DATA CIRCUIT DATA CIRCUIT I/O16 I/O8 LB CS1 CS2 LB HB OE WE PRELIMINARY CONTROL CIRCUIT (April, 2002, Version 0.0) 2 AMIC Technology, Inc. LP62E16512-I Series Pin Description - CSP Symbol Description Symbol Description A0 - A18 Address Inputs HB Higher Byte Enable Input (I/O9 - I/O16) CS1 , CS2 Chip Enable OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply WE Write Enable Input GND Ground LB Byte Enable Input (I/O1 - I/O8) NC No Connection Recommended DC Operating Conditions (TA = -40°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit 1.65 1.8 2.2 V 0 0 0 V VCC Supply Voltage GND Ground VIH Input High Voltage 1.4 - VCC + 0.3 V VIL Input Low Voltage -0.3 - +0.4 V CL Output Load - - 30 pF TTL Output Load - - 1 - PRELIMINARY (April, 2002, Version 0.0) 3 AMIC Technology, Inc. LP62E16512-I Series Absolute Maximum Ratings* *Comments VCC to GND ..............................................-0.5V to +3.0V IN, IN/OUT Volt to GND ................... -0.5V to VCC + 0.5V Operating Temperature, Topr ...................-40°C to +85°C Storage Temperature, Tstg.....................-55°C to +125°C Power Dissipation, PT ...................................................................... 0.7W Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = -40°C to + 85°C, VCC = 1.65V to 2.2V, GND = 0V) Symbol ILI Parameter Input Leakage Current LP62E16512-70LLI Min. Max. - 1 Unit µA Conditions VIN = GND to VCC CS1 = VIH or CS2 = VIL or ILO Output Leakage Current - 1 µA LB = HB = VIH VI/O = GND to VCC ICC Active Power Supply Current ICC1 CS1 = VIL , CS2 = VIH , - 5 mA LB = VIL or HB = VIL , II/O = 0mA - 40 mA Min. Cycle, Duty = 100%, CS1 = VIL , CS2 = VIH , LB = VIL or HB = VIL Dynamic Operating II/O = 0mA Current ICC2 CS1 ≤ 0.2V, CS2 ≥ VCC-0.2V , - 5 mA LB ≤ 0.2V or HB ≤ 0.2V f = 1MHz , II/O = 0mA ISB - 1 mA CS1 = VIH or CS2 = VIL or LB = HB = VIH Standby Current ISB1 CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or - 10 µA LB = HB ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VOL Output Low Voltage - 0.2 V IOL = 0.1 mA VOH Output High Voltage 1.4 - V IOH = -1.0 mA PRELIMINARY (April, 2002, Version 0.0) 4 AMIC Technology, Inc. LP62E16512-I Series Truth Table I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current CS1 CS2 OE WE LB HB H X X X X X High - Z High - Z ISB1, ISB X L X X X X High - Z High - Z ISB1, ISB X X X X H H High - Z High - Z ISB1, ISB L L Read Read ICC1, ICC2, ICC L H Read High - Z ICC1, ICC2, ICC H L High - Z Read ICC1, ICC2, ICC L L Write Write ICC1, ICC2, ICC L H Write High - Z ICC1, ICC2, ICC H L High - Z Write ICC1, ICC2, ICC L H L H L X H L L H H H L X High - Z High - Z ICC1, ICC2, ICC L H H H X L High - Z High - Z ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. PRELIMINARY (April, 2002, Version 0.0) 5 AMIC Technology, Inc. LP62E16512-I Series AC Characteristics (TA = -40°C to +85°C, VCC = 1.65V to 2.2V) Symbol LP62E16512-70LLI Parameter Unit Min. Max. 70 - ns Read Cycle tRC Read Cycle Time tAA Address Access Time - 70 ns tAcs1 , tAcs2 Chip Enable Access Time - 70 ns tBE Byte Enable Access Time - 70 ns tOE Output Enable to Output Valid - 35 ns tCLZ1 , tCLZ2 Chip Enable to Output in Low Z 10 - ns tBLZ Byte Enable to Output in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 5 - ns tCHZ1 , tCHZ2 Chip Disable to Output in High Z - 25 ns tBHZ Byte Disable to Output in High Z - 25 ns tOHZ Output Disable to Output in High Z - 25 ns tOH Output Hold from Address Change 5 - ns Write Cycle Time 70 - ns tCW1 , tCW2 Chip Enable to End of Write 60 - ns tBW Byte Enable to End of Write 60 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 60 - ns tWP Write Pulse Width 50 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z - 25 ns tDW Data to Write Time Overlap 30 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Write Cycle tWC Note: tCLZ1 , tCLZ2 , tBLZ , tOLZ , tCHZ1, tCHZ2 , tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. PRELIMINARY (April, 2002, Version 0.0) 6 AMIC Technology, Inc. LP62E16512-I Series Timing Waveforms (1, 2, 4) Read Cycle 1 tRC Address tAA tOH tOH DOUT (1, 2, 3) Read Cycle 2 tRC Address tAA CS1 CS2 tACS1 , tACS2 tCHZ1 , tCHZ2 tCLZ1 , tCLZ2 tBE HB, LB tBLZ 5 tBHZ 5 OE tOE tOHZ 5 tOLZ 5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CS1 = VIL, or CS2 = VIH , HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CS1 and ( HB and, or LB ) transition low or CS2 transition High. 4. OE = VIL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (April, 2002, Version 0.0) 7 AMIC Technology, Inc. LP62E16512-I Series Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC Address tWR3 tAW tCW CS1 CS2 tBW HB, LB tAS1 tWP2 WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT PRELIMINARY (April, 2002, Version 0.0) 8 AMIC Technology, Inc. LP62E16512-I Series Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tAW tAS1 tWR3 tCW1 , tCW 2 CS1 CS2 tBW HB, LB tWP WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT PRELIMINARY (April, 2002, Version 0.0) 9 AMIC Technology, Inc. LP62E16512-I Series Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC Address tAW tCW1 , tCW2 CS1 tAS1 tWR3 tBW2 CS2 HB, LB tWP WE tDW tDH DATA IN tWHZ 4 tOW DATA OUT Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low CS1 , WE and ( HB and , or LB ) or a high CS2. 3. tWR is measured from the earliest of CS1 or WE or ( HB and , or LB ) going high or CS2 going Low to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. PRELIMINARY (April, 2002, Version 0.0) 10 AMIC Technology, Inc. LP62E16512-I Series AC Test Conditions Input Pulse Levels 0.2V to VCC-0.2V Input Rise And Fall Time 5 ns Input and Output Timing Reference Levels 0.8V Output Load See Figures 1 and 2 TTL TTL CL CL 5pF 30pF * Including scope and jig. * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2 , tBHZ , tBLZ , tOLZ, tCHZ1, tCHZ2 , tOHZ, tWHZ, and tOW Data Retention Characteristics (TA = -40°C to 85°C) Symbol VDR Parameter VCC for Data Retention Min. Max. Unit 1.2 2.2 V Conditions CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or LB = HB ≥ VCC-0.2V VCC = 1.2V, ICCDR Data Retention Current - 0.2* µA tCDR Chip Disable to Data Retention Time 0 - ns tRC - ns 5 - ms tR Operation Recovery Time tVR VCC Rising Time from Data Retention Voltage to Operating Voltage * LP62E16512 - 70LLI PRELIMINARY CS1 ≥ VCC - 0.2V or CS2 ≤ 0.2V or LB = HB ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V See Retention Waveform ICCDR: max. 0.1µA at TA = 25°C (0.2µA at TA = 0°C to + 40°C ) (April, 2002, Version 0.0) 11 AMIC Technology, Inc. LP62E16512-I Series Low VCC Data Retention Waveform (1) ( CS1 Controlled) DATA RETENTION MODE VCC 1.65V 1.65V tCDR tR VDR ≥ 1.2V tVR VIH CS1 VIH CS1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CS2 Controlled) DATA RETENTION MODE VCC 1.65V 1.65V tCDR tR VDR ≥ 1.2V tVR CS2 VIL VIL CS2 ≤ 0.2V Ordering Information Part No. Access Time(ns) Operating Current Max.(mA) Standby Current Max.(uA) Package LP62E16512U-70LLI 70 40 10 48L CSP PRELIMINARY (April, 2002, Version 0.0) 12 AMIC Technology, Inc. LP62E16512-I Series Package Information 48LD CSP ( 8 x 10 mm ) Outline Dimensions (48TFBGA) unit: mm BOTTOM VIEW TOP VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (48X) 6 5 4 3 2 1 1 2 3 4 5 6 A B A E1 E B e D1 A 0.10 C SIDE VIEW D 0.20(4X) Symbol A A1 A2 D E D1 E1 e b A SEATING PLANE A1 C C D E F G H e B C D E F G H Dimensions in mm MIN. NOM. MAX. --0.20 0.48 7.90 9.90 ------0.30 --0.25 0.53 8.00 10.00 3.75 5.25 0.75 0.35 1.20 0.30 0.58 8.10 10.10 ------0.40 Notes: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. 4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 5. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD) PRELIMINARY (April, 2002, Version 0.0) 13 AMIC Technology, Inc.