AMICC A82DL1644UG-70

A82DL16x4T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,
A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only,
Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM
Preliminary
Document Title
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x4T(U) 16 Megabit
(2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 4M
(256Kx16 Bit) Static RAM
Revision History
Rev. No.
0.0
History
Issue Date
Initial issue
August 15, 2005
PRELIMINARY (August, 2005, Version 0.0)
Remark
Preliminary
AMIC Technology, Corp.
A82DL16x4T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,
A82DL16x4T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only,
Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM
Preliminary
DISTINCTIVE CHARACTERISTICS
- Suspends erase operations to allow programming in
same bank
Data Polling and Toggle Bit
- Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
- Reduces overall programming time when issuing
multiple program command sequences
MCP Features
Single power supply operation 2.7 to 3.6 volt
High Performance
- Access time as fast as 70ns
Package 69-Ball TFBGA (8x11x1.4 mm)
Industrial operating temperature range: -40°C to 85°C
for –U; -25°C to 85°C for –I
Flash Features
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/ Busy output (RY/ BY )
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin ( RESET )
- Hardware method of resetting the internal state machine
to reading array data
WP /ACC input pin
- Write protect ( WP ) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function accelerates program timing
Sector protection
- Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program
or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package
- 69-Ball TFBGA (8x11x1.4 mm)
Top or bottom boot block
Manufactured on 0.18 µm process technology
- Compatible with AM42DL16x4D devices
Compatible with JEDEC standards
- Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
- Access time as fast as 70ns
- Program time: 7µs/word typical utilizing Accelerate
function
Ultra low power consumption (typical values)
- 2mA active read current at 1MHz
- 10mA active read current at 5MHz
- 200nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125°C
- Reliable operation for the life of the system
LP SRAM Features
Power supply range: 2.7V to 3.6V
Access times: 70 ns (max.)
Current:
Very low power version: Operating: 35mA(max.)
Standby: 10uA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chips enable inputs for easy
application
Data retention voltage: 2.0V (min.)
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
PRELIMINARY (July, 2005, Version 0.0)
1
AMIC Technology, Corp.
A82DL16x4T(U) Series
GENERAL DESCRIPTION
A82DL16x4T(U) Features
The A82DL16x2T(U) family consists of 16 megabit, 3.0 voltonly flash memory devices, organized as 1,048,576 words of
16 bits each or 2,097,152 bytes of 8 bits each. Word mode
data appears on I/O0–I/O15; byte mode data appears on I/O0–
I/O7. The device is designed to be programmed in-system
with the standard 3.0 volt VCC supply, and can also be
programmed in standard EPROM programmers.
The device is available with an access time of 70ns. The
devices are offered in 69-ball Fine-pitch BGA. Standard
control pins—chip enable ( CE_F ), write enable ( WE ), and
The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits:
RY/ BY pin, I/O7 ( Data Polling) and I/O6/I/O2 (toggle bits).
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both modes.
output enable ( OE )—control normal read and write
operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A82DL16x4T(U) devices uses multiple bank architectures to provide flexibility for different applications. Three
devices are available with these bank sizes:
Device
DL1624
DL1634
DL1644
PRELIMINARY
Bank 1
2 Mb
4 Mb
8 Mb
Bank 2
14 Mb
12 Mb
8 Mb
(August, 2005, Version 0.0)
2
AMIC Technology, Corp.
A82DL16x4T(U) Series
Pin Configurations
69-Ball TFBGA
Top View
Flash only
A1
A5
A6
A10
NC
NC
NC
NC
B1
B3
B4
B5
B6
B7
B8
NC
A7
LB_S
WP/ACC
WE
A8
A11
Shared
C2
C3
C4
C5
C6
C7
C8
C9
A3
A6
UB_S
RESET
CE2_S
A19
A12
A15
D2
D4
D4
D5
D6
D7
D8
D9
A2
A5
A18
RY/BY
NC
A9
A13
NC
E1
E2
E3
E4
E7
E8
E9
E10
NC
A1
A4
A17
A10
A14
NC
NC
F1
F2
F3
F4
F7
F8
F9
F10
NC
A0
VSS
I/O1
I/O6
NC
A16
NC
G8
G9
G2
G3
G4
G5
G6
G7
CE_F
OE
I/O9
I/O3
I/O4
I/O13
H2
H3
H4
H5
H6
CE1_S
I/O0
I/O10
VCC_F
VCC_S
H7
I/O12
SRAM only
I/O15(A-1) BYTE_F
H8
H9
I/O7
VSS
J3
J4
J5
J6
J7
J8
I/O8
I/O2
I/O11
NC
I/O5
K1
K5
K6
K10
NC
NC
NC
NC
I/O14
Special Handling Instructions for TFBGA Package
Special handling is required for Flash Memory products in TFBGA packages.
Flash memory devices in TFBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or
data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time
PRELIMINARY
(August, 2005, Version 0.0)
3
AMIC Technology, Corp.
A82DL16x4T(U) Series
Product Information Guide
Part Number
A82DL16x4T(U)
Standard Voltage Range:
VCC_F/VCC_S=2.7-3.6V
Speed Options
70
Max Access Time (ns)
CE_F / CE_S Access (ns)
70
70
OE Access (ns)
40
MCP Block Diagram
VCC_F
VSS
A19 to A0
A19 to A0
RY/BY
BYTE_F
WP/ACC
CE_F
16M Bit
Flash Memory
RESET
I/O15 (A-1) to I/O0
I/O15 (A-1) to I/O0
VCC_S
VSS
A17 to A0
WE
OE
LB_S
UB_S
CE1_S
CE2_S
PRELIMINARY
(August, 2005, Version 0.0)
4M Bit
Static RAM
4
I/O15 (A-1) to I/O0
AMIC Technology, Corp.
A82DL16x4T(U) Series
Flash Block Diagram
VCC_F
VSS
Upper Bank
RY/BY
I/O0-I/O15
Y-Decoder
Upper Bank Address
A0-A19
A0-A19
Latches and Control Logic
OE BYTE_F
X-Decoder
A0-A19
STATE
CONTROL
&
COMMAND
REGISTER
RESET
WE
CE_F
BYTE_F
WP/ACC
Status
I/O0-I/O15
Control
Lower Bank Address
Upper Bank
Latches and
Control Logic
Y-Decoder
A0-A19
X-Decoder
OE
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(August, 2005, Version 0.0)
5
I/O0-I/O15
A0-A19
I/O0-I/O15
BYTE_F
AMIC Technology, Corp.
A82DL16x4T(U) Series
Pin Descriptions
Logic Symbol
Pin No.
Description
A0 - A19
Address Inputs
I/O0 - I/O14
I/O15
I/O15 (A-1)
20
Data Inputs/Outputs
A-1
A0-A19
Data Input/Output, Word Mode
16 or 8
LSB Address Input, Byte Mode
I/O0-I/O15(A-1)
CE_F
Chip Enable
CE_S
Chip Enable (SRAM)
CE_S
WE
Write Enable
CE_F
OE
Output Enable
OE
WE
Hardware Write Protect/Acceleration Pin
WP/ACC
RESET
Hardware Reset Pin, Active Low
RESET
BYTE_F
Selects 8-bit or 16-bit Mode
WP /ACC
RY/ BY
VSS
Ground
Power Supply (Flash)
VCC_S
Power Supply (SRAM)
PRELIMINARY
BYTE_F
Ready/ BUSY Output
VCC_F
NC
RY/BY
Pin Not Connected Internally
(August, 2005, Version 0.0)
6
AMIC Technology, Corp.
A82DL16x4T(U) Series
SRAM Block Diagram
VCC_S
A0
DECODER
A16
512 X 8192
VSS
MEMORY ARRAY
A17
I/O8
I/O0
INPUT
COLUMN I/O
DATA
CIRCUIT
INPUT
DATA
CIRCUIT
I/O15
I/O7
CE1_S
CE2_S
LB_S
CONTROL
UB_S
CIRCUIT
OE
WE
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7
AMIC Technology, Corp.
A82DL16x4T(U) Series
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1-1. Device Bus Operations – Flash Byte Mode ( BYTE_F
Operation
(Notes 1, 2)
CE_F
Read from Flash
L
Write to Flash
Standby
Output Disable
Flash Hardware
Reset
Sector Protect
(Notes)
VCC ±
0.3 V
L
X
H
X
X
L
H
X
X
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
L
H
L
Temporary
Sector Unprotect
X
Write to SRAM
CE2_S
L
Sector Unprotect
(Note 5)
Read from
SRAM
CE1_S
L
H
X
X
H
H
L
L
LB_S UB_S RESET
OE
WE
A0A19
L
H
AIN
X
X
H
L
AIN
X
X
X
X
H
H
X
WP /ACC
(Note 4)
I/O7–
I/O0
I/O15–
I/O0
H
L/H
IOUT
IOUT
X
H
(Note 4)
IIN
IIN
X
X
VCC ±
0.3 V
H
High-Z
High-Z
L
X
H
L/H
High-Z
High-Z
X
L
(Note3) (Note3)
X
X
X
X
X
L
L/H
High-Z
High-Z
H
L
SA,
A6 = L,
A1 = H,
A0 = L
X
X
VID
L/H
IIN
X
H
L
SA,
A6 = H,
A1 = H,
A0 = L
X
X
VID
(Note 6)
IIN
X
IIN
High-Z
X
X
AIN
X
X
VID
(Note 6)
IOUT
IOUT
High-Z
IOUT
IOUT
High-Z
IIN
IIN
High-Z
IIN
IIN
High-Z
X
X
= VIH)
L
H
H
L
X
H
AIN
L
H
L
L
H
L
L
H
L
AIN
H
H
L
H
X
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, IIN = Data In, IOUT = Data Out
Notes:
1.Other operations except for those indicated in this column are inhibited.
2.Do not apply CE_F = VIL, CE1_S = VIL and CE2_S = VIH at the same time.
3.Don’t care or open LB_S or UB_S .
4.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector/Sector Block Protection and Unprotection” section.
5. If WP /ACC = VIL, the two outermost boot sectors remain protected. If WP /ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP /ACC = VHH, all sectors will be unprotected.
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(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Table 1-2. Device Bus Operations – Flash Byte Mode ( BYTE_F
Operation
(Notes 1, 2)
CE_F
Read from Flash
L
Write to Flash
Standby
Output Disable
Flash Hardware
Reset
Sector Protect
(Notes)
VCC ±
0.3 V
L
H
X
X
L
H
X
X
L
H
X
X
L
L
H
H
X
X
L
H
X
X
L
H
X
X
L
H
X
X
L
X
L
L
Temporary
Sector Unprotect
X
Write to SRAM
CE2_S
L
Sector Unprotect
(Note 5)
Read from
SRAM
CE1_S
H
H
L
H
H
LB_S UB_S
RESET
WP /ACC
(Note 4)
I/O7–
I/O0
I/O15–
I/O8
H
L/H
IOUT
High-Z
X
H
(Note 3)
IIN
I/O14–8
=Hi-Z;
I/O15=A-1
X
X
VCC_F ±
0.3 V
H
High-Z
High-Z
X
L
X
H
L/H
High-Z
High-Z
X
X
X
L
X
X
X
X
L
L/H
High-Z
High-Z
X
X
VID
L/H
IIN
X
X
X
VID
(Note 6)
IIN
X
X
X
VID
(Note 6)
IIN
High-Z
H
L
IOUT
IOUT
H
L
High-Z
IOUT
L
H
IOUT
High-Z
H
L
IIN
IIN
L
H
High-Z
IIN
L
H
IIN
High-Z
OE
WE
A0-A19
L
H
AIN
X
X
H
L
AIN
X
X
X
X
H
H
H
X
(Note3) (Note3)
SA,
H
L
= VIL)
L
A6 = L,
A1 = H,
A0 = L
H
L
SA,
A6 = H,
A1 = H,
A0 = L
X
X
AIN
L
X
H
AIN
L
AIN
H
H
X
X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In (for Flash Byte Mode, I/O15=A-1), IIN = Data In, IOUT = Data Out
Notes:
1.Other operations except for those indicated in this column are inhibited.
2.Do not apply CE_F = VIL, CE1_S = VIL and CE2_S = VIH at the same time.
3.Don’t care or open LB_S or UB_S .
4.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector/Sector Block Protection and Unprotection” section.
5. If WP /ACC = VIL, the two outermost boot sectors remain protected. If WP /ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP /ACC = VHH, all sectors will be unprotected.
PRELIMINARY
(August, 2005, Version 0.0)
9
AMIC Technology, Corp.
A82DL16x4T(U) Series
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Word/Byte Configuration
The BYTE_F pin determines whether the I/O pins I/O15-I/O0
Accelerated Program Operation
operate in the byte or word configuration. If the BYTE_F pin
is set at logic ”1”, the device is in word configuration, I/O15I/O0 are active and controlled by CE_F and OE .
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
the WP /ACC pin. This function is primarily intended to allow
faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically
enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing VHH from the WP /ACC pin returns the
device to normal operation. Note that the WP /ACC pin must
not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the
WP /ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
If the BYTE_F pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE_F and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is
used as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE_F and OE pins to VIL. CE_F is the power control
and selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH. The
BYTE_F pin determines whether the device outputs array
data in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, lCC1_F in the DC Characteristics table represents
the active current specification for reading array data.
Autoselect Functions
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7-I/O0. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.
Simultaneous Read/Write Operations with Zero
Latency
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE_F to VIL, and
This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to read
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. ICC6_F and ICC7_F in the DC Characteristics
table represent the current specifications for read-while-program and read-while-erase, respectively.
OE to VIH.
Standby Mode
Writing Commands/Command Sequences
For program operations, the BYTE_F pin determines
whether the device accepts program data in bytes or words,
Refer to “Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The “Word / Byte Program Command
Sequence” section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables 3-4 indicate the
address range that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the larger, code
sectors of uniform size. A “bank address” is the address bits
required to uniquely select a bank. Similarly, a “sector
address” is the address bits required to uniquely select a
sector.
ICC2_F in the DC Characteristics table represents the active
current specification for the write mode. The "AC
PRELIMINARY
(August, 2005, Version 0.0)
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE
input.
The device enters the CMOS standby mode when the
CE_F & RESET pins are both held at VCC_F ± 0.3V. (Note
that this is a more restricted voltage range than VIH.) If
CE_F and RESET are held at VIH, but not within VCC_F ±
0.3V, the device will be in the standby mode, but the standby
current will be greater. The device requires the standard
access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3_F in the DC Characteristics tables represent the standby
current specification.
10
AMIC Technology, Corp.
A82DL16x4T(U) Series
Automatic Sleep Mode
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
sleep mode is independent of the CE_F , WE and OE
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the
system. ICC4_F in the DC Characteristics table represents the
automatic sleep mode current specification.
the RY/ BY pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
RY/ BY to determine whether the reset operation is
complete. If RESET is asserted when a program or erase
operation is not executing (RY/ BY pin is “1”), the reset
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws
CMOS standby current (ICC4_F ). If RESET is held at VIL but
not within VSS ± 0.3V, the standby current will be greater.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
Table 2. A82DL16x4T(U) Device Bank Divisions
Device
Part Number
Bank 1
Bank 2
Megabits
Sector Sizes
Megabits
Sector Sizes
A82DL1624
2 Mbit
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
14 Mbit
Twenty-eight
64 Kbyte/32 Kword
A82DL1634
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
12 Mbit
Twenty-four
64 Kbyte/32 Kword
A82DL1644
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
8 Mbit
Sixteen
64 Kbyte/32 Kword
PRELIMINARY
(August, 2005, Version 0.0)
11
AMIC Technology, Corp.
A82DL16x4T(U) Series
A82DL1624T
A82DL1634T
Bank 2
Bank 1
Bank 1
Bank 1
Bank 2
Bank 2
A82DL1644T
Table 3. Sector Addresses for Top Boot Sector Devices
Sector
Sector Address
A19–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
00000xxx
00001xxx
00010xxx
00011xxx
00100xxx
00101xxx
00110xxx
00111xxx
01000xxx
01001xxx
01010xxx
01011xxx
01100xxx
01101xxx
01110xxx
01111xxx
10000xxx
10001xxx
10010xxx
10011xxx
10100xxx
10101xxx
10110xxx
10111xxx
11000xxx
11001xxx
11010xxx
11011xxx
11100xxx
11101xxx
11110xxx
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1F1FFFh
1F2000h-1F3FFFh
1F4000h-1F5FFFh
1F6000h-1F7FFFh
1F8000h-1F9FFFh
1FA000h-1FBFFFh
1FC000h-1FDFFFh
1FE000h-1FFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7FFFFh
80000h–87FFFh
88000h–8FFFFh
90000h–97FFFh
98000h–9FFFFh
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
C8000h–CFFFFh
D0000h–D7FFFh
D8000h–DFFFFh
E0000h–E7FFFh
E8000h–EFFFFh
F0000h–F7FFFh
F8000h–F8FFFh
F9000h–F9FFFh
FA000h–FAFFFh
FB000h–FBFFFh
FC000h–FCFFFh
FD000h–FDFFFh
FE000h–FEFFFh
FF000h–FFFFFh
Note:
The address range is A19: A-1in byte mode ( BYTE_F =VIL) or A19:A0 in word mode ( BYTE_F =VIH). The bank address bits are
A19-A17 for A82DL1624T, A19 and A18 for A82DL1634T, and A19 for A82DL1644T.
PRELIMINARY
(August, 2005, Version 0.0)
12
AMIC Technology, Corp.
A82DL16x4T(U) Series
A82DL1624U
Bank 1
A82DL1634U
Bank 2
Bank 2
Bank 2
Bank 1
Bank 1
A82DL1644U
Table 4. Sector Addresses for Bottom Boot Sector Devices
Sector
Sector Address
A19–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001XXX
00010XXX
00011XXX
00100XXX
00101XXX
00110XXX
00111XXX
01000XXX
01001XXX
01010XXX
01011XXX
01100XXX
01101XXX
01110XXX
01111XXX
10000XXX
10001XXX
10010XXX
10011XXX
10100XXX
10101XXX
10110XXX
10111XXX
11000XXX
11001XXX
11010XXX
11011XXX
11100XXX
11101XXX
11110XXX
11111XXX
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
00000h-00FFFh
01000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-04FFFh
05000h-05FFFh
06000h-06FFFh
07000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
80000h-87FFFh
88000h-8FFFFh
90000h-97FFFh
98000h-9FFFFh
A0000h-A7FFFh
A8000h-AFFFFh
B0000h-B7FFFh
B8000h-BFFFFh
C0000h-C7FFFh
C8000h-CFFFFh
D0000h-D7FFFh
D8000h-DFFFFh
E0000h-E7FFFh
E8000h-EFFFFh
F0000h-F7FFFh
F8000h-FFFFFh
Note:
The address range is A19: A-1in byte mode ( BYTE_F =VIL) or A19:A0 in word mode ( BYTE_F =VIH). The bank address bits are
A19-A17 for A82DL1624U, A19 and A18 for A82DL1634U, and A19 for A82DL1644U.
PRELIMINARY
(August, 2005, Version 0.0)
13
AMIC Technology, Corp.
A82DL16x4T(U) Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (8.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Table 5. In
addition, when verifying sector protection, the sector address
must appear on the appropriate highest order address bits.
(see Table 3-4). Table 5 shows the remaining address bits
that are don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command
register, as shown in Table 12. This method does not require
VID. Refer to the Autoselect Command Sequence section for
more information.
Table 5. A82DL16x4T(U) Autoselect Codes (High Voltage Method)
Description
CE_F
OE
WE
A19
to
A12
A11
to
A10
A9
A8
to
A7
A6
I/O8 to I/O15
A5
to
A2
A1
A0
BYTE_F
BYTE_F
= VIH
= VIL
I/O7
to
I/O0
Manufacturer ID: AMIC
L
L
H
BA
X
VID
X
L
X
L
L
X
X
37h
Device ID: A82DL1624
L
L
H
BA
X
VID
X
L
X
L
H
22h
X
2Dh (T), 2Eh (U)
Device ID: A82DL1634
L
L
H
BA
X
VID
X
L
X
L
H
22h
X
28h (T), 2Bh (U)
Device ID: A82DL1644
L
L
H
BA
X
VID
X
L
X
L
H
22h
X
33h (T), 35h (B)
Continuation ID
L
L
H
X
X
VID
X
L
X
H
H
X
X
7Fh
Read Sector Protection
Verification
L
L
H
SA
X
VID
X
L
X
H
L
X
X
01h (protected),
00h (unprotected)
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care, BA=Bank Address
Note: The autoselect codes may also be accessed in-system via command sequences.
PRELIMINARY
(August, 2005, Version 0.0)
14
AMIC Technology, Corp.
A82DL16x4T(U) Series
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors. Sector
protection and unprotection can be implemented via two
methods.
The primary method requires VID on the RESET pin only,
and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and
Figure 23 shows the timing diagram. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle.
The sector unprotect algorithm unprotects all sectors in
parallel. All previously protected sectors must be individually
re-protected. To change data in protected sectors efficiently,
the temporary sector unprotect function is available. See
“Temporary Sector/Sector Block Unprotect”.
The alternate method for protection and unprotection is by
software temporary sector /sector block unprotect command.
See Figure 2 for Command Flow.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See the Autoselect Mode section for details.
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
Table 6. Top Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector /
Sector Block
SA0
A19–A12
Sector / Sector Block Size
64 Kbytes
SA4-SA7
00000XXX
00001XXX,
00010XXX,
00011XXX
001XXXXX
256 (4x64) Kbytes
SA8-SA11
010XXXXX
256 (4x64) Kbytes
SA12-SA15
011XXXXX
256 (4x64) Kbytes
SA16-SA19
100XXXXX
256 (4x64) Kbytes
SA20-SA23
101XXXXX
256 (4x64) Kbytes
SA24-SA27
110XXXXX
256 (4x64) Kbytes
SA28-SA30
11100XXX,
11101XXX,
11110XXX
192 (3x64) Kbytes
SA31
11111000
8 Kbytes
SA32
11111001
8 Kbytes
SA33
11111010
8 Kbytes
SA34
11111011
8 Kbytes
SA35
11111100
8 Kbytes
SA36
11111101
8 Kbytes
SA37
11111110
8 Kbytes
SA38
11111111
8 Kbytes
SA1-SA3
192 (3x64) Kbytes
Write Protect ( WP /ACC)
A19–A12
Sector / Sector Block Size
SA38
11111XXX
64 Kbytes
SA37-SA35
11110XXX,
11101XXX,
11100XXX
192 (3x64) Kbytes
SA34-SA31
110XXXXX
256 (4x64) Kbytes
SA30-SA27
101XXXXX
256 (4x64) Kbytes
SA26-SA23
100XXXXX
256 (4x64) Kbytes
SA22-SA19
011XXXXX
256 (4x64) Kbytes
The Write Protect function provides a hardware method of
protecting certain boot sectors without using VID. This
function is one of two provided by the WP /ACC pin.
If the system asserts VIL on the WP /ACC pin, the device
disables program and erase functions in the two “outermost”
8 Kbyte boot sectors independently of whether those sectors
were protected or unprotected using the method described in
“Sector/Sector Block Protection and Unprotection”. The two
outermost 8 Kbyte boot sectors are the two sectors
containing the lowest addresses in a bottom-boot-configured
device, or the two sectors containing the highest addresses
in a top-boot-configured device.
If the system asserts VIH on the WP /ACC pin, the device
reverts to whether the two outermost 8 Kbyte boot sectors
were last set to be protected or unprotected. That is, sector
protection or unprotection for these two sectors depends on
whether they were last protected or unprotected using the
method described in “Sector/Sector Block Protection and
Unprotection”.
Note that the WP /ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may result.
SA18-SA15
010XXXXX
256 (4x64) Kbytes
Temporary Sector/Sector Block Unprotect
SA14-SA11
001XXXXX
256 (4x64) Kbytes
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
This feature allows temporary unprotection of previously
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID
(8.5V-12.5V). During this mode, formerly protected sectors
can be programmed or erased by selecting the sector
addresses. Once VID is removed from the RESET pin, all the
previously protected sectors are protected again. Figure 1
shows the algorithm, and Figure 22 shows the timing
diagrams, for this feature.
Table 7. Bottom Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector /
Sector Block
SA7
00001XXX,
00010XXX,
00011XXX
00000111
SA6
00000110
8 Kbytes
SA5
00000101
8 Kbytes
SA4
00000100
8 Kbytes
SA3
00000011
8 Kbytes
SA2
00000010
8 Kbytes
SA1
00000001
8 Kbytes
SA0
00000000
8 Kbytes
SA10-SA8
PRELIMINARY
192 (3x64) Kbytes
8 Kbytes
(August, 2005, Version 0.0)
15
AMIC Technology, Corp.
A82DL16x4T(U) Series
START
START
RESET = VID
(Note 1)
555/AA + 2AA/55 + 555/77
(Note 1)
Perform Erase or
Program Operations
Perform Erase or
Program Operations
RESET = VIH
XXX/F0
(Reset Command)
Temporary Sector
Unprotect
Completed (Note 2)
Soft-ware Temporary
Sector Unprotect
Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode
PRELIMINARY
(August, 2005, Version 0.0)
16
Figure 1-2. Temporary Sector Unprotect Operation by Software Mode
AMIC Technology, Corp.
A82DL16x4T(U) Series
START
START
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
PLSCNT=1
RESET=VID
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
RESET=VID
Wait 1 us
No
First Write
Cycle=60h?
No
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
All sectors
protected?
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Increment
PLSCNT
First Write
Cycle=60h?
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?**
No
Set up
next sector
address
Yes
Yes
Protect another
sector?
Device failed
PLSCNT=
1000?
Yes
No
Yes
No
Remove VID
from RESET
Device failed
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
Data=00h?**
Yes
Last sector
verified?
No
Yes
Remove VID
from RESET
Sector Unprotect
Algorithm
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Read access time is 200ns-300ns
Write reset
Command
Sector Unprotect
complete
Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms
PRELIMINARY
(August, 2005, Version 0.0)
17
AMIC Technology, Corp.
A82DL16x4T(U) Series
START
START
PLSCNT=1
555/AA + 2AA/55 +
555/77
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
555/AA + 2AA/55 +
555/77
Wait 1 us
No
First Write
Cycle=60h?
Yes
No
Temporary Sector
Unprotect Mode
Yes
Set up sector
address
All sectors
protected?
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Increment
PLSCNT
First Write
Cycle=60h?
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?**
No
Set up
next sector
address
Yes
Yes
Protect another
sector?
Device failed
PLSCNT=
1000?
Yes
Yes
No
Write reset
command
Sector Protect
Algorithm
No
Device failed
Sector Protect
complete
Data=00h?**
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Write reset
Command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
** Access time is 200ns-300ns
Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms
PRELIMINARY
(August, 2005, Version 0.0)
18
AMIC Technology, Corp.
A82DL16x4T(U) Series
Hardware Data Protection
Power-Up Write Inhibit
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to Table 12 for command definitions).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC_F power-up and power-down transitions, or from
system noise.
If WE = CE_F = VIL and OE = VIH during power up, the
Low VCC Write Inhibit
When VCC_F is less than VLKO, the device does not accept
any write cycles. This protects data during VCC_F power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until
VCC_F is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional
writes when VCC_F is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE , CE_F or
WE do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL,
CE_F = VIH or WE = VIH. To initiate a write cycle, CE_F
device does not accept commands on the rising edge of WE .
The internal state machine is automatically reset to reading
array data on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified software algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the device is
ready to read array data. The system can read CFI
information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Tables 8-11. The system must write the
reset command to return the device to the autoselect mode.
and WE must be a logical zero while OE is a logical one.
Table 8. CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
PRELIMINARY (August, 2005, Version 0.0)
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19
AMIC Technology, Corp.
A82DL16x4T(U) Series
Table 9. System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
1Bh
36h
0027h
1Ch
38h
0036h
Data
Description
VCC Min. (write/erase)
I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt
VCC Max. (write/erase)
I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt
1Dh
3Ah
0000h
Vpp Min. voltage (00h = no Vpp pin present)
1Eh
3Ch
0000h
Vpp Max. voltage (00h = no Vpp pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10 Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
27h
4Eh
0015h
28h
50h
0002h
29h
52h
0000h
2Ah
54h
0000h
Data
Description
N
Device Size = 2 byte
Flash Device Interface description
N
2Bh
56h
0000h
Max. number of byte in multi-byte write = 2
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
5Ah
0007h
2Eh
5Ch
0000h
2Fh
5Eh
0020h
30h
60h
0000h
31h
62h
001Eh
32h
64h
0000h
33h
66h
0000h
34h
68h
0001h
35h
6Ah
0000h
36h
6Ch
0000h
37h
6Eh
0000h
38h
40h
0000h
39h
72h
0000h
3Ah
74h
0000h
3BH
76h
0000h
3Ch
78h
0000h
PRELIMINARY
(August, 2005, Version 0.0)
Erase Block Region 1 Information
(refer to the CFI specification)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
20
AMIC Technology, Corp.
A82DL16x4T(U) Series
Table 11. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
44h
88h
0032h
Minor version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock
Data
Description
Query-unique ASCII string “PRI”
0 = Required, 1 = Not Required
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
48h
90h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
04 = A29L800 mode
4Ah
94h
4Bh
96h
00XXh
(See Note)
0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors (excluding Bank 1)
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt,
4Dh
9Ah
0085h
4Eh
9Ch
0095h
ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV
4Fh
9Eh
000Xh
Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot
Device
D3-D0: 100 mV
Note:
The number of sectors in Bank 2 is device dependent.
A82DL1624 = 1Ch
A82DL1634 = 18h
A82DL1644 = 10h
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
(or erase-suspend-read mode if that bank was in Erase
Suspend).
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. Table
12 defines the valid register command sequences. Writing
incorrect address and data values or writing them in the
improper sequence may place the device in an unknown
state. A reset command is then required to return the device
to reading array data.
All addresses are latched on the falling edge of WE or
CE_F , whichever happens later. All data is latched on the
Autoselect Command Sequence
The autoselect command sequence allows the host system
to access the manufacturer and device codes, and determine
whether or not a sector is protected. Table 12 shows the
address and data requirements. This method is an
alternative to that shown in Table 5, which is intended for
PROM programmers and requires VID on address pin A9.
The autoselect command sequence may be written to an
address wit h in a bank that is either in t he read or erasesuspend-read mode. The autoselect command may not be
written while the device is actively programming or erasing in
the other bank.
The autoselect command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle that
contains the bank address and the autoselect command. T he
bank then enter s the autoselect mode. The system may read
at any address within the same bank any number of times
without initiating another autoselect command sequence:
A read cycle at address (BA)XX00h (where BA is the bank
address) returns the manufacturer code.
A read cycle at address (BA)XX01h in word mode (or
(BA)XX02h in byte mode) returns the device code.
A read cycle to an address containing a sector address
(SA) within the same bank, and the address 02h on A7-A0
in word mode (or the address 04h on A6-A-1 in byte mode)
returns 01h if the sector is protected, or 00h if it is
unprotected. (Refer to Tables 3-4 for valid sector
addresses).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the bank
was previously in Erase Suspend).
rising edge of WE or CE_F , whichever happens first. Refer
to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
After the device accepts an Erase Suspend command, the
corresponding bank enters the erase-suspend-read mode,
after which the system can read data from any non-erasesuspended sector within the same bank. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return a bank
to the read (or erase-suspend-read) mode if I/O5 goes high
during an active program or erase operation, or if the bank is
in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device
Bus Operations section for more information. The Read-Only
Operations table provides the read parameters, and Figure
11 shows the timing diagram.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE_F pin. Programming is
a four-bus-cycle operation. The program command sequence
is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 12 shows the address and
data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, that
bank then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using I/O7, I/O6, or RY/ BY . Refer
to the Write Operation Status section for information on these
status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the program operation. The program
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from “0” back to a
“1.” Attempting to do so may cause that bank to set I/O5 = 1,
or cause the I/O7 and I/O6 status bits to indicate the operation
was successful. However, a succeeding read will show that
the data is still “0.” Only erase operations can convert a “0” to
a “1.”
Reset Command
Writing the reset command resets the banks to the read or
erase-suspend-read mode. Address bits are don’t cares for
this command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the bank to which the system was writing
to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the bank to which the
system was writing to reading array data. If the program
command sequence is written to a bank that is in the Erase
Suspend mode, writing the reset command returns that bank
to the erase-suspend-read mode. Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data. If a bank entered the autoselect
mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If I/O5 goes high during a program or erase operation, writing
the reset command returns the banks to reading array data
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to a bank faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The device
then returns to reading array data.
The device offers accelerated program operations through
the WP /ACC pin. When the system asserts VHH on the
WP /ACC pin, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
uses the higher voltage on the WP /ACC pin to accelerate
the operation. Note that the WP /ACC pin must not be at VHH
any operation other than accelerated programming, or device
damage may result. In addition, the WP /ACC pin must not
be left floating or unconnected; inconsistent behavior of the
device may result.
Figure 3 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and Figure 15 for
timing diagrams.
START
Write Program
Command
Sequence
Data Poll
from System
Embedded
Program
algorithm in
progress
Verify Data ?
No
Yes
Increment Address
No
Last Address ?
Yes
Programming
Completed
Note : See Table 14 for program command sequnce.
Figure 3. Program Operation
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase
operation by reading I/O7, I/O6, I/O2, or RY/ BY in the erasing
bank.
Refer to the Write Operation Status section for information on
these status bits.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide
any controls or timings during these operations. Table 12
shows the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that bank
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, I/O2, or RY/ BY . Refer to the
Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operations tables in the AC
Characteristics section for parameters, and Figure 17 section
for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to
interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50 µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the
sector erase operation, the device requires a maximum of 20
µs to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase timeout, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the bank
enters the erase-suspend-read mode. The system can read
data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected
for erasure.) Reading at any address within erase-suspended
sectors produces status information on I/O7–I/O0. The system
can use I/O7, or I/O6 and I/O2 together, to determine if a
sector is actively erasing or is erase-suspended. Refer to the
Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete,
the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using the I/O7 or I/O6 status bits, just as in the standard Byte
Program operation. Refer to the Write Operation Status
section for more information.
In the erase-suspend-read mode, the system can also issue
the autoselect command sequence. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for
details.
To resume the sector erase operation, the system must write
the Erase Resume command. The bank address of the
erase-suspended bank is ignored when writing this command.
Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip has
resumed erasing.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
12 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase timeout of 50 µs occurs. During the time-out period, additional
sector addresses and sector erase commands within the
bank may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these
additional cycles must be less than 50µs, otherwise erasure
may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted.
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. Any command other than Sector Erase
or Erase Suspend during the time-out period resets that bank
to reading array data. The system must rewrite the command
sequence and any additional addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out (See the section on I/O3: Sector Erase
Timer.). The time-out begins from the rising edge of the final
WE pulse in the command sequence.
PRELIMINARY
(August, 2005, Version 0.0)
24
AMIC Technology, Corp.
A82DL16x4T(U) Series
START
Write Erase
Command Sequence
(Notes 1,2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See Table 14 for erase command sequence.
2. See the section on I/O3 for information on the sector
erase timer.
Figure 4. Erase Operation
PRELIMINARY
(August, 2005, Version 0.0)
25
AMIC Technology, Corp.
A82DL16x4T(U) Series
Command Definitions
Table 12. A82DL16x4T(U) Command Definitions
Cycle
Command
Sequence
(Note 1)
First
Addr Data
1
RA
RD
Reset (Note 7)
1
XXX
F0
Autoselect (Note 8)
Read (Note 6)
Manufacturer ID
Device ID
Word
Byte
Word
Byte
Word
Byte
Continuation ID
Sector Protect Verify
(Note 9)
Command Temporary
Sector Unprotect(Note 15)
Program
Word
Byte
Word
Byte
Word
Byte
Word
Unlock Bypass
Byte
4
4
4
4
3
4
3
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
AA
AA
AA
AA
AA
AA
AA
Second
Addr Data
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
55
55
55
55
55
55
55
Unlock Bypass Program (Note 10)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 11)
2
XXX
90
XXX
00
Word
Chip Erase
Byte
Word
Byte
Sector Erase
6
6
555
AAA
555
AAA
AA
AA
Erase Suspend (Note 12)
1
XXX
B0
Erase Resume (Note 13)
1
XXX
30
1
55
AA
98
CFI Query (Note 14)
Word
Byte
2AA
555
2AA
55
55
555
Bus Cycles (Notes 2–5)
Third
Fourth
Addr
Data
Addr
Data
(BA)555
(BA)AAA
(BA)555
(BA)AAA
555
AAA
(BA)555
(BA)AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
90
90
90
90
(BA)X00
37
(BA)X01
(see
Fifth
Addr
Data
Sixth
Addr Data
(BA)X02 Table5)
X03
X06
(SA)
(SA)X04
7F
00/01
77
A0
PA
PD
20
80
80
555
AA A
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE_F pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE_F pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits I/O15-I/O8 are don’t care in command sequences. Except for RD and PD.
5. Unless otherwise noted, address bits A19-A11 are don’t cares.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if I/O5 goes high (while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain
the manufacture ID, or device ID information. Data bits I/O15-I/O8 are don’t care. See the Autoselect Command Sequence
section for more information.
9. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.
11. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase operation, and require the bank address.
13. The Erase Resume command is valid only during the Erase.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
15. Once reset command is applied, software temporary unprotect is exit to return read array data. But under erase suspend
condition, this command is still effective even a reset command has been applied. The reset command which can deactivate
the software temporary unprotect command is useful only after the erase command is complete.
PRELIMINARY
(August, 2005, Version 0.0)
26
AMIC Technology, Corp.
A82DL16x4T(U) Series
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7.
Table 13 and the following subsections describe the function
of these bits. I/O7 and I/O6 each offer a method for
determining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/ BY , to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
START
Read I/O7-I/O0
Address = VA
I/O7: Data Polling
Yes
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
I/O7 = Data ?
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 1µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7. The system must
provide an address within any of the sectors selected for
erasure to read valid status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100µs, then the bank returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads I/O7 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, I/O7 may change asynchronously with I/O0–
I/O6 while Output Enable ( OE ) is asserted low. That is, the
device may change from providing status information to valid
data on I/O7. Depending on when the system samples the
I/O7 output, it may read the status or valid data. Even if the
device has completed the program or erase operation and
I/O7 has valid data, the data outputs on I/O0-I/O6 may be still
invalid. Valid data on I/O0-I/O7 will appear on successive read
cycles.
Table 13 shows the outputs for Data Polling on I/O7. Figure
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
Yes
I/O7 = Data ?
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 5. Data Polling Algorithm
5 shows the Data Polling algorithm. Figure 19 in the AC
Characteristics section shows the Data Polling timing
diagram.
PRELIMINARY
(August, 2005, Version 0.0)
27
AMIC Technology, Corp.
A82DL16x4T(U) Series
RY/ BY : Ready/ Busy
The RY/ BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or
complete. The RY/ BY status is valid after the rising edge of
the final WE pulse in the command sequence. Since RY/ BY
is an open-drain output, several RY/ BY pins can be tied
together in parallel with a pull-up resistor to VCC_F.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 13 shows the outputs for RY/ BY .
START
Read I/O7-I/O0
Read I/O7-I/O0
(Note 1)
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final WE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
The system may use either OE or CE_F to control the read
cycles. When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 : Data
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 1µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
Table 13 shows the outputs for Toggle Bit I on I/O6. Figure 6
shows the toggle bit algorithm. Figure 20 in the “AC
Characteristics” section shows the toggle bit timing diagrams.
Figure 23 shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on I/O2: Toggle Bit II.
PRELIMINARY (August, 2005, Version 0.0)
28
Toggle Bit
= Toggle ?
No
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Twice
Toggle Bit
= Toggle ?
(Notes 1,2)
No
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Note:
The system should recheck the toggle bit even if I/O5=”1"
because the toggle bit may stop toggling as I/O5 changes to
“1”. See the subsections on I/O6 and I/O2 for more information.
Figure 6. Toggle Bit Algorithm
AMIC Technology, Corp.
A82DL16x4T(U) Series
I/O2: Toggle Bit II
I/O5: Exceeded Timing Limits
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE pulse in the command sequence.
I/O2 toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may
use either OE or CE_F to control the read cycles.) But I/O2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Figure 20 shows the
toggle bit timing diagram. Figure 21 shows the differences
between I/O2 and I/O6 in graphical form.
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The device may output a “1” on I/O5 if the system tries to
program a “1” to a location that was previously programmed
to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation, and
when the timing limit has been exceeded, I/O5 produces a
“1.” .
Under both these conditions, the system must write the reset
command to return to reading array data (or to the erasesuspend-read mode if a bank was previously in the erasesuspend-program mode).
Reading Toggle Bits I/O6, I/O2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7-I/O0 at least twice in a row to determine whether a toggle
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7-I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
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(August, 2005, Version 0.0)
29
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50µs. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (Except Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted.
Table 13 shows the status of I/O3 relative to the other status
bits.
AMIC Technology, Corp.
A82DL16x4T(U) Series
Table 13. Write Operation Status
Status
I/O7
I/O6
(Note 2)
Standard Embedded Program Algorithm
Mode
Embedded Erase Algorithm
Erase
Erase
Suspend Erase-Suspend- Suspended Sector
Mode
Read
Non-Erase
Suspend Sector
Erase-Suspend-Program
I/O5
I/O3
(Note 1)
I/O2
RY/ BY
(Note 2)
I/O7
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
I/O7
Toggle
0
N/A
N/A
0
Notes:
1. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on I/O5 for more information.
2. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
PRELIMINARY
(August, 2005, Version 0.0)
30
AMIC Technology, Corp.
A82DL16x4T(U) Series
ABSOLUTE MAXIMUM RATINGS*
*Comments
Storage Temperature Plastic Packages. . . -55°C to +125°C
Ambient Temperature, ……………………...-65°C to + 125°C
Voltage with Respect to Ground (Note 1)
VCC_F/VCC_S ………. . . . . . . … . ... . ……. . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . . . -0.5V to +12.5V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
WP /ACC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V
All other pins (Note 1) . . . . . . -0.5V to VCC_F/VCC_S + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . …. . 200mA
OPERATING RANGES
Notes:
Industrial (U) Devices
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC_F/VCC_F +0.5V. See
Figure 7. During voltage transitions, input or I/O pins may
overshoot to VCC_F/VCC_S +2.0V for periods up to
20ns. See Figure 8.
2. Minimum DC input voltage on A9, OE , RESET and
Ambient Temperature (TA) . . . . . . . . . . . . . . -40°C to +85°C
VCC Supply Voltages
VCC_F/VCC_S for all devices . .. . . . . . . …...+2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
WP /ACC is -0.5V. During voltage transitions, A9, OE ,
WP /ACC and RESET may overshoot VSS to -2.0V for
periods of up to 20ns. See Figure 7. Maximum DC input
voltage on A9 is +12.5V which may overshoot to 14.0V
for periods up to 20ns. Maximum DC input voltage on
WP /ACC is +9.5V which may overshoot to +12.0V for
period up to 20ns.
3. No more than one output is shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
Figure 7. Maximum Negative Overshoot Waveform
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Figure 8. Maximum Positive Overshoot Waveform
20ns
VCC_F//VCC_S
+2.0V
VCC_F/VCC_S
+0.5V
2.0V
20ns
PRELIMINARY
(August, 2005, Version 0.0)
20ns
31
AMIC Technology, Corp.
A82DL16x4T(U) Series
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Description
Min.
ILI
Input Load Current
VIN = VSS to VCC_F. VCC_F= VCC_F Max
ILIT
A9 Input Load Current
VCC = VCC Max, A9 =12.5V
ILO
Output Leakage Current
VOUT = VSS to VCC_F.
VCC = VCC_F Max
ICC1_F
VCC_F Active Read Current
(Notes 1, 2)
Typ.
Max.
Unit
±1.0
35
µA
±1.0
µA
CE_F = VIL, OE = VIH
5 MHz
10
16
Byte Mode
1 MHz
2
4
5 MHz
10
16
1 MHz
2
4
CE_F = VIL, OE = VIH
Word Mode
µA
mA
CE_F = VIL, OE =VIH
20
30
mA
ICC3_F
VCC_F Active Write Current
(Notes 2, 3)
VCC_F Standby Current (Note 2)
CE_F = VIH, RESET = VCC_F ± 0.3V
0.2
5
µA
ICC4_F
VCC_F Reset Current (Note 2)
RESET = VSS ± 0.3V
0.2
5
µA
ICC5_F
Automatic Sleep Mode
(Note 2, 4)
VIH = VCC_F ± 0.3V;
0.2
5
µA
Byte
21
45
Word
21
45
Byte
21
45
Word
21
45
17
35
ACC pin
5
10
VCC_F pin
15
30
ICC2_F
VIL = VSS ± 0.3V
ICC6_F
ICC7_F
ICC8_F
IACC
VIL
VIH
VHH
VID
VOL
VCC_F Active Read-While-Program
Current (Notes 1, 2)
CE_F = VIL, OE = VIH
VCC_F Active Read-While-Erase Current
(Notes 1, 2)
CE_F = VIL, OE = VIH
VCC_F Active
Program-While-Erase-Suspended
Current (Notes 2, 5)
CE_F = VIL, OE = VIH
ACC Accelerated Program Current, Word
or Byte
CE_F = VIL, OE = VIH
mA
mA
mA
Input Low Level
-0.5
0.8
V
Input High Level
0.7 x
VCC_F
VCC_F +
0.3
V
VCC_F = 3.0 V ± 10%
8.5
9.5
V
VCC_F = 3.0 V ± 10%
8.5
12.5
V
0.45
V
Voltage for WP /ACC Sector
Protect/Unprotect and Program
Acceleration
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
VOH1
IOL = 4.0mA, VCC_F = VCC_F Min
IOH = -2.0 mA, VCC_F = VCC_F Min
Output High Voltage
IOH = -100 µA, VCC_F = VCC Min
VOH2
VLKO
mA
Low VCC_F Lock-Out Voltage
(Note 5)
0.85x
VCC_F
V
VCC_F 0.4
V
2.3
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE at VIH.
2. Maximum ICC specifications are tested with VCC_F = VCC_F max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC_F + 30ns. Typical sleep mode
current is 200nA.
5. Not 100% tested.
PRELIMINARY
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32
AMIC Technology, Corp.
A82DL16x4T(U) Series
TEST CONDITIONS
Table 14. Test Specifications
Test Condition
-70
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
35
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
0.0 - 3.0
V
Input timing measurement reference levels
1.5
V
Output timing measurement reference levels
1.5
V
Figure 9. Test Setup
3.3 V
2.7 KΩ
Device
Under
Test
CL
6.2 KΩ
Diodes = IN3064 or Equivalent
Figure 10. Input Waveforms and Measurement Levels
3.0V
Input
1.5V
Measurement Level
1.5V
Output
0.0V
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33
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Read Only Operations
Description
Parameter
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
Test Setup
Speed
Unit
-70
Min.
70
ns
Max.
70
ns
Max.
70
ns
Output Enable to Output Delay
Max.
40
ns
tDF
Chip Enable to Output High Z
(Notes 1,3)
Max.
16
ns
tGHQZ
tDF
Output Enable to Output High Z
(Notes 1,3)
Max.
16
ns
tAXQX
tOH
Output Hold Time from Addresses, CE or OE ,
Whichever Occurs First
Min.
0
ns
Min.
0
ns
Min.
10
ns
CE_F = VIL
tOEH
Output Enable Hold Time
(Note 1)
OE = VIL
OE = VIL
Read
Toggle and
Data Polling
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 14 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of (VCC_F)/2. The time from OE high
to the data bus driven to (VCC_F)/2 is taken as tDF.
Figure 11. Read Operation Timings
tRC
Addresses
Addresses Stable
tACC
CE_F
tRH
tRH
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
Output
Output Valid
High-Z
RESET
RY/BY
0V
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(August, 2005, Version 0.0)
34
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Hardware Reset ( RESET )
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET Pin Low (Not During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET Pulse Width
Min
500
ns
tRH
RESET High Time Before Read (See Note)
Min
50
ns
tRB
RY/ BY Recovery Time
Min
0
ns
tRPD
RESET Low to Standby Mode
Min
20
µs
Note: Not 100% tested.
Figure 12. RESET Timings
RY/BY
0V
CE_F, OE
tRH
RESET
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
~
~ ~
~
tReady
RY/BY
tRB
CE_F, OE
~
~
RESET
tRP
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(August, 2005, Version 0.0)
35
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Word/Byte Configuration ( BYTE_F )
Parameter
JEDEC
Speed Option
Description
Std
Unit
-70
tELFL/tELFH
CE_F to BYTE_F Switching Low or High
Max
5
ns
tFLQZ
BYTE_F Switching Low to Output High-Z
Max
25
ns
tHQV
BYTE_F Switching High to Output Active
Min
70
ns
Figure 13. BYTE_F Timings for Read Operations
CE_F
OE
BYTE_F
tELFL
BYTE_F
Switching
from word to
byte mode
Data Output
(I/O0-I/O14)
I/O0-I/O14
Data Output
(I/O0-I/O7)
I/O15
Output
I/O15 (A-1)
Address Input
tFLQZ
tELFH
BYTE_F
BYTE _F
Switching
from byte to
word mode
I/O0-I/O14
Data Output
(I/O0-I/O7)
I/O15 (A-1)
Address Input
Data Output
(I/O0-I/O14)
I/O15
Output
tFHQV
Figure 14. BYTE_F Timings for Write Operations
CE_F
The falling edge of the last WE signal
WE
BYTE_F
tSET
(tAS)
tHOLD (tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
PRELIMINARY
(August, 2005, Version 0.0)
36
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Description
Speed
Unit
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
70
ns
tAVWL
tAS
Address Setup Time
Min.
0
ns
tASO
Address Setup Time to OE low during toggle bit polling
15
ns
tAH
Address Hold Time
45
ns
tAHT
Address Hold Time From CE_F or OE high during
toggle bit polling
0
ns
tDVWH
tDS
Data Setup Time
Min.
35
ns
tWHDX
tDH
Data Hold Time
Min.
0
ns
tOEPH
Output Enable High during toggle bit polling
Min.
20
ns
tGHWL
Read Recover Time Before Write
Min.
tWLAX
tGHWL
-70
Min.
( OE high to WE low)
0
ns
tELWL
tCS
CE_F Setup Time
Min.
0
ns
tWHEH
tCH
CE_F Hold Time
Min.
0
ns
tWLWH
tWP
Write Pulse Width
Min.
30
ns
tWHDL
tWPH
Write Pulse Width High
Min.
30
ns
tSR/W
Latency Between Read and Write Operations
Min.
0
Byte
Typ.
5
Word
Typ.
7
Typ.
4
sec
Sector Erase Operation (Note 2)
Typ.
0.7
sec
tvcs
VCC_F Set Up Time (Note 1)
Min.
50
µs
tRB
Recovery Time from RY/ BY
Min
0
ns
Program/Erase Valid to RY/ BY Delay
Min
90
ns
tWHWH1
tWHWH1
tWHWH1
tWHWH1
Byte Programming Operation
(Note 2)
µs
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH2
tWHWH2
tBUSY
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
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37
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Figure 15. Program Operation Timings
Read Status Data (last two cycles)
Program Command Sequence (last two cycles)
PA
555h
PA
tAH
PA
~
~ ~
~
Addresses
tAS
~
~
tWC
CE_F
~
~
tCH
OE
tWP
~
~
tWHWH1
WE
tCS
tWPH
tDH
A0h
Data
PD
~
~
tDS
tBUSY
Status
DOUT
tRB
~
~ ~
~
RY/BY
tVCS
VCC_F
Note :
1. PA = program address, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
Figure 16. Accelerated Program Timing Diagram
WP/ACC
~
~
VHH
VIL or VIH
VIL or VIH
tVHH
PRELIMINARY
(August, 2005, Version 0.0)
tVHH
38
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Figure 17. Chip/Sector Erase Operation Timings
Read Status Data
Erase Command Sequence (last two cycles)
tAS
~
~
tWC
VA
555h for chip erase
tAH
VA
~
~ ~
~
SA
2AAh
Addresses
~
~
CE_F
OE
tCH
~
~
tWP
WE
tWPH
tWHWH2
tCS
Data
tDH
55h
30h
~
~
tDS
10h for chip erase
tBUSY
In
Progress
Complete
tRB
~
~
RY/BY
~
~
tVCS
VCC_F
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustration shows device in word mode.
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(August, 2005, Version 0.0)
39
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Figure 18. Back-to-back Read/Write Cycle Timings
Addresses
tWC
tRC
Valid PA
Valid RA
tAH
tWC
tWC
Valid PA
Valid PA
tACC
tCPH
tCE
CE_F
tCP
tOE
OE
tGHWL
tOEH
tWP
WE
tDF
tWPH
tDS
tOH
tDH
Valid
In
Data
Valid
In
Valid
Out
Valid
In
tSR/W
WE Controlled Write Cycle
Read Cycle
CE Controlled Write Cycles
Figure 19. Data Polling Timings (During Embedded Algorithms)
~
~
tRC
Addresses
VA
tACC
CE_F
VA
~
~ ~
~
VA
tCE
tCH
~
~
tOE
OE
tDF
~
~
tOEH
WE
tOH
Status Data
~
~
Complement
Complement
True
Valid Data
~
~
High-Z
I/O7
Status Data
True
Valid Data
High-Z
I/O0 - I/O6
High-Z
tBUSY
~
~
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
tAS
~
~
tAHT
~
~
Addresses
tAHT
tASO
tCEPH
CE_F
~
~
tOEH
tOEPH
WE
~
~
OE
tOE
I/O6 , I/O2 Valid Status
Valid Status
Valid Status
(first read)
(second read)
~
~
tDH
Valid Status
Valid Data
(stop togging)
~
~
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 21. I/O2 vs. I/O6
~
~
~
~
Erase
Complete
~
~
~
~
~
~
~
~
~
~
Erase
~
~
Erase Suspend
Read
~
~
~
~
~
~
I/O2
~
~
I/O6
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
~
~
Erase
Enter Erase
Suspend Program
~
~
WE
Erase
Suspend
~
~
Enter
Embedded
Erasing
I/O2 and I/O6 toggle with OE and CE_F
Note : Both I/O6 and I/O2 toggle with OE or CE_F. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tVHH
VHH Rise and Fall Time (See Note)
Min
250
µs
tRSP
RESET Setup Time for Temporary
Min
4
µs
Min
4
µs
Sector/Sector Block Unprotect
RESET Hold Time from RY/ BY High for
Temporary Sector/Sector Block Unprotect
tRRB
Note: Not 100% tested.
Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram
VID
~
~
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
RESET
tVIDR
tVIDR
Program or Erase Command Sequence
CE_F
~
~
WE
RY/BY
~ ~
~
~
tRSP
tRRB
Program/Erase Command Sequence
CE_F
~
~
WE
555
2AA
555
I/O0 - I/O7
AA
55
77
XXX
~
~
~ ~
Address
~
~
FQ
RY/BY
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram
VID
VIH
~
~
RESET
SA, A6,
A1, A0
Valid*
Valid*
~
~
Valid*
Verify
~
~
Sector Protect/Unprotect
60h
60h
40h
Status
~
~
Data
1us
CE
Sector Protect:150us
Sector Unprotect:15ms
WE
OE
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
PRELIMINARY
(August, 2005, Version 0.0)
43
200ns-300ns
AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Alternate CE_F Controlled Erase and Program Operations
Parameter
Description
Speed
Unit
JEDEC
Std
-70
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
70
ns
tAVEL
tAS
Address Setup Time
Min.
0
ns
tELAX
tAH
Address Hold Time
Min.
45
ns
tDVEH
tDS
Data Setup Time
Min.
35
ns
tEHDX
tDH
Data Hold Time
Min.
0
ns
tGHEL
tGHEL
Min.
0
ns
Read Recover Time Before Write
( OE High to WE Low)
tWLEL
tWS
WE Setup Time
Min.
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
ns
tELEH
tCP
CE_F Pulse Width
Min.
30
ns
tEHEL
tCPH
CE_F Pulse Width High
Min.
30
ns
tWHWH1
tWHWH1
tWHWH1
tWHWH1
tWHWH2
tWHWH2
Programming Operation
Byte
Typ.
5
(Note 2)
Word
Typ.
7
Typ.
4
µs
Typ.
0.7
sec
Accelerated Programming Operation,
Word or Byte (Note 2)
Sector Erase Operation (Note 2)
µs
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
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AMIC Technology, Corp.
A82DL16x4T(U) Series
AC CHARACTERISTICS
Figure 24. Alternate CE_F Controlled Write (Erase/Program) Operation Timings
PA for program
SA for sector erase
555 for chip erase
Data Polling
~
~
555 for program
2AA for erase
PA
~
~
Addresses
tAS
tWH
tAH
~
~
tWC
WE
OE
~
~
tGHEL
tCP
~
~
tWHWH1 or 2
tCPH
CE_F
tBUSY
tWS
tDS
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
I/O7
DOUT
~
~
~
~
tDH
RESET
~
~
RY/BY
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. I/O7 is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
SRAM
DC Electrical Characteristics
Symbol
(TA = -40°C to +85°C, VCC_S = 2.7V to 3.6V, GND = 0V)
Parameter
- 70 ns
⎜ILI⎥
Input Leakage Current
⎜ILO⎥
Output Leakage Current
ICC_S
Active Power Supply
Current
Unit
Min.
Max.
-
1
µA
-
1
µA
-
3
mA
Conditions
VIN = GND to VCC_S
CE1_S = VIH or CE2_S = VIL
or OE = VIH or WE = VIL
VI/O = GND to VCC
CE1_S = VIL, CE2_S = VIH
II/O = 0mA
Min. Cycle, Duty = 100%
-
ICC1_S
30
mA
CE1_S = VIL, CE2_S = VIH
II/O = 0mA
Dynamic Operating
CE1_S = VIL, CE2_S = VIH
Current
ICC2_S
-
3
mA
ISB_S
-
0.5
mA
VCC_S ≤ 3.3V, CE1_S = VIH or
CE2_S =VIL
-
5
µA
VCC ≤ 3.3V, CE1_S ≥ VCC - 0.2V
or CE2_S ≤ 0.2V, VIN ≥ 0V
Standby Power Supply
Current
ISB1_S
VIH = VCC_S, VIL = 0V
f = 1 MHZ, II/O = 0mA
VOL
Output Low Voltage
-
0.4
V
IOL = 2.1mA
VOH
Output High Voltage
2.2
-
V
IOH = -1.0mA
Truth Table
CE1_S
CE2_S
OE
WE
I/O Operation
H
X
X
X
High Z
ISB, ISB1
X
L
X
X
High Z
ISB, ISB1
Output Disable
L
H
H
H
High Z
ICC, ICC1, ICC2
Read
L
H
L
H
DOUT
ICC, ICC1, ICC2
Write
L
H
X
L
DIN
ICC, ICC1, ICC2
Mode
Standby
Supply Current
Note: X = H or L
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
6
pF
VIN = 0V
CI/O*
Input/Output Capacitance
8
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
AC Characteristics
(TA = -40°C to +85°C, VCC_S = 2.7V to 3.6V)
Symbol
-70 ns
Parameter
Unit
Min.
Max.
70
-
ns
-
70
ns
CE1_S
-
70
ns
CE2_S
-
70
ns
-
35
ns
CE1_S
10
-
ns
CE2_S
10
-
ns
5
-
ns
CE1_S
0
25
ns
CE2_S
0
25
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
tACE1
Chip Enable Access Time
tACE2
tOE
tCLZ1
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ2
tOLZ
Output Enable to Output in Low Z
tCHZ1
Chip Disable to Output in High Z
tCHZ2
tOHZ
Output Disable to Output in High Z
0
25
ns
tOH
Output Hold from Address Change
10
-
ns
tWC
Write Cycle Time
70
-
ns
tCW
Chip Enable to End of Write
60
-
ns
tAS
Address Setup Time
0
-
ns
tAW
Address Valid to End of Write
60
-
ns
tWP
Write Pulse Width
50
-
ns
tWR
Write Recovery Time
0
-
ns
tWHZ
Write to Output in High Z
0
25
ns
tDW
Data to Write Time Overlap
30
-
ns
tDH
Data Hold from Write Time
0
-
ns
tOW
Output Active from End of Write
5
-
ns
Write Cycle
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Timing Waveforms
Read Cycle 1 (1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2 (1, 3, 4, 6)
CE1_S
tACE1
tCLZ15
tCHZ15
DOUT
Read Cycle 3 (1, 4, 7, 8)
CE2_S
tACE2
tCHZ25
tCLZ25
DOUT
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Timing Waveforms (continued)
Read Cycle 4 (1)
tRC
Address
tAA
OE
tOE
tOH
tOLZ5
CE1_S
tACE1
tCHZ15
tCLZ15
CE2_S
tACE2
tOHZ5
tCHZ25
tCLZ25
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1_S = VIL and CE2_S = VIH.
3. Address valid prior to or coincident with CE1_S transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2_S is high.
7. CE1_S is low.
8. Address valid prior to or coincident with CE2_S transition high.
Write Cycle 1 (6)
(Write Enable Controlled)
t WC
Address
tAW
t WR3
t CW 5
CE1_S
(4)
CE2_S
(4)
t AS1
tWP 2
WE
t DW
tDH
DIN
tWHZ
t OW
DOUT
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tWR3
tAW
tCW
CE1_S
1
tAS
CE2_S
5
(4)
(4)
tCW 5
tWP2
WE
tDW
tDH
DIN
tWHZ 7
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1_S , a high CE2_S and a low WE .
3. tWR is measured from the earliest of CE1_S or WE going high or CE2_S going low to the end of the Write cycle.
4. If the CE1_S low transition or the CE2_S high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1_S going low or CE2_S going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
SRAM
Data Retention Characteristics (TA = -40°C to 85°C)
Symbol
Parameter
Min.
Max.
Unit
2.0
3.6
V
CE1_S ≥ VCC - 0.2V
VDR2
2.0
3.6
V
CE2_S ≤ 0.2V,
ICCDR1_S
-
1*
µA
VDR1
Conditions
VCC for Data Retention
VCC_S = 2V,
CE1_S ≥ VCC_S - 0.2V,
VIN ≥ 0V
Data Retention Current
-
1*
µA
VCC_S = 2V,
CE2_S ≤ 0.2V,
VIN ≥ 0V
Chip Disable to Data Retention Time
0
-
ns
See Retention Waveform
Operation Recovery Time
5
-
ms
ICCDR2_S
tCDR
tR
*
ICCDR_S: max.
1µA at TA = 0°C to + 40°C
Low VCC Data Retention Waveform (1) ( CE1_S Controlled)
DATA RETENTION MODE
VCC_S
3.0V
tCDR
CE1_S
3.0V
VDR _Σ ≥ 2V
VIH
tR
VIH
CE1_S ≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2_S Controlled)
DATA RETENTION MODE
VCC_S
3.0V
tCDR
CE2_S
3.0V
VDR_S ≥ 2.0V
VIL
tR
VIL
CE2_S ≤ 0.2V
PRELIMINARY
(August, 2005, Version 0.0)
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AMIC Technology, Corp.
A82DL16x4T(U) Series
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ. (Note 1)
Max. (Note 2)
Unit
Sector Erase Time
0.7
15
sec
Chip Erase Time
27
Byte Programming Time
5
150
µs
Word Programming Time
7
210
µs
Accelerated Word/Byte Programming Time
4
120
µs
Chip Programming Time
Byte Mode
9
27
sec
(Note 3)
Word Mode
6
18
sec
Comments
Excludes 00h programming
prior to erasure (Note 4)
sec
Excludes system-level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC_F, 10,000 cycles. Additionally,
programming typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC_F = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12
for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 10,000 cycles.
FLASH LATCH-UP CHARACTERISTICS
Description
Min.
Max.
-1.0V
VCC+1.0V
-100 mA
+100 mA
-1.0V
12.5V
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Input Voltage with respect to VSS on all I/O pins
VCC_F Current
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE and RESET )
Includes all pins except VCC_F. Test conditions: VCC_F = 3.0V, one pin at time.
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Ordering Information
Top Boot Sector Flash & SRAM
Part No.
Access Time
(ns)
Bank 1
Bank 2
A82DL1624TG-70
Package
69-ball TFBGA
A82DL1624TG-70F
69-ball Pb-Free TFBGA
A82DL1624TG-70I
69-ball TFBGA
70
2M
14M
A82DL1624TG-70IF
69-ball Pb-Free TFBGA
A82DL1624TG-70U
69-ball TFBGA
A82DL1624TG-70UF
69-ball Pb-Free TFBGA
A82DL1634TG-70
69-ball TFBGA
A82DL1634TG-70F
69-ball Pb-Free TFBGA
A82DL1634TG-70I
69-ball TFBGA
70
4M
12M
A82DL1634TG-70IF
69-ball Pb-Free TFBGA
A82DL1634TG-70U
69-ball TFBGA
A82DL1634TG-70UF
69-ball Pb-Free TFBGA
A82DL1644TG-70
69-ball TFBGA
A82DL1644TG-70F
69-ball Pb-Free TFBGA
A82DL1644TG-70I
69-ball TFBGA
70
8M
8M
A82DL1644TG-70IF
69-ball Pb-Free TFBGA
A82DL1644TG-70U
69-ball TFBGA
A82DL1644TG-70UF
69-ball Pb-Free TFBGA
Note: Industrial operating temperature range: -40°C to 85°C for –U; -25°C to 85°C for –I
PRELIMINARY
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AMIC Technology, Corp.
A82DL16x4T(U) Series
Bottom Boot Sector Flash & SRAM
Part No.
Access Time
(ns)
Bank 1
Bank 2
A82DL1624UG-70
Package
69-ball TFBGA
A82DL1624UG-70F
69-ball Pb-Free TFBGA
A82DL1624UG-70I
69-ball TFBGA
70
2M
14M
A82DL1624UG-70IF
69-ball Pb-Free TFBGA
A82DL1624UG-70U
69-ball TFBGA
A82DL1624UG-70UF
69-ball Pb-Free TFBGA
A82DL1634UG-70
69-ball TFBGA
A82DL1634UG-70F
69-ball Pb-Free TFBGA
A82DL1634UG-70I
69-ball TFBGA
70
4M
12M
A82DL1634UG-70IF
69-ball Pb-Free TFBGA
A82DL1634UG-70U
69-ball TFBGA
A82DL1634UG-70UF
69-ball Pb-Free TFBGA
A82DL1644UG-70
69-ball TFBGA
A82DL1644UG-70F
69-ball Pb-Free TFBGA
A82DL1644UG-70I
69-ball TFBGA
70
8M
8M
A82DL1644UG-70IF
69-ball Pb-Free TFBGA
A82DL1644UG-70U
69-ball TFBGA
A82DL1644UG-70UF
69-ball Pb-Free TFBGA
Note: Industrial operating temperature range: -40°C to 85°C for –U; -25°C to 85°C for –I
PRELIMINARY
(August, 2005, Version 0.0)
55
AMIC Technology, Corp.
A82DL16x4T(U) Series
Package Information
69LD STF BGA (8 x 11mm) Outline Dimensions
Pin #1
-A-
D
unit: mm
D1
aaa
e
-B-
aaa
E1
E
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10
See Detail B
ddd M C
eee M C A B
See Detail A
C
CAVITY
// bbb C
b
A
A1
c
A
A2
B
-Cccc C
SOLDER BALL
1
SEATING PLANE
Detail A
Symbol
A
A1
A2
c
D
E
D1
E1
e
b
aaa
bbb
ccc
ddd
eee
MD/ME
2
3
Detail B
Dimensions in mm
Min
Nom
Max
1.40
0.25
0.30
0.35
0.91
0.96
1.01
0.22
0.26
0.30
7.90
8.00
8.10
10.90
11.00
11.10
7.20
7.20
0.80
0.35
0.40
0.45
0.15
0.20
0.12
0.15
0.08
10/10
Dimensions in inches
Min
Nom
Max
0.055
0.010
0.012
0.014
0.036
0.038
0.040
0.009
0.010
0.012
0.311
0.315
0.319
0.429
0.433
0.437
0.283
0.283
0.031
0.14
0.16
0.18
0.006
0.008
0.005
0.006
0.003
10/10
Notes:
1. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
2. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL
DIAMETER, PARALLEL TO PRIMARY DATUM C.
3. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN
THE EDGE OF THE SOLDER BALL AND THE BODY EDGE.
4. REFERENCE DOCUMENT : JEDEC MO-219
5. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY.
PRELIMINARY
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AMIC Technology, Corp.