774.book Page 1 Tuesday, January 29, 2013 12:02 PM PIC16C77X 28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D Microcontroller Core Features: Pin Diagram * Enhanced features 1999-2013 Microchip Technology Inc. 600 mil. PDIP, Windowed CERDIP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/VRL RA3/AN3/VREF+/VRH RA4/T0CKI RA5/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 AVDD AVSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC16C774 • High-performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • 4K x 14 words of Program Memory, 256 x 8 bytes of Data Memory (RAM) • Interrupt capability (up to 14 internal/external interrupt sources) • Eight level deep hardware stack • Direct, indirect, and relative addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code-protection • Power saving SLEEP mode • Selectable oscillator options • Low-power, high-speed CMOS EPROM technology • Fully static design • In-Circuit Serial Programming(ISCP • Wide operating voltage range: 2.5V to 5.5V • High Sink/Source Current 25/25 mA • Commercial and Industrial temperature ranges • Low-power consumption: - < 2 mA @ 5V, 4 MHz - 22.5 A typical @ 3V, 32 kHz - < 1 A typical standby current 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3/AN9/LVDIN RB2/AN8 RB1/SS RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 Peripheral Features: * * * * * * • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Two Capture, Compare, PWM modules • Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM max. resolution is 10-bit • 12-bit multi-channel Analog-to-Digital converter • On-chip absolute bandgap voltage reference generator • Synchronous Serial Port (SSP) with SPI (Master Mode) and I2C • Universal Synchronous Asynchronous Receiver Transmitter, supports high/low speeds and 9-bit address mode (USART/SCI) • Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls • Programmable Brown-out detection circuitry for Brown-out Reset (BOR) • Programmable Low-voltage detection circuitry Advance Information DS30275B-page 1 774.book Page 2 Tuesday, January 29, 2013 12:02 PM PIC16C77X Pin Diagrams 300 mil. SDIP, SOIC, Windowed CERDIP, SSOP •1 28 2 27 3 26 4 25 5 6 7 8 9 10 PIC16C773 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/VRL RA3/AN3/VREF+/VRH RA4/T0CKI AV DD AVSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RB7 RB6 RB5 RB4 RB3/AN9/LVDIN RB2/AN8 RB1/SS RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA 24 23 22 21 20 19 18 12 17 13 16 14 15 RA3/AN3/VREF+/VRH RA2/AN2/VREF-/VRL RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC 11 6 5 4 3 2 1 44 43 42 41 40 PLCC 7 8 9 10 11 12 13 14 15 16 17 PIC16C774 39 38 37 36 35 34 33 32 31 30 29 RB3/AN9/LVDIN RB2/AN8 RB1/SS RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC 1 2 3 4 5 6 7 8 9 10 11 PIC16C774 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN AVSS AVDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4 RA4/T0CKI NC NC RB4 RB5 RB6 RB7 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/VRL RA3/AN3/VREF+/VRH RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1/SS RB2/AN8 RB3/AN9/LVDIN 44 43 42 41 40 39 38 37 36 35 34 MQFP TQFP 12 13 14 15 16 17 18 19 20 21 22 RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC 18 19 20 21 22 23 24 25 26 27 28 RA4/T0CKI RA5/AN4 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 AVDD AVSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC DS30275B-page 2 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 3 Tuesday, January 29, 2013 12:02 PM PIC16C77X Key Features PICmicro™ Mid-Range Reference Manual (DS33023) PIC16C773 PIC16C774 Operating Frequency DC - 20 MHz DC - 20 MHz Resets (and Delays) POR, BOR, MCLR, WDT (PWRT, OST) POR, BOR, MCLR, WDT (PWRT, OST) Program Memory (14-bit words) 4K 4K Data Memory (bytes) 256 256 Interrupts 13 14 I/O Ports Ports A,B,C Ports A,B,C,D,E Timers 3 3 Capture/Compare/PWM modules 2 2 Serial Communications MSSP, USART MSSP, USART Parallel Communications — PSP 12-bit Analog-to-Digital Module 6 input channels 10 input channels Instruction Set 35 Instructions 35 Instructions 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 3 774.book Page 4 Tuesday, January 29, 2013 12:02 PM PIC16C77X Table of Contents 1.0 Device Overview ............................................................................................................................................................................ 5 2.0 Memory Organization................................................................................................................................................................... 11 3.0 I/O Ports ....................................................................................................................................................................................... 27 4.0 Timer0 Module ............................................................................................................................................................................. 39 5.0 Timer1 Module ............................................................................................................................................................................. 41 6.0 Timer2 Module ............................................................................................................................................................................. 45 7.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................... 47 8.0 Master Synchronous Serial Port (MSSP) Module ........................................................................................................................ 53 9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................. 97 10.0 Voltage Reference Module and Low-voltage Detect.................................................................................................................. 113 11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117 12.0 Special Features of the CPU ..................................................................................................................................................... 127 13.0 Instruction Set Summary............................................................................................................................................................ 143 14.0 Development Support ................................................................................................................................................................ 145 15.0 Electrical Characteristics............................................................................................................................................................ 151 16.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 173 17.0 Packaging Information ............................................................................................................................................................... 175 Appendix A: Revision History ......................................................................................................................................................... 187 Appendix B: Device Differences..................................................................................................................................................... 187 Appendix C: Conversion Considerations........................................................................................................................................ 187 Index .................................................................................................................................................................................................. 189 Bit/Register Cross-Reference List...................................................................................................................................................... 196 On-Line Support................................................................................................................................................................................. 197 Reader Response .............................................................................................................................................................................. 198 PIC16C77X Product Identification System......................................................................................................................................... 199 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at [email protected]. We appreciate your assistance in making this a better document. DS30275B-page 4 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 5 Tuesday, January 29, 2013 12:02 PM PIC16C77X 1.0 DEVICE OVERVIEW There a two devices (PIC16C773 and PIC16C774) covered by this datasheet. The PIC16C773 devices come in 28-pin packages and the PIC16C774 devices come in 40-pin packages. The 28-pin devices do not have a Parallel Slave Port implemented. This document contains device-specific information. Additional information may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. FIGURE 1-1: The following two figures are device block diagrams sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-1 and Table 1-2, respectively. PIC16C773 BLOCK DIAGRAM 13 EPROM Program Memory 4K x 14 Program Bus PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/VRL RA3/AN3/VREF+/VRH RA4/T0CKI RAM File Registers 256 x 8 8 Level Stack (13-bit) 14 8 Data Bus Program Counter RAM Addr (1) PORTB 9 RB0/INT RB1/SS RB2/AN8 RB3/AN9/LVDIN RB7:RB4 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg STATUS reg 8 3 Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Low-voltage Detect Precision Reference Timer0 CCP1,2 ALU RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 W reg Watchdog Timer Brown-out Reset MCLR 12-bit ADC MUX PORTC VDD, VSS AVDD AVSS Timer1 Synchronous Serial Port Timer2 USART Note 1: Higher order bits are from the STATUS register. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 5 774.book Page 6 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 1-2: PIC16C774 BLOCK DIAGRAM 13 EPROM Program Memory 4K x 14 Program Bus PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/VRL RA3/AN3/VREF+/VRH RA4/T0CKI RA5/AN4 RAM File Registers 256 x 8 8 Level Stack (13-bit) 14 8 Data Bus Program Counter RAM Addr (1) PORTB 9 RB0/INT RB1/SS RB2/AN8 RB3/AN9/LVDIN RB7:RB4 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg STATUS reg 8 3 Instruction Decode & Control OSC1/CLKIN OSC2/CLKOUT Timing Generation Precision Reference RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MUX Power-up Timer Oscillator Start-up Timer Power-on Reset Low-voltage Detect PORTC ALU 8 PORTD W reg Watchdog Timer Brown-out Reset RD7/PSP7:RD0/PSP0 Parallel Slave Port MCLR PORTE RE0/AN5/RD VDD, VSS RE1/AN6/WR 12-bit ADC Timer0 CCP1,2 RE2/AN7/CS AV DD AVSS Timer1 Synchronous Serial Port Timer2 USART Note 1: Higher order bits are from the STATUS register. DS30275B-page 6 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 7 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 1-1 PIC16C773 PINOUT DESCRIPTION Pin Name DIP, SSOP, SOIC Pin# I/O/P Type Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. OSC1/CLKIN 9 I OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. RA0/AN0 2 I/O TTL RA1/AN1 3 I/O TTL RA1 can also be analog input1 RA2/AN2/VREF-/VRL 4 I/O TTL RA2 can also be analog input2 or negative analog reference voltage input or internal voltage reference low RA3/AN3/VREF+/VRH 5 I/O TTL RA3 can also be analog input3 or positive analog reference voltage input or internal voltage reference high RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. PORTA is a bi-directional I/O port. RA0 can also be analog input0 PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 I/O TTL/ST(1) RB1/SS 22 I/O TTL/ST(1) RB2/AN8 23 I/O TTL RB2 can also be analog input8 RB3/AN9/LVDIN 24 I/O TTL RB3 can also be analog input9 or the low voltage detect input reference RB4 25 I/O TTL Interrupt on change pin. RB5 26 I/O TTL Interrupt on change pin. RB6 27 I/O TTL/ST(2) RB7 28 I/O TTL/ST(2) RB0 can also be the external interrupt pin. RB1 can also be the SSP slave select Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI/CCP2 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. AVSS 8 P AVDD 7 P VSS 19 P — Ground reference for logic and I/O pins. VDD 20 P — Positive supply for logic and I/O pins. Ground reference for A/D converter Positive supply for A/D converter Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 7 774.book Page 8 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 1-2 PIC16C774 PINOUT DESCRIPTION Pin Name DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type ST/CMOS Description (4) Oscillator crystal input/external clock source input. OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0 RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1 RA2/AN2/VREF-/VRL 4 5 21 I/O TTL RA2 can also be analog input2 or negative analog reference voltage input or internal voltage reference low RA3/AN3/VREF+/VRH 5 6 22 I/O TTL RA3 can also be analog input3 or positive analog reference voltage input or internal voltage reference high RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5/AN4 7 8 24 I/O TTL PORTA is a bi-directional I/O port. RA5 can also be analog input4 PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(1) RB1/SS 34 37 9 I/O TTL/ST(1) RB2/AN8 35 38 10 I/O TTL RB2 can also be analog input8 RB3/AN9/LVDIN 36 39 11 I/O TTL RB3 can also be analog input9 or input reference for low voltage detect RB4 37 41 14 I/O TTL Interrupt on change pin. RB5 38 42 15 I/O TTL Interrupt on change pin. RB6 39 43 16 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. RB0 can also be the external interrupt pin. RB1 can also be the SSP slave select Legend: I = input Note 1: 2: 3: 4: O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured for the multiplexed function. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS30275B-page 8 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 9 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 1-2 PIC16C774 PINOUT DESCRIPTION (Cont.’d) DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. Pin Name Description PORTC is a bi-directional I/O port. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. (3) RD0/PSP0 19 21 38 I/O ST/TTL RD1/PSP1 20 22 39 I/O ST/TTL(3) RD2/PSP2 21 23 40 I/O ST/TTL(3) RD3/PSP3 22 24 41 I/O ST/TTL(3) RD4/PSP4 27 30 2 I/O ST/TTL(3) RD5/PSP5 28 31 3 I/O ST/TTL(3) RD6/PSP6 29 32 4 I/O ST/TTL(3) RD7/PSP7 30 33 5 I/O ST/TTL(3) RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave port, or analog input5. RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port, or analog input6. RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave port, or analog input7. AVss 12 13 29 P Ground reference for A/D converter AVDD 11 12 28 P Positive supply for A/D converter VSS 31 34 6 P — VDD 32 35 7 P — Positive supply for logic and I/O pins. NC — 1,17,28, 40 12,13, 33,34 — These pins are not internally connected. These pins should be left unconnected. PORTE is a bi-directional I/O port. Ground reference for logic and I/O pins. Legend: I = input Note 1: 2: 3: 4: O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured for the multiplexed function. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 9 774.book Page 10 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 10 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 11 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.0 MEMORY ORGANIZATION There are two memory blocks in each of these PICmicro ® microcontrollers. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). 2.1 Program Memory Organization The PIC16C77X PICmicros have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Each device has 4K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 2-1: PROGRAM MEMORY MAP AND STACK Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1 RP0 = 00 = 01 = 10 = 11 Bank0 Bank1 Bank2 Bank3 (STATUS<6:5>) Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register FSR. PC<12:0> CALL, RETURN RETFIE, RETLW 2.2 13 Stack Level 1 Stack Level 2 Stack Level 8 On-chip Program Memory Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h 3FFFh 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 11 774.book Page 12 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 2-2: REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) PORTE (1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD (1) TRISE (1) PCLATH INTCON PIE1 PIE2 PCON SSPCON2 PR2 SSPADD SSPSTAT TXSTA SPBRG REFCON LVDCON ADRESL ADCON1 accesses 70h-7Fh 7Fh Bank 0 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB PCLATH INTCON A0h General Purpose Register 80 Bytes 96 Bytes 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh File Address EFh F0h General Purpose Register 80 Bytes accesses 70h - 7Fh 6Fh 70h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB PCLATH INTCON Bank 2 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h accesses 70h - 7Fh 17Fh FFh Bank 1 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h File Address 1EFh 1F0h 1FFh Bank 3 (1) Not implemented on PIC16C773. * Unimplemented data memory locations, read as '0'. Not a physical register. DS30275B-page 12 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 13 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section. The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 0 00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(4) STATUS 04h(4) FSR 05h PORTA --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx 11xx uuuu 11uu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h(5) PORTE — — — 0Ah(1,4) PCLATH — — — 0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF 0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF 0Dh PIR2 LVDIF — — – BCLIF — — CCP2IF 0--- 0--0 0--- 0--0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON 11h TMR2 IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer — — — — PORTA5(5) T1CKPS1 PORTA Data Latch when written: PORTA<4:0> pins when read — — RE2 RE1 RE0 T1OSCEN T1SYNC TMR1CS — TOUTPS3 TOUTPS2 TOUTPS1 12h T2CON SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register1 (LSB) 16h CCPR1H Capture/Compare/PWM Register1 (MSB) 17h CCP1CON 18h RCSTA TOUTPS0 TMR2ON T2CKPS1 ---- -000 ---0 0000 RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1ON T2CKPS0 Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 uuuu uuuu ---0 0000 Timer2 module’s register 13h 000q quuu xxxx xxxx ---- -000 Write Buffer for the upper 5 bits of the Program Counter T1CKPS0 0001 1xxx SSPM0 --00 0000 --uu uuuu 0000 0000 0000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON 1Eh ADRESH — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 A/D High Byte Result Register 1999-2013 Microchip Technology Inc. CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000 ADCON0 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. These registers can be addressed from any bank. These registers/bits are not implemented on the 28-pin devices read as '0'. 2: 3: 4: 5: CHS2 uuuu uuuu 1Fh 1: ADCS0 --00 0000 xxxx xxxx Legend: Note ADCS1 --00 0000 Advance Information DS30275B-page 13 774.book Page 14 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) 0000 0000 0000 0000 Bank 1 80h(4) INDF 81h OPTION_REG 82h(4) PCL 83h(4) STATUS 84h(4) FSR 85h TRISA 86h TRISB Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer — — bit5(5) PORTA Data Direction Register 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu --11 1111 --11 1111 PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h(5) TRISE IBF OBF IBOV 0000 -111 0000 -111 8Ah(1,4) PCLATH — — — 8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF 8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE 8Dh PIE2 LVDIE — — — BCLIE — 8Eh PCON — — — — — — PSPMODE — PORTE Data Direction Bits Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 RBIF 0000 000x 0000 000u TMR2IE TMR1IE 0000 0000 0000 0000 — CCP2IE 0--- 0--0 0--- 0--0 POR BOR ---- --qq ---- --uu — 8Fh — Unimplemented — 90h — Unimplemented — — 0000 0000 0000 0000 91h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA 0000 -010 0000 -010 99h SPBRG 0000 0000 0000 0000 9Ah — 9Bh REFCON 9Ch LVDCON 9Ah — 9Eh ADRESL CSRC TX9 TXEN SYNC — BRGH TRMT TX9D Baud Rate Generator Register Unimplemented — — VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ---- — — BGST LVDEN LV3 LV2 LV1 LV0 --00 0101 --00 0101 Unimplemented A/D Low Byte Result Register DS30275B-page 14 VCFG0 PCFG3 PCFG2 Advance Information PCFG1 PCFG0 0000 0000 0000 0000 ADCON1 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. These registers can be addressed from any bank. These registers/bits are not implemented on the 28-pin devices read as '0'. 2: 3: 4: 5: VCFG1 uuuu uuuu 9Fh 1: VCFG2 — xxxx xxxx Legend: Note ADFM — 1999-2013 Microchip Technology Inc. 774.book Page 15 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (2) Bank 2 100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h(4) STATUS 104h(4) FSR 105h — 106h PORTB 107h — 108h — 109h — 10Ah(1,4) PCLATH 10Bh(4) INTCON 10Ch10Fh IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer — Unimplemented 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu — — xxxx 11xx uuuu 11uu Unimplemented — — Unimplemented — — Unimplemented — — ---0 0000 ---0 0000 0000 000x 0000 000u — — 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PORTB Data Latch when written: PORTB pins when read — — — GIE PEIE T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF Unimplemented Bank 3 180h(4) INDF 181h OPTION_REG 182h(4) PCL 183h(4) STATUS 184h(4) FSR 185h Addressing this location uses contents of FSR to address data memory (not a physical register) INTEDG T0CS T0SE PSA PS2 PS1 PS0 IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer — 186h RBPU Program Counter's (PC) Least Significant Byte TRISB Unimplemented PORTB Data Direction Register 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu — — 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — ---0 0000 ---0 0000 0000 000x 0000 000u — — 18Ah(1,4) PCLATH 18Bh(4) 18Ch18Fh — Legend: Note INTCON 1: 2: 3: 4: 5: — — — GIE PEIE T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE Unimplemented T0IF INTF RBIF x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. These registers can be addressed from any bank. These registers/bits are not implemented on the 28-pin devices read as '0'. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 15 774.book Page 16 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.1 STATUS REGISTER For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. FIGURE 2-3: R/W-0 IRP Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC bit7 bit 7: R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. DS30275B-page 16 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 17 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.2 OPTION_REG REGISTER Note: The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 2-4: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. OPTION_REG REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit7 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1999-2013 Microchip Technology Inc. WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Advance Information DS30275B-page 17 774.book Page 18 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 2-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: IINTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state DS30275B-page 18 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 19 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. FIGURE 2-6: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. PIE1 REGISTER (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset Note 1: PSPIE is reserved on the 28-pin devices, always maintain this bit clear. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 19 774.book Page 20 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. FIGURE 2-7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1 REGISTER (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PSPIF is reserved on the 28-pin devices, always maintain this bit clear. DS30275B-page 20 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 21 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.6 PIE2 REGISTER This register contains the individual enable bits for the CCP2, SSP bus collision, and low voltage detect interrupts. FIGURE 2-8: PIE2 REGISTER (ADDRESS 8Dh) R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 LVDIE — — — BCLIE — — CCP2IE bit7 bit 7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset LVDIE: Low-voltage Detect Interrupt Enable bit 1 = LVD Interrupt is enabled 0 = LVD Interrupt is disabled bit 6-4: Unimplemented: Read as '0' bit 3: BCLIE: Bus Collision Interrupt Enable bit 1 = Bus Collision interrupt is enabled 0 = Bus Collision interrupt is disabled bit 2-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 21 774.book Page 22 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.7 PIR2 REGISTER . Note: This register contains the CCP2, SSP Bus Collision, and Low-voltage detect interrupt flag bits. FIGURE 2-9: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR2 REGISTER (ADDRESS 0Dh) R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 LVDIF — — — BCLIF — — CCP2IF bit7 bit 7: bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset LVDIF: Low-voltage Detect Interrupt Flag bit 1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software) 0 = The supply voltage is greater than the specified LVD voltage bit 6-4: Unimplemented: Read as '0' bit 3: BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision has occurred while the SSP module configured in I2C Master was transmitting (must be cleared in software) 0 = No bus collision occurred bit 2-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused DS30275B-page 22 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 23 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.2.2.8 PCON REGISTER Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word). FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 — — — — — — POR BOR bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 23 774.book Page 24 Tuesday, January 29, 2013 12:02 PM PIC16C77X 2.3 PCL and PCLATH 2.4 The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. 2.3.1 STACK The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. Program Memory Paging PIC16C77X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30275B-page 24 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 25 Tuesday, January 29, 2013 12:02 PM PIC16C77X EXAMPLE 2-1: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). movlw movwf clrf incf btfss goto NEXT A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1. HOW TO CLEAR RAM USING INDIRECT ADDRESSING 0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next CONTINUE : ;YES, continue An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-11. FIGURE 2-11: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing from opcode RP1:RP0 6 bank select location select 0 IRP 7 bank select 00 01 10 FSR register 0 location select 11 00h 80h 100h 180h 7Fh FFh 17Fh 1FFh Data Memory(1) Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail see Figure 2-2. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 25 774.book Page 26 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 26 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 27 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.0 I/O PORTS FIGURE 3-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023). Data bus WR Port BLOCK DIAGRAM OF RA3:RA2 PINS D Q VDD CK Q P Data Latch 3.1 PORTA and the TRISA Register PORTA is a 6-bit wide bi-directional port for the 40/44 pin devices and is 5-bits wide for the 28-pin devices. PORTA<5> is not on the 28-pin devices. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF inputs and precision on-board references (VRL/VRH). The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 3-1: BCF CLRF D WR TRIS CK N Q I/O pin(1) VSS Analog input mode Q TRIS Latch TTL input buffer RD TRIS Q D EN RD PORT To A/D Converter VRH, VRL VRHOEN, VRLOEN Sense input for VRO+, VRO- amplifier INITIALIZING PORTA STATUS, RP0 PORTA BSF MOVLW STATUS, RP0 0xCF MOVWF TRISA ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6> are always read as '0'. 1999-2013 Microchip Technology Inc. Note 1: I/O pins have protection diodes to VDD and VSS. Advance Information DS30275B-page 27 774.book Page 28 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 3-2: Data bus BLOCK DIAGRAM OF RA1:RA0 AND RA5 PINS FIGURE 3-3: Data bus D Q WR TRIS CK Q N Q D Q CK Q WR TRIS I/O pin(1) VSS Schmitt Trigger input buffer TRIS Latch VSS Analog input mode Q CK I/O pin(1) Data Latch P Data Latch D Q N Q CK D WR PORT VDD WR Port BLOCK DIAGRAM OF RA4/T0CKI PIN TRIS Latch RD TRIS Q TTL input buffer RD TRIS Q D ENEN RD PORT D TMR0 clock input EN Note 1: I/O pin has protection diodes to VSS only. RD PORT To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 3-1 PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 RA1/AN1 RA2/AN2/VREF-/VRL bit0 bit1 bit2 TTL TTL TTL Function Input/output or analog input0 Input/output or analog input1 Input/output or analog input2 or VREF- input or internal reference voltage low RA3/AN3/VREF+/VRH bit3 TTL Input/output or analog input or VREF+ input or output of internal reference voltage high RA4/T0CKI bit4 ST Input/output or external clock input for Timer0 Output is open drain type RA5/AN4(1) bit5 TTL Input/output or analog input Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: RA5 is reserved on the 28-pin devices, maintain this bit clear. TABLE 3-2 Address Name 05h SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 PORTA(1) — — 85h TRISA(1) — — 9Fh ADCON1 ADFM VCFG2 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 PORTA Data Direction Register VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --11 1111 --11 1111 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: PORTA<5>, TRISA<5> are reserved on the 28-pin devices, maintain these bits clear. DS30275B-page 28 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 29 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.2 PORTB and the TRISB Register The RB1 pin is multiplexed with the SSP module slave select (RB1/SS). PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin. EXAMPLE 3-1: INITIALIZING PORTB BCF CLRF STATUS, RP0 PORTB BSF MOVLW STATUS, RP0 0xCF MOVWF TRISB ; ; ; ; ; ; ; ; ; ; ; BLOCK DIAGRAM OF RB1/SS PIN VDD RBPU(2) weak P pull-up Data Latch Data bus D WR Port Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. The RB0 pin is multiplexed with the external interrupt (RB0/INT). FIGURE 3-4: FIGURE 3-5: BLOCK DIAGRAM OF RB0 PIN Q I/O pin(1) CK TRIS Latch D Q WR TRIS TTL Input Buffer CK RD TRIS Q D EN RD Port SS input Schmitt Trigger Buffer RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). The RB2 pin is multiplexed with analog channel 8 (RB2/AN8). VDD RBPU(2) Data bus WR Port weak P pull-up Data Latch D Q BLOCK DIAGRAM OF RB2/AN8 PIN VDD RBPU(2) I/O pin(1) CK Data bus TRIS Latch D Q WR TRIS FIGURE 3-6: TTL Input Buffer CK WR Port weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS RD TRIS Q RD Port Analog input mode CK TTL Input Buffer D EN RD TRIS Q D RB0/INT Schmitt Trigger Buffer RD Port EN RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). To A/D converter RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 29 774.book Page 30 Tuesday, January 29, 2013 12:02 PM PIC16C77X The RB3 pin is multiplexed with analog channel 9 and the low voltage detect input (RB3/AN9/LVDIN) FIGURE 3-7: BLOCK DIAGRAM OF RB3/AN9/LVDIN PIN VDD RBPU(2) Data bus WR Port weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS b) Q Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. RD TRIS RD Port This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) Analog input mode or LVD input TTL mode Input Buffer CK Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). D The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. EN To A/D converter and LVD reference input RD Port FIGURE 3-8: Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). BLOCK DIAGRAM OF RB7:RB4 PINS VDD RBPU(2) Data bus WR Port weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS TTL Input Buffer CK RD TRIS Q Latch D EN RD Port ST Buffer Q1 Set RBIF From other RB7:RB4 pins Q D RD Port EN Q3 RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). DS30275B-page 30 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 31 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 3-3 PORTB FUNCTIONS Name Bit# Buffer RB0/INT bit0 TTL/ST(1) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1/SS bit1 TTL/ST(3) Input/output pin or SSP slave select. Internal software programmable weak pull-up. RB2/AN8 bit2 TTL Input/output pin or analog input8. Internal software programmable weak pull-up. RB3/AN9/LVDIN bit3 TTL Input/output pin or analog input9 or Low-voltage detect input. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when used as the SSP slave select. TABLE 3-4 Address SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name 06h, 106h PORTB 86h, 186h TRISB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 11xx uuuu 11uu 1111 1111 1111 1111 PORTB Data Direction Register 81h, 181h OPTION_REG RBPU INTEDG 9Fh ADCON1 ADFM VCFG2 T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 31 774.book Page 32 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.3 PORTC and the TRISC Register PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin. PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify-write instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. EXAMPLE 3-1: INITIALIZING PORTC BCF CLRF STATUS, RP0 PORTC BSF MOVLW STATUS, RP0 0xCF MOVWF TRISC DS30275B-page 32 ; ; ; ; ; ; ; ; ; ; ; Select Bank 0 Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs FIGURE 3-9: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT D VDD 0 Q P 1 CK Q Data Latch WR TRIS D CK I/O pin(1) Q Q N TRIS Latch VSS Schmitt Trigger RD TRIS Peripheral OE(3) RD PORT Peripheral input Q D EN Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 33 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 3-5 PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous transmit or Synchronous clock RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous receive or Synchronous data Legend: ST = Schmitt Trigger input TABLE 3-6 Address Name 07h PORTC 87h TRISC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PORTC Data Direction Register Legend: x = unknown, u = unchanged. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 33 774.book Page 34 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.4 PORTD and TRISD Registers This section is applicable to the 40/44-pin devices only. FIGURE 3-10: PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Data bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. WR PORT PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. D Q I/O pin(1) CK Data Latch D WR TRIS Q Schmitt Trigger input buffer CK TRIS Latch RD TRIS Q D EN EN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 3-7 Name PORTD FUNCTIONS Bit# Buffer Type (1) Function RD0/PSP0 bit0 ST/TTL Input/output port pin or parallel slave port bit0 RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1 RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2 RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3 RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4 RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5 RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6 RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7 Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode. TABLE 3-8 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 08h PORTD RD7 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE 0000 -111 0000 -111 IBF RD6 OBF IBOV PSPMODE — PORTE Data Direction Bits Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD. DS30275B-page 34 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 35 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.5 PORTE and TRISE Register FIGURE 3-11: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) This section is applicable to the 40/44-pin devices only. Data bus PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. D WR PORT Q I/O pin(1) CK Data Latch I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). Ensure ADCON1 is configured for digital I/O. In this mode the input buffers are TTL. D WR TRIS Q TRIS Latch Figure 3-12 shows the TRISE register, which also controls the parallel slave port operation. RD TRIS PORTE pins are multiplexed with analog inputs. When selected as an analog input, these pins will read as '0's. Q TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: Schmitt Trigger input buffer CK D ENEN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. On a Power-on Reset these pins are configured as analog inputs. FIGURE 3-12: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — bit2 bit1 bit0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4: PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' PORTE Data Direction Bits bit 2: Bit2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 35 774.book Page 36 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 3-9 PORTE FUNCTIONS Name Bit# Buffer Type Function (1) Input/output port pin or read control input in parallel slave port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) Input/output port pin or write control input in parallel slave port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected) RE0/RD/AN5 bit0 ST/TTL RE1/WR/AN6 bit1 ST/TTL(1) RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port mode or analog input: CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode. TABLE 3-10 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 09h PORTE — — — — — 89h TRISE IBF OBF IBOV PSPMODE — 9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RE2 RE1 RE0 ---- -xxx ---- -uuu PORTE Data Direction Bits 0000 -111 0000 -111 PCFG2 0000 0000 0000 0000 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE. DS30275B-page 36 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 37 Tuesday, January 29, 2013 12:02 PM PIC16C77X 3.6 Parallel Slave Port FIGURE 3-13: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is implemented on the 40/44-pin devices only. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. Data bus D WR PORT Q RDx pin CK TTL It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The configuration bits, PCFG3:PCFG0 (ADCON1<3:0>) must be configured to make pins RE2:RE0 as digital I/O. Q RD PORT D EN EN One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. Read RD TTL Chip Select TTL CS TTL WR Write Note: I/O pin has protection diodes to VDD and VSS. FIGURE 3-14: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 37 774.book Page 38 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 3-15: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 3-11 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Value on: POR, BOR Value on all other resets xxxx xxxx uuuu uuuu ---- -xxx ---- -uuu Bit 2 Bit 1 Bit 0 RE2 RE1 RE0 PORTE Data Direction Bits 0000 -111 0000 -111 08h PORTD 09h PORTE Port data latch when written: Port pins when read — — — — — 89h TRISE IBF OBF IBOV PSPMODE — 0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 ADFM VCFG2 VCFG1 TXIE VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. DS30275B-page 38 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 39 Tuesday, January 29, 2013 12:02 PM PIC16C77X 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). The Timer0 module timer/counter has the following features: • • • • • • 4.2 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). 4.1 Prescaler The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Timer0 Operation Timer0 can operate as a timer or as a counter. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in below. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. FIGURE 4-1: TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 1 1 Programmable Prescaler RA4/T0CKI pin 0 8 Sync with Internal clocks TMR0 PSout (2 cycle delay) T0SE 3 PS2, PS1, PS0 PSA T0CS Set interrupt flag bit T0IF on overflow Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram). 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 39 774.book Page 40 Tuesday, January 29, 2013 12:02 PM PIC16C77X 4.2.1 4.3 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. Note: The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. To avoid an unintended device RESET, a specific instruction sequence (shown in the PICmicro™ Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. FIGURE 4-2: Timer0 Interrupt BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus CLKOUT (=Fosc/4) 0 RA4/T0CKI pin 8 M U X 1 M U X 0 1 SYNC 2 Cycles TMR0 reg T0SE T0CS 0 1 Watchdog Timer Set flag bit T0IF on Overflow PSA 8-bit Prescaler M U X 8 8 - to - 1MUX PS2:PS0 PSA 1 0 WDT Enable bit MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0 Address Name 01h,101h TMR0 0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h OPTION_REG 85h TRISA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0IE INTE RBIE T0IF INTF RBIF T0CS T0SE PSA PS2 PS1 PS0 Timer0 module’s register GIE PEIE RBPU INTEDG — — PORTA Data Direction Register Value on: POR, BOR Value on all other resets xxxx xxxx uuuu uuuu 0000 000x 0000 000u 1111 1111 1111 1111 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. DS30275B-page 40 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 41 Tuesday, January 29, 2013 12:02 PM PIC16C77X 5.0 TIMER1 MODULE 5.1 The Timer1 module timer/counter has the following features: • 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) • Readable and writable (Both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • Reset from CCP module trigger Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Figure 5-3 is a simplified block diagram of the Timer1 module. Additional information on timer modules is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). FIGURE 5-1: Timer1 Operation In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal “reset input”. This reset can be generated by the CCP module (Section 7.0). T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 — — R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN R/W-0 T1SYNC R/W-0 R/W-0 TMR1CS TMR1ON bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 41 774.book Page 42 Tuesday, January 29, 2013 12:02 PM PIC16C77X 5.1.1 TIMER1 COUNTER OPERATION In this mode, Timer1 is being incremented via an external source. Increments occur on a rising edge. After Timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. FIGURE 5-2: TIMER1 INCREMENTING EDGE T1CKI (Default high) T1CKI (Default low) Note: Arrows indicate counter increments. FIGURE 5-3: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1H Synchronized clock input 0 TMR1 TMR1L 1 TMR1ON on/off T1SYNC T1OSC RC0/T1OSO/T1CKI RC1/T1OSI 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Synchronize Prescaler 1, 2, 4, 8 det 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS30275B-page 42 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 43 Tuesday, January 29, 2013 12:02 PM PIC16C77X 5.2 Timer1 Oscillator 5.3 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. TABLE 5-1 Osc Type CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Freq C1 Timer1 Interrupt The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>). 5.4 Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). C2 Note: 32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only. The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). LP Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM 100 kHz Epson C-2 100.00 KC-P 20 PPM 200 kHz STD XTL 200.000 kHz 20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. TABLE 5-2 In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1. REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 0Bh,8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON --00 0000 --uu uuuu Legend: Note 1: — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. These bits are reserved on the 28-pin devices, always maintain these bits clear. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 43 774.book Page 44 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 44 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 45 Tuesday, January 29, 2013 12:02 PM PIC16C77X 6.0 TIMER2 MODULE 6.1 The Timer2 module timer has the following features: • • • • • • • Timer2 Operation Timer2 can be used as the PWM time-base for PWM mode of the CCP module. 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (Both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). Timer2 has a control register, shown in Figure 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 6-2 is a simplified block diagram of the Timer2 module. Additional information on timer modules is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. FIGURE 6-1: U-0 — T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON R/W-0 R/W-0 T2CKPS1 T2CKPS0 bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 1999-2013 Microchip Technology Inc. Advance Information R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset DS30275B-page 45 774.book Page 46 Tuesday, January 29, 2013 12:02 PM PIC16C77X 6.2 Timer2 Interrupt FIGURE 6-2: Sets flag bit TMR2IF The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset. 6.3 TIMER2 BLOCK DIAGRAM TMR2 output (1) Reset Postscaler 1:1 to 1:16 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock. EQ 4 Prescaler 1:1, 1:4, 1:16 TMR2 reg FOSC/4 2 Comparator PR2 reg Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. TABLE 6-1 Address REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Name 0Bh,8Bh, INTCON 10Bh,18Bh Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 12h T2CON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h Legend: Note 1: PR2 0000 0000 0000 0000 Timer2 module’s register — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON 1111 1111 1111 1111 Timer2 Period Register x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. These bits are reserved on the 28-pin, always maintain these bits clear. DS30275B-page 46 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 47 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.0 CAPTURE/COMPARE/PWM (CCP) MODULE(S) CCP2 Module Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the special trigger. Therefore, operation of a CCP module in the following sections is described with respect to CCP1. Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. Additional information on the CCP module is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). TABLE 7-1 Table 7-2 shows the interaction of the CCP modules. CCP1 Module Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 7-2 CCP Mode Timer Resource Capture Compare PWM Timer1 Timer1 Timer2 INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Capture CCP MODE - TIMER RESOURCE Capture Interaction Same TMR1 time-base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None FIGURE 7-1: U-0 — bit7 U-0 — CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh) R/W-0 CCPxX R/W-0 R/W-0 CCPxY CCPxM3 R/W-0 CCPxM2 R/W-0 R/W-0 CCPxM1 CCPxM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 47 774.book Page 48 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.1 Capture Mode 7.1.4 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 7.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. FIGURE 7-2: CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. EXAMPLE 7-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW CCP1CON NEW_CAPT_PS MOVWF CCP1CON ;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value CAPTURE MODE OPERATION BLOCK DIAGRAM Prescaler 1, 4, 16 Set flag bit CCP1IF (PIR1<2>) RC2/CCP1 Pin CCPR1H and edge detect CCPR1L Capture Enable TMR1H TMR1L CCP1CON<3:0> Q’s 7.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 7.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode. DS30275B-page 48 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 49 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.2 Compare Mode 7.2.1 In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • driven High • driven Low • remains Unchanged Note: 7.2.2 The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. FIGURE 7-3: CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. COMPARE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Comparator TMR1H SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). 7.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated which may be used to initiate an action. Special Event Trigger (CCP2 only) Q S Output Logic match RC2/CCP1 R Pin TRISC<2> Output Enable CCP1CON<3:0> Mode Select TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 7.2.3 Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. TMR1L The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCP2 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). Note: TABLE 7-3 Address The special event trigger from the CCP2 module will not set interrupt flag bit TMR1IF (PIR1<0>). REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Name 0Bh,8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF Value on: POR, BOR Value on all other resets 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM register1 (LSB) 16h CCPR1H Capture/Compare/PWM register1 (MSB) 17h CCP1CON — — CCP1X CCP1Y xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, always maintain these bits clear. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 49 774.book Page 50 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.3 PWM Mode 7.3.1 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 7-4 shows a simplified block diagram of the CCP module in PWM mode. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3. FIGURE 7-4: SIMPLIFIED PWM BLOCK DIAGRAM PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 6.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. CCP1CON<5:4> Duty cycle registers CCPR1L 7.3.2 CCPR1H (Slave) R Comparator Q RC2/CCP1 TMR2 (Note 1) S TRISC<2> Comparator Clear Timer, CCP1 pin and latch D.C. PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base. A PWM output (Figure 7-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/ period). FIGURE 7-5: PWM OUTPUT PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) • Tosc • (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: Period log = TMR2 = PR2 Note: TMR2 = Duty Cycle DS30275B-page 50 FOSC FPWM ) bits log(2) Duty Cycle TMR2 = PR2 ( If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared. For an example PWM period and duty cycle calculation, see the PICmicro™ Mid-Range Reference Manual, (DS33023). Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 51 Tuesday, January 29, 2013 12:02 PM PIC16C77X 7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. TABLE 7-4 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 7-5 Address 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 208.3 kHz 1 0x1F 7 1 0x17 5.5 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name 0Bh,8Bh, INTCON 10Bh,18Bh Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’s period register 1111 1111 1111 1111 12h T2CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) 16h CCPR1H Capture/Compare/PWM register1 (MSB) 17h CCP1CON — — 0000 0000 0000 0000 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 — CCP1X CCP1Y xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, always maintain these bits clear. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 51 774.book Page 52 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 52 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 53 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I 2C™) 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 53 774.book Page 54 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h) R/W-0 R/W-0 SMP CKE bit7 R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit0 R =Readable bit W =Writable bit U =Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SMP: Sample bit SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode In I2C master or slave mode: 1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0= Slew rate control enabled for high speed mode (400 kHz) bit 6: CKE: SPI Clock Edge Select (Figure 8-6, Figure 8-8, and Figure 8-9) CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or not ACK bit. In I2C slave mode: 1 = Read 0 = Write In I2C master mode: 1 = Transmit is in progress 0 = Transmit is not in progress. Or’ing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty DS30275B-page 54 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 55 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-2: R/W-0 WCOL bit7 SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit0 R = Readable bit W = Writable bit - n = Value at POR reset bit 7: WCOL: Write Collision Detect bit Master Mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave Mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. In slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software). 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. (Must be cleared in software). 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output. In SPI mode 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C slave mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) In I2C master mode Unused in this mode bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = FOSC/4 0001 = SPI master mode, clock = FOSC/16 0010 = SPI master mode, clock = FOSC/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) ) 1xx1 = Reserved 1x1x = Reserved 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 55 774.book Page 56 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-3: R/W-0 GCEN bit7 SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h) R/W-0 AKSTAT R/W-0 AKDT R/W-0 AKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit0 R =Readable bit W =Writable bit U =Unimplemented bit, Read as ‘0’ - n =Value at POR reset bit 7: GCEN: General Call Enable bit (In I2C slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR. 0 = General call address disabled. bit 6: AKSTAT: Acknowledge Status bit (In I2C master mode only) In master transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5: AKDT: Acknowledge Data bit (In I2C master mode only) In master receive mode: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 1 = Not Acknowledge 0 = Acknowledge bit 4: AKEN: Acknowledge Sequence Enable bit (In I2C master mode only). In master receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3: RCEN: Receive Enable bit (In I2C master mode only). 1 = Enables Receive mode for I2C 0 = Receive idle bit 2: PEN: Stop Condition Enable bit (In I2C master mode only). SCK release control 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition idle bit 1: RSEN: Repeated Start Condition Enabled bit (In I2C master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition idle. bit 0: SEN: Start Condition Enabled bit (In I2C master mode only) 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition idle. Note: For bits AKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS30275B-page 56 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 57 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1 SPI Mode FIGURE 8-4: The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: MSSP BLOCK DIAGRAM (SPI MODE) Internal data bus Read • Serial Data Out (SDO) • Serial Data In (SDI) • Serial Clock (SCK) Write SSPBUF reg Additionally, a fourth pin may be used when in a slave mode of operation: • Slave Select (SS) 8.1.1 SSPSR reg SDI OPERATION shift clock bit0 SDO When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • • • • Master Mode (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data input sample phase (middle or end of data output time) • Clock edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select Mode (Slave mode only) Figure 8-4 shows the block diagram of the MSSP module when in SPI mode. SS Control Enable SS Edge Select 2 Clock Select SCK SSPM3:SSPM0 SMP:CKE 4 TMR2 output 2 2 Edge Select Prescaler TOSC 4, 16, 64 Data to TX/RX in SSPSR Data direction bit The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit BF (SSPSTAT<0>) and the interrupt flag bit SSPIF (PIR1<3>) are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL (SSPCON<7>) will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>), indicates when the SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the MSSP Interrupt is used to 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 57 774.book Page 58 Tuesday, January 29, 2013 12:02 PM PIC16C77X determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 8-1 shows the loading of the SSPBUF (SSPSR) for data transmission. EXAMPLE 8-1: LOADING THE SSPBUF (SSPSR) REGISTER BSF STATUS, RP0 LOOP BTFSS SSPSTAT, BF GOTO BCF MOVF LOOP STATUS, RP0 SSPBUF, W MOVWF RXDATA MOVF TXDATA, W MOVWF SSPBUF ;Specify Bank 1 ;Has data been ;received ;(transmit ;complete)? ;No ;Specify Bank 0 ;W reg = contents ;of SSPBUF ;Save in user RAM ;W reg = contents ; of TXDATA ;New data to xmit 8.1.3 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON registers, and then set bit SSPEN. This configures the FIGURE 8-5: • SDI is automatically controlled by the SPI module • SDO must have TRISC<5> cleared • SCK (Master mode) must have TRISC<3> cleared • SCK (Slave mode) must have TRISC<3> set • SS must have TRISA<5> set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions. 8.1.2 SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: TYPICAL CONNECTION Figure 8-5 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: • Master sends data—Slave sends dummy data • Master sends data—Slave sends data • Master sends dummy data—Slave sends data SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) SDI Shift Register (SSPSR) MSb SDO LSb Shift Register (SSPSR) MSb LSb Serial Clock SCK SCK PROCESSOR 1 DS30275B-page 58 PROCESSOR 2 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 59 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1.4 Figure 8-6, Figure 8-8, and Figure 8-9 where the MSb is transmitted first. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 8-5) is to broadcast data by the software protocol. • • • • In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI module is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a “line activity monitor”. This allows a maximum bit clock frequency (at 20 MHz) of 8.25 MHz. Figure 8-6 shows the waveforms for Master mode. When CKE = 1, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give waveforms for SPI communication as shown in FIGURE 8-6: FOSC/4 (or TCY) FOSC/16 (or 4 • TCY) FOSC/64 (or 16 • TCY) Timer2 output/2 SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 clock modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDO (CKE = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit0 bit7 Input Sample (SMP = 0) SDI (SMP = 1) bit0 bit7 Input Sample (SMP = 1) SSPIF Next Q4 cycle after Q2 SSPSR to SSPBUF 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 59 774.book Page 60 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1.5 SLAVE MODE In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched the interrupt flag bit SSPIF (PIR1<3>) is set. While in slave mode the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in sleep mode, the slave can transmit/receive data. When a byte is received the device will wake-up from sleep. 8.1.6 SLAVE SELECT SYNCHRONIZATION The SS pin allows a synchronous slave mode. The SPI must be in slave mode with SS pin control enabled (SSPCON<3:0> = 0100). The pin must not be driven low for the SS pin to function as an input. TRISA<5> must be set. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the FIGURE 8-7: SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application. Note: When the SPI module is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to VDD. Note: If the SPI is used in Slave Mode with CKE = '1', then SS pin control must be enabled. When the SPI module resets, the bit counter is forced to 0. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit6 bit7 bit0 bit0 bit7 bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2 SSPSR to SSPBUF DS30275B-page 60 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 61 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-8: SPI SLAVE MODE WAVEFORM (CKE = 0) SS optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit0 bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2 SSPSR to SSPBUF FIGURE 8-9: SPI SLAVE MODE WAVEFORM (CKE = 1) SS not optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit0 bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2 SSPSR to SSPBUF 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 61 774.book Page 62 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.1.7 8.1.8 SLEEP OPERATION EFFECTS OF A RESET A reset disables the MSSP module and terminates the current transfer. In master mode all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. In slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the device to be placed in sleep mode, and data to be shifted into the SPI transmit/receive shift register. When all 8-bits have been received, the MSSP interrupt flag bit will be set and if enabled will wake the device from sleep. TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION Address Name 0Bh, 8Bh, 10Bh,18Bh INTCON 0Ch PIR1 8Ch PIE1 13h SSPBUF 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 94h SSPSTAT SMP CKE D/A P S R/W UA Legend: Note 1: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. These bits are reserved on the 28-pin devices, always maintain these bits clear. DS30275B-page 62 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 63 Tuesday, January 29, 2013 12:02 PM PIC16C77X MSSP I 2C Operation 8.2 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. FIGURE 8-11: I2C MASTER MODE BLOCK DIAGRAM Internal data bus Read SSPADD<6:0> 7 Write Baud Rate Generator Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment." SSPBUF reg SCL A "glitch" filter is on the SCL and SDA pins when the pin is an input. This filter operates in both the 100 kHz and 400 kHz modes. In the 100 kHz mode, when these pins are an output, there is a slew rate control of the pin that is independant of device frequency. shift clock SSPSR reg SDA MSb LSb FIGURE 8-10: I2C SLAVE MODE BLOCK DIAGRAM Match detect Internal data bus SSPADD reg Read Write Start and Stop bit detect / generate SSPBUF reg SCL shift clock SSPSR reg SDA MSb LSb Match detect Addr Match Set/Clear S bit and Clear/Set P bit (SSPSTAT reg) and Set SSPIF Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin, which is the data. The SDA and SCL pins that are automatically configured when the I2C mode is enabled. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). The MSSP module has six registers for I2C operation. They are the: SSPADD reg Start and Stop bit detect Addr Match Set, Reset S, P bits (SSPSTAT reg) • • • • • SSP Control Register (SSPCON) SSP Control Register2 (SSPCON2) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible • SSP Address Register (SSPADD) The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: • I 2C Slave mode (7-bit address) • I 2C Slave mode (10-bit address) • I 2C Master mode, clock = OSC/4 (SSPADD +1) Before selecting any I 2C mode, the SCL and SDA pins must be programmed to inputs by setting the appropriate TRIS bits. Selecting an I 2C mode, by setting the SSPEN bit, enables the SCL and SDA pins to be used as the clock and data lines in I 2C mode. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 63 774.book Page 64 Tuesday, January 29, 2013 12:02 PM PIC16C77X The SSPSTAT register gives the status of the data transfer. This information includes detection of a START (S) or STOP (P) bit, specifies if the received byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. SSPBUF is the register to which the transfer data is written to or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the complete byte is received, it is transferred to the SSPBUF register and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register is read, a receiver overflow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the SSPSR is lost. The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of the address needs to be loaded (A7:A0). 8.2.1 SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs. The MSSP module will override the input state with the output data when required (slavetransmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. 8.2.1.1 Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) 1. 2. 3. a) 4. b) If the BF bit is set, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF and SSPOV are set. Table 8-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low time for proper operation. The high and low times of the I2C specification as well as the requirement of the MSSP module is shown in timing parameter #100 and parameter #101 of the Electrical Specifications. DS30275B-page 64 The SSPSR register value is loaded into the SSPBUF register on the falling edge of the 8th SCL pulse. The buffer full bit, BF is set on the falling edge of the 8th SCL pulse. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) - on the falling edge of the 9th SCL pulse. In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmitter: There are certain conditions that will cause the MSSP module not to give this ACK pulse. These are if either (or both): The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. ADDRESSING 5. 6. 7. 8. 9. Receive first (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address. This will clear bit UA and release the SCL line. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated Start condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Note: Advance Information Following the Repeated Start condition (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. The user does not update the SSPADD for the second half of the address. 1999-2013 Microchip Technology Inc. 774.book Page 65 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.1.2 SLAVE RECEPTION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the received byte. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. Note: The SSPBUF will be loaded if the SSPOV bit is set and the BF flag is cleared. If a read of the SSPBUF was performed, but the user did not clear the state of the SSPOV bit before the next receive occured. The ACK is not sent and the SSPBUF is updated. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. TABLE 8-2 DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received BF SSPOV SSPSR SSPBUF Generate ACK Pulse 0 1 1 0 0 0 1 1 Yes No No Yes Yes No No No Note 1: Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes Shaded cells show the conditions where the user software did not properly clear the overflow condition. 8.2.1.3 An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in software, and the SSPSTAT register is used to determine the status of the byte tranfer. The SSPIF flag bit is set on the falling edge of the ninth clock pulse. SLAVE TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and the SCL pin is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 8-13). As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the not ACK is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should be enabled by setting the CKP bit. FIGURE 8-12: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) R/W=0 ACK Receiving Address A7 A6 A5 A4 A3 A2 A1 SDA SCL S 1 2 3 4 5 6 7 Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 8 9 1 2 3 4 5 6 7 8 9 Not Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 8 7 SSPIF 9 P Bus Master terminates transfer BF (SSPSTAT<0>) Cleared in software SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 65 774.book Page 66 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-13: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) R/W = 1 ACK Receiving Address SDA SCL A7 S A6 1 2 Data in sampled A5 A4 A3 A2 A1 3 4 5 6 7 D7 8 9 R/W = 0 Not ACK Transmitting Data 1 SCL held low while CPU responds to SSPIF D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P SSPIF BF (SSPSTAT<0>) cleared in software SSPBUF is written in software From SSP interrupt service routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) DS30275B-page 66 Advance Information 1999-2013 Microchip Technology Inc. 1999-2013 Microchip Technology Inc. S 1 Advance Information UA (SSPSTAT<1>) 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK Receive First Byte of Address R/W = 0 1 BF (SSPSTAT<0>) (PIR1<3>) SSPIF SCL SDA 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated. 6 A6 A5 A4 A3 A2 A1 8 A0 Receive Second Byte of Address Dummy read of SSPBUF to clear BF flag A7 Clock is held low until update of SSPADD has taken place 9 ACK 2 3 1 4 1 Cleared in software 1 1 Cleared by hardware when SSPADD is updated. Dummy read of SSPBUF to clear BF flag Sr 1 5 0 6 7 A9 A8 Receive First Byte of Address 8 9 R/W=1 ACK 1 3 4 5 6 7 8 9 ACK P Write of SSPBUF initiates transmit Cleared in software Bus Master terminates transfer CKP has to be set for clock to be released 2 D4 D3 D2 D1 D0 Transmitting Data Byte D7 D6 D5 Master sends NACK Transmit is complete 774.book Page 67 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-14: I2C SLAVE-TRANSMITTER (10-BIT ADDRESS) DS30275B-page 67 DS30275B-page 68 S 1 1 Advance Information UA (SSPSTAT<1>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF SCL SDA 2 1 3 1 5 0 6 A9 7 A8 UA is set indicating that the SSPADD needs to be updated 8 9 ACK R/W = 0 SSPBUF is written with contents of SSPSR 4 1 Receive First Byte of Address 1 3 A5 4 A4 Cleared in software 2 A6 5 A3 6 A2 7 A1 8 A0 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address. Dummy read of SSPBUF to clear BF flag A7 Receive Second Byte of Address Clock is held low until update of SSPADD has taken place 9 ACK 3 D5 4 D4 5 D3 Cleared in software 2 D6 Cleared by hardware when SSPADD is updated with high byte of address. Dummy read of SSPBUF to clear BF flag 1 D7 Receive Data Byte 6 D2 7 D1 8 D0 9 ACK R/W = 1 Read of SSPBUF clears BF flag P Bus Master terminates transfer 774.book Page 68 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-15: I2C SLAVE-RECEIVER (10-BIT ADDRESS) 1999-2013 Microchip Technology Inc. 774.book Page 69 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.2 If the general call address matches, the SSPSR is transfered to the SSPBUF, the BF flag is set (eighth bit), and on the falling edge of the ninth bit (ACK bit) the SSPIF flag is set. GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. When the interrupt is serviced. The source for the interrupt can be checked by reading the contents of the SSPBUF to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when GCEN is set while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the UA bit will not be set, and the slave will begin receiving data after the acknowledge (Figure 8-16). The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all 0’s with R/W = 0 The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7> is set). Following a start-bit detect, 8-bits are shifted into SSPSR and the address is compared against SSPADD, and is also compared to the general call address, fixed in hardware. FIGURE 8-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE) Address is compared to General Call Address after ACK, set interrupt flag R/W = 0 ACK D7 General Call Address SDA Receiving data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 SCL S 1 2 3 4 5 6 7 8 9 1 9 SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is read SSPOV (SSPCON<6>) '0' GCEN (SSPCON2<7>) '1' 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 69 774.book Page 70 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.3 8.2.4 SLEEP OPERATION 2 EFFECTS OF A RESET A reset diables the SSP module and terminates the current transfer. While in sleep mode, the I C module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep (if the SSP interrupt is enabled). REGISTERS ASSOCIATED WITH I2C OPERATION TABLE 8-3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT 0Bh, 8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0000 0000 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 LVDIF — — — BCLIF — — CCP2IF 0--- 0--0 0--- 0--0 8Dh PIE2 LVDIE — — — BCLIE — — CCP2IE 0--- 0--0 0--- 0--0 13h SSPBUF xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 91h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: Note 1: 2: Synchronous Serial Port Receive Buffer/Transmit Register x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode. These bits are reserved on the 28-pin devices, always maintain these bits clear. These bits are reserved on these devices, always maintain these bits clear. DS30275B-page 70 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 71 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.5 In master mode, the SCL and SDA lines are manipulated by the MSSP hardware. MASTER MODE Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle with both the S and P bits clear. The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): • • • • • START condition STOP condition Data transfer byte transmitted/received Acknowledge transmit Repeated Start FIGURE 8-17: SSP BLOCK DIAGRAM (I2C MASTER MODE) SSPM3:SSPM0, SSPADD<6:0> Internal data bus Read Write SSPBUF shift clock SDA SDA in SSPSR SCL in Bus Collision 1999-2013 Microchip Technology Inc. LSb Start bit, Stop bit, Acknowledge Generate Start bit detect, Stop bit detect Write collision detect Clock Arbitration State counter for end of XMIT/RCV clock cntl SCL Receive Enable MSb clock arbitrate/WCOL detect (hold off clock source) Baud rate generator Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset AKSTAT, PEN (SSPCON2) Advance Information DS30275B-page 71 774.book Page 72 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.6 8.2.7.4 MULTI-MASTER OPERATION In multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. In multi-master operation, the SDA line must be monitored, for abitration, to see if the signal level is the expected output level. This check is performed in hardware, with the result placed in the BCLIF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition 8.2.7 I2C MASTER OPERATION SUPPORT Master Mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. Once master mode is enabled, the user has six options. - Assert a start condition on SDA and SCL. - Assert a Repeated Start condition on SDA and SCL. - Write to the SSPBUF register initiating transmission of data/address. - Generate a stop condition on SDA and SCL. - Configure the I2C port to receive data. - Generate an Acknowledge condition at the end of a received byte of data. I2C MASTER MODE OPERATION The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic '0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master receive mode the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case the R/W bit will be logic '1'. Thus the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial data is received via SDA while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for SPI mode operation is now used to set the SCL clock frequency for either 100 kHz, 400 kHz, or 1 MHz I2C operation. The baud rate generator reload value is contained in the lower 7 bits of the SSPADD register. The baud rate generator will automatically begin counting on a write to the SSPBUF. Once the given operation is complete (i.e. transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state A typical transmit sequence would go as follows: Note: The MSSP Module, when configured in I2C Master Mode, does not allow queueing of events. For instance: The user is not allowed to initiate a start condition, and immediately write the SSPBUF register to initiate transmission before the START condition is complete. In this case the SSPBUF will not be written to, and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. a) b) c) d) e) f) g) h) DS30275B-page 72 The user generates a Start Condition by setting the START enable bit (SEN) in SSPCON2. SSPIF is set. The module will wait the required start time before any other operation takes place. The user loads the SSPBUF with address to transmit. Address is shifted out the SDA pin until all 8 bits are transmitted. The MSSP Module shifts in the ACK bit from the slave device, and writes its value into the SSPCON2 register ( SSPCON2<6>). The module generates an interrupt at the end of the ninth clock cycle by setting SSPIF. The user loads the SSPBUF with eight bits of data. DATA is shifted out the SDA pin until all 8 bits are transmitted. Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 73 Tuesday, January 29, 2013 12:02 PM PIC16C77X i) The MSSP Module shifts in the ACK bit from the slave device, and writes its value into the SSPCON2 register ( SSPCON2<6>). The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user generates a STOP condition by setting the STOP enable bit PEN in SSPCON2. Interrupt is generated once the STOP condition is complete. j) k) l) 8.2.8 BAUD RATE GENERATOR In I2C master mode, the BRG is reloaded automatically. If Clock Arbitration is taking place for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 8-19). FIGURE 8-18: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 Reload SCL Control 2 In I C master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 8-18). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clock. CLKOUT Reload BRG Down Counter Fosc/4 FIGURE 8-19: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL de-asserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements (on Q2 and Q4 cycles) BRG value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place, and BRG starts its count. BRG reload 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 73 774.book Page 74 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.9 I2C MASTER MODE START CONDITION TIMING 8.2.9.5 If the user writes the SSPBUF when an START sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a START condition, the user sets the start condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0>, and starts its count. If SCL and SDA are both sampled high when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the START condition, and causes the S bit (SSPSTAT<3>) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the baud rate generator is suspended leaving the SDA line held low, and the START condition is complete. Note: WCOL STATUS FLAG Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete. If at the beginning of START condition the SDA and SCL pins are already sampled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag (BCLIF) is set, the START condition is aborted, and the I2C module is reset into its IDLE state. FIGURE 8-20: FIRST START BIT TIMING Set S bit (SSPSTAT<3>) Write to SEN bit occurs here. SDA = 1, SCL = 1 TBRG At completion of start bit, Hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 2nd Bit 1st Bit SDA TBRG SCL TBRG S DS30275B-page 74 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 75 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-21: START CONDITION FLOWCHART SSPEN = 1, SSPCON<3:0> = 1000 Idle Mode SEN (SSPCON2<0> = 1) Bus collision detected, Set BCLIF, Release SCL, Clear SEN No SDA = 1? SCL = 1? Yes Load BRG with SSPADD<6:0> No No No Yes SDA = 0? SCL= 0? Yes BRG Rollover? Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0>, Set S bit. No SCL = 0? Yes No BRG rollover? Yes Reset BRG Force SCL = 0, Start Condition Done, Clear SEN and set SSPIF 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 75 774.book Page 76 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.10 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C module is in the idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<6:0>, and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin will be de-asserted (brought high). When SCL is sampled high the baud rate generator is re-loaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA is low) for one TBRG while SCL is high. Following this, the RSEN bit in the SSPCON2 register will be automatically cleared, and the baud rate generator is not reloaded, leaving the SDA pin held low. As soon as a start condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the baud rate generator has timed-out. Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 8.2.10.6 WCOL STATUS FLAG If the user writes the SSPBUF when a Repeated Start sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated Start condition is complete. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. Note 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low to high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". FIGURE 8-22: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, SCL(no change) SDA = 1, SCL = 1 TBRG At completion of start bit, hardware clear RSEN bit and set SSPIF TBRG TBRG 1st Bit SDA Write to SSPBUF occurs here. Falling edge of ninth clock End of Xmit TBRG SCL TBRG Sr = Repeated Start DS30275B-page 76 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 77 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-23: REPEATED START CONDITION FLOWCHART (PAGE 1) Start Idle Mode, SSPEN = 1, SSPCON<3:0> = 1000 B RSEN = 1 Force SCL = 0 No SCL = 0? Yes Release SDA, Load BRG with SSPADD<6:0> BRG rollover? No Yes Release SCL (Clock Arbitration) SCL = 1? No Yes Bus Collision, Set BCLIF, Release SDA, Clear RSEN No SDA = 1? Yes Load BRG with SSPADD<6:0> C 1999-2013 Microchip Technology Inc. A Advance Information DS30275B-page 77 774.book Page 78 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-24: REPEATED START CONDITION FLOWCHART (PAGE 2) B C A Yes No No No SDA = 0? SCL = 1? Yes BRG rollover? Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0> Set S No SCL = '0'? Yes Reset BRG DS30275B-page 78 Advance Information No BRG rollover? Yes Force SCL = 0, Repeated Start condition done, Clear RSEN, Set SSPIF. 1999-2013 Microchip Technology Inc. 774.book Page 79 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.11 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or either half of a 10-bit address is accomplished by simply writing a value to SSPBUF register. This action will set the buffer full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time spec). SCL is held low for one baud rate generator roll over count (TBRG). Data should be valid before SCL is released high (see Data setup time spec). When the SCL pin is released high, it is held that way for TBRG, the data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA allowing the slave device being addressed to respond with an ACK bit during the ninth bit time, if an address match occurs or if data was received properly. The status of ACK is read into the AKDT on the falling edge of the ninth clock. If the master receives an acknowledge, the acknowledge status bit (AKSTAT) is cleared. If not, the bit is set. After the ninth clock the SSPIF is set, and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF leaving SCL low and SDA unchanged (Figure 8-26). 8.2.11.7 BF STATUS FLAG In transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out. 8.2.11.8 WCOL STATUS FLAG If the user writes the SSPBUF when a transmit is already in progress (i.e. SSPSR is still shifting out a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 8.2.11.9 AKSTAT STATUS FLAG In transmit mode, the AKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an acknowledge (ACK = 0), and is set when the slave does not acknowledge (ACK = 1). A slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock the master will de-assert the SDA pin allowing the slave to respond with an acknowledge. On the falling edge of the ninth clock the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the AKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared, and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 79 774.book Page 80 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-25: MASTER TRANSMIT FLOWCHART Idle Mode Write SSPBUF Num_Clocks = 0, BF = 1 Force SCL = 0 Release SDA so slave can drive ACK, Force BF = 0 Yes Num_Clocks = 8? No Load BRG with SSPADD<6:0>, start BRG count Load BRG with SSPADD<6:0>, start BRG count, SDA = Current Data bit BRG rollover? BRG rollover? No No Yes Yes Force SCL = 1, Stop BRG Stop BRG, Force SCL = 1 (Clock Arbitration) SCL = 1? (Clock Arbitration) No SCL = 1? No Yes Yes SDA = Data bit? Read SDA and place into AKSTAT bit (SSPCON2<6>) No Bus collision detected Set BCLIF, hold prescale off, Clear XMIT enable Yes Load BRG with SSPADD<6:0>, count high time Load BRG with SSPADD<6:0>, count SCL high time No Rollover? Yes BRG rollover? No No SCL = 0? SDA = Data bit? No Yes Yes Yes Force SCL = 0, Set SSPIF Reset BRG Num_Clocks = Num_Clocks + 1 DS30275B-page 80 Advance Information 1999-2013 Microchip Technology Inc. 1999-2013 Microchip Technology Inc. S Advance Information R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 cleared in software 2 6 7 8 9 After start condition SEN cleared by hardware. SSPBUF written 1 D7 3 D5 4 D4 5 D3 6 D2 7 D1 SSPBUF is written in software 8 D0 cleared in software service routine From SSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address From slave clear AKSTAT bit SSPCON2<6> 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7 bit address and R/W start transmit A7 Transmit Address to Slave SEN = 0 Write SSPCON2<0> SEN = 1 START condition begins P Cleared in software 9 ACK AKSTAT in SSPCON2 = 1 774.book Page 81 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-26: I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS30275B-page 81 774.book Page 82 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.12 I2C MASTER MODE RECEPTION 8.2.12.10 BF STATUS FLAG Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: The SSP Module must be in an IDLE STATE before the RCEN bit is set, or the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag is set, the SSPIF is set, and the baud rate generator is suspended from counting, holding SCL low. The SSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag is automatically cleared. The user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit, AKEN (SSPCON2<4>). DS30275B-page 82 In receive operation, BF is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when SSPBUF is read. 8.2.12.11 SSPOV STATUS FLAG In receive operation, SSPOV is set when 8 bits are received into the SSPSR, and the BF flag is already set from a previous reception. 8.2.12.12 WCOL STATUS FLAG If the user writes the SSPBUF when a receive is already in progress (i.e. SSPSR is still shifting in a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 83 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-27: MASTER RECEIVER FLOWCHART Idle mode RCEN = 1 Num_Clocks = 0, Release SDA Force SCL=0, Load BRG w/ SSPADD<6:0>, start count BRG rollover? No Yes Release SCL (Clock Arbitration) SCL = 1? No Yes Sample SDA, Shift data into SSPSR Load BRG with SSPADD<6:0>, start count. BRG rollover? No Yes SCL = 0? No Yes Num_Clocks = Num_Clocks + 1 No Num_Clocks = 8? Yes Force SCL = 0, Set SSPIF, Set BF. Move contents of SSPSR into SSPBUF, Clear RCEN. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 83 DS30275B-page 84 S Advance Information AKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 Cleared in software 3 6 A6 A5 A4 A3 A2 Transmit Address to Slave SEN = 0 Write to SSPBUF occurs here Start XMIT Write to SSPCON2<0> (SEN = 1) Begin Start Condition 7 A1 8 9 R/W = 1 ACK ACK from Slave 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPIF interrupt at end of acknowledge sequence Data shifted in on falling edge of CLK 1 D7 D6 D5 D4 D3 D2 D1 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK P Set SSPIF interrupt at end of acknowledge sequence Bus Master terminates transfer Set P bit (SSPSTAT<4>) and SSPIF PEN bit = 1 written here SSPOV is set because SSPBUF is still full 8 D0 RCEN cleared automatically Set AKEN start acknowledge sequence SDA = AKDT = 1 Receiving Data from Slave RCEN = 1 start next receive ACK from Master SDA = AKDT = 0 Last bit is shifted into SSPSR and contents are unloaded into SSPBUF Cleared in software Set SSPIF interrupt at end of receive 4 Cleared in software 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN cleared automatically Master configured as a receiver by programming SSPCON2<3>, (RCEN = 1) Write to SSPCON2<4> to start acknowledge sequence SDA = AKDT (SSPCON2<5>) = 0 774.book Page 84 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-28: I 2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS) 1999-2013 Microchip Technology Inc. 774.book Page 85 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.13 ACKNOWLEDGE SEQUENCE TIMING rate generator counts for TBRG . The SCL pin is then pulled low. Following this, the AKEN bit is automatically cleared, the baud rate generator is turned off, and the SSP module then goes into IDLE mode. (Figure 829) An acknowledge sequence is enabled by setting the acknowledge sequence enable bit, AKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the acknowledge data bit is presented on the SDA pin. If the user wishes to generate an acknowledge, then the AKDT bit should be cleared. If not, the user should set the AKDT bit before starting an acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG), and the SCL pin is de-asserted (pulled high). When the SCL pin is sampled high (clock arbitration), the baud 8.2.13.13 WCOL STATUS FLAG If the user writes the SSPBUF when an acknowledege sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 8-29: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, Write to SSPCON2 AKEN = 1, AKDT = 0 AKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPIF Set SSPIF at the end of receive Cleared in software Cleared in software Set SSPIF at the end of acknowledge sequence Note: TBRG= one baud rate generator period. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 85 774.book Page 86 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-30: ACKNOWLEDGE FLOWCHART Idle mode Set AKEN Force SCL = 0 BRG rollover? Yes No No SCL = 0? Yes Yes Drive AKDT bit (SSPCON2<5>) onto SDA pin, Load BRG with SSPADD<6:0>, start count. SCL = 0? Reset BRG Force SCL = 0, Clear AKEN, Set SSPIF No No AKDT = 1? Yes No BRG rollover? Yes Yes Force SCL = 1 SDA = 1? No Bus collision detected, Set BCLIF, Release SCL, Clear AKEN No SCL = 1? (Clock Arbitration) Yes Load BRG with SSPADD <6:0>, start count. DS30275B-page 86 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 87 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.14 STOP CONDITION TIMING while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later the PEN bit is cleared and the SSPIF bit is set (Figure 8-31). A stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit PEN (SSPCON2<2>). At the end of a receive/transmit the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low . When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high Whenever the firmware decides to take control of the bus, it will first determine if the bus is busy by checking the S and P bits in the SSPSTAT register. If the bus is busy, then the CPU can be interrupted (notified) when a Stop bit is detected (i.e. bus is free). 8.2.14.14 WCOL STATUS FLAG If the user writes the SSPBUF when a STOP sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). FIGURE 8-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set Write to SSPCON2 Set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup stop condition. Note: TBRG = one baud rate generator period. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 87 774.book Page 88 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-32: STOP CONDITION FLOWCHART Idle Mode, SSPEN = 1, SSPCON<3:0> = 1000 PEN = 1 Start BRG Force SDA = 0 SCL doesn’t change BRG rollover? No SDA = 0? No Yes Release SDA, Start BRG Yes Start BRG BRG rollover? BRG rollover? No No Yes No P bit Set? Yes De-assert SCL, SCL = 1 Yes (Clock Arbitration) SCL = 1? Bus Collision detected, Set BCLIF, Clear PEN No SDA going from 0 to 1 while SCL = 1 Set SSPIF, Stop Condition done PEN cleared. Yes DS30275B-page 88 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 89 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.15 CLOCK ARBITRATION 8.2.16 Clock arbitration occurs when the master, during any receive, transmit, or repeated start/stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 8-33). SLEEP OPERATION While in sleep mode, the I2C module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep ( if the SSP interrupt is enabled). 8.2.17 EFFECTS OF A RESET A reset disables the SSP module and terminates the current transfer. FIGURE 8-33: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, Release SCL, If SCL = 1 Load BRG with SSPADD<6:0>, and start count to measure high time interval BRG overflow occurs, Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting clock high interval. SCL SCL line sampled once every machine cycle (Tosc 4). Hold off BRG until SCL is sampled high. SDA TBRG 1999-2013 Microchip Technology Inc. TBRG Advance Information TBRG DS30275B-page 89 774.book Page 90 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.18 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its IDLE state. (Figure 8-34). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. If a START, Repeated Start, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The Master will continue to monitor the SDA and SCL pins, and if a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when bus collision occurred. In multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared. FIGURE 8-34: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high data doesn’t match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt. BCLIF DS30275B-page 90 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 91 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.2.18.15 BUS COLLISION DURING A START CONDITION During a START condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the START condition (Figure 8-35). SCL is sampled low before SDA is asserted low. (Figure 8-36). b) During a START condition both the SDA and the SCL pins are monitored. If: while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 8-37). If however a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The baud rate generator is then reloaded and counts down to 0, and during this time, if the SCL pins is sampled as '0', a bus collision does not occur. At the end of the BRG count the SCL pin is asserted low. Note: the SDA pin is already low or the SCL pin is already low, then: the START condition is aborted, and the BCLIF flag is set, and the SSP module is reset to its IDLE state (Figure 8-35). The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low The reason that bus collision is not a factor during a START condition is that no two bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the START condition, and if the address is the same, arbitration must be allowed to continue into the data portion, REPEATED START, or STOP conditions. FIGURE 8-35: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1 SDA SCL Set SEN, enable start condition if SDA = 1, SCL=1 SEN cleared automatically because of bus collision. SSP module reset into idle state. SEN BCLIF SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1 SSPIF and BCLIF are cleared in software. S SSPIF SSPIF and BCLIF are cleared in software. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 91 774.book Page 92 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 8-36: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, Bus collision occurs, Set BCLIF. SEN SCL = 0 before BRG time out, Bus collision occurs, Set BCLIF. BCLIF Interrupts cleared in software. S '0' '0' SSPIF '0' '0' FIGURE 8-37: BRG RESET DUE TO SDA COLLISION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled low by other master. Reset BRG and assert SDA SCL S SCL pulled low after BRG Timeout SEN BCLIF '0' Set SEN, enable start sequence if SDA = 1, SCL = 1 S SSPIF SDA = 0, SCL = 1 Set SSPIF DS30275B-page 92 Advance Information Interrupts cleared in software. 1999-2013 Microchip Technology Inc. 774.book Page 93 Tuesday, January 29, 2013 12:02 PM PIC16C77X however SDA is sampled high then the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time. 8.2.18.16 BUS COLLISION DURING A REPEATED START CONDITION During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ’1’. If, however, SCL goes from high to low before the BRG times out and SDA has not already been asserted, then a bus collision occurs. In this case, another master is attempting to transmit a data ’1’ during the Repeated Start condition. When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0>, and counts down to 0. The SCL pin is then deasserted, and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e. another master is attempting to transmit a data ’0’). If If at the end of the BRG time out both SCL and SDA are still high, the SDA pin is driven low, the BRG is reloaded, and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete (Figure 8-38). FIGURE 8-38: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL RSEN BCLIF S '0' Cleared in software '0' SSPIF '0' '0' FIGURE 8-39: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, Set BCLIF. Release SDA and SCL BCLIF Interrupt cleared in software RSEN S '0' '0' SSPIF '0' '0' 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 93 774.book Page 94 Tuesday, January 29, 2013 12:02 PM PIC16C77X The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allow to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0'. If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure 8-40). 8.2.18.17 BUS COLLISION DURING A STOP CONDITION Bus collision occurs during a STOP condition if: a) b) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is de-asserted, SCL is sampled low before SDA goes high. FIGURE 8-40: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, Set BCLIF SDA SDA asserted low SCL PEN BCLIF P '0' '0' SSPIF '0' '0' FIGURE 8-41: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high Set BCLIF PEN BCLIF P '0' SSPIF '0' DS30275B-page 94 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 95 Tuesday, January 29, 2013 12:02 PM PIC16C77X 8.3 Connection Considerations for I2C Bus For standard-mode I2C bus devices, the values of resistors Rp Rs in Figure 8-42 depends on the following parameters example, with a supply voltage of VDD = 5V+10% and VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 = 1.7 k VDD as a function of Rp is shown in Figure 8-42. The desired noise margin of 0.1VDD for the low level limits the maximum value of Rs. Series resistors are optional and used to improve ESD susceptibility. • Supply voltage • Bus capacitance • Number of connected devices (input current + leakage current). The bus capacitance is the total capacitance of wire, connections, and pins. This capacitance limits the maximum value of Rp due to the specified rise time (Figure 8-42). The supply voltage limits the minimum value of resistor Rp due to the specified minimum sink current of 3 mA at VOL max = 0.4V for the specified output stages. For The SMP bit is the slew rate control enabled bit. This bit is in the SSPSTAT register, and controls the slew rate of the I/O pins when in I2C mode (master or slave). FIGURE 8-42: SAMPLE DEVICE CONFIGURATION FOR I2C BUS VDD + 10% Rp DEVICE Rp Rs Rs SDA SCL NOTE: I2C devices with input levels related to VDD must have one common supply line to which the pull up resistor is also connected. 1999-2013 Microchip Technology Inc. Advance Information Cb=10 - 400 pF DS30275B-page 95 774.book Page 96 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 96 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 97 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to be set in order to configure pins RC6/TX/CK and RC7/ RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc. FIGURE 9-1: R/W-0 CSRC bit7 bit 7: The USART module also has a multi-processor communication capability using 9-bit address detection. TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 — R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset CSRC: Clock Source Select bit Asynchronous mode Don’t care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6: TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5: TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4: SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3: Unimplemented: Read as '0' bit 2: BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed 0 = Low speed Synchronous mode Unused in this mode bit 1: TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 97 774.book Page 98 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-2: R/W-0 SPEN bit7 RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5: SREN: Single Receive Enable bit Asynchronous mode Don’t care Synchronous mode - master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave Unused in this mode bit 4: CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3: ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1) 1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2: FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1: OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30275B-page 98 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 99 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.1 USART Baud Rate Generator (BRG) EXAMPLE 9-1: The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored. Table 9-1 shows the formula for computation of the baud rate for different USART modes which only apply in master mode (internal clock). CALCULATING BAUD RATE ERROR Desired Baud rate = Fosc / (64 (X + 1)) 9600 = 16000000 /(64 (X + 1)) X 25.042 = 25 = Calculated Baud Rate=16000000 / (64 (25 + 1)) = Error Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated using the formula in Table 9-1. From this, the error in baud rate can be determined. 9615 = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600) / 9600 = 0.16% It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Example 9-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 9.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. TABLE 9-1 BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) X = value in SPBRG (0 to 255) Baud Rate= FOSC/(16(X+1)) NA 0 1 TABLE 9-2 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Address Name 98h TXSTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CSRC TX9 TXEN SYNC — RX9 SREN CREN 18h RCSTA SPEN 99h SPBRG Baud Rate Generator Register ADDEN Bit 2 Bit 1 BRGH TRMT FERR Bit 0 Value on: POR, BOR Value on all other resets TX9D 0000 -010 0000 -010 OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 99 774.book Page 100 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 9-3 BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz KBAUD % ERROR NA NA NA NA 19.53 76.92 96.15 294.1 500 5000 19.53 +1.73 +0.16 +0.16 -1.96 0 - 16 MHz SPBRG value KBAUD (decimal) 255 64 51 16 9 0 255 FOSC = 5.0688 MHz BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW +0.16 +0.16 -0.79 +2.56 0 - 207 51 41 12 7 0 255 NA NA NA 9.766 19.23 75.76 96.15 312.5 500 2500 9.766 % ERROR 7.15909 MHz SPBRG % value KBAUD ERROR (decimal) +1.73 +0.16 -1.36 +0.16 +4.17 0 - 255 129 32 25 7 4 0 255 +0.23 +0.23 +1.32 -1.88 -0.57 - 185 92 22 18 5 0 255 32.768 kHz 1 MHz 3.579545 MHz 4 MHz NA NA NA 9.622 19.24 77.82 94.20 298.3 NA 1789.8 6.991 SPBRG value (decimal) SPBRG SPBRG SPBRG SPBRG SPBRG KBAUD % value KBAUD % KBAUD % % % value value KBAUD value KBAUD value ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) NA NA NA 9.6 19.2 79.2 97.48 316.8 NA 1267 4.950 TABLE 9-4 BAUD RATE (K) NA NA NA NA 19.23 76.92 95.24 307.69 500 4000 15.625 10 MHz SPBRG % value KBAUD ERROR (decimal) 0 0 +3.13 +1.54 +5.60 - 131 65 15 12 3 0 255 NA NA NA 9.615 19.231 76.923 1000 NA NA 100 3.906 +0.16 +0.16 +0.16 +4.17 - 103 51 12 9 0 255 NA NA NA 9.622 19.04 74.57 99.43 298.3 NA 894.9 3.496 +0.23 -0.83 -2.90 +3.57 -0.57 - 92 46 11 8 2 0 255 NA 1.202 2.404 9.615 19.24 83.34 NA NA NA 250 0.9766 +0.16 +0.16 +0.16 +0.16 +8.51 - 207 103 25 12 2 0 255 0.303 1.170 NA NA NA NA NA NA NA 8.192 0.032 7.15909 MHz SPBRG value % (decimal) KBAUD ERROR SPBRG value (decimal) +1.14 -2.48 - 26 6 0 255 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz KBAUD % ERROR NA 1.221 2.404 9.469 19.53 78.13 104.2 312.5 NA 312.5 1.221 +1.73 +0.16 -1.36 +1.73 +1.73 +8.51 +4.17 - 16 MHz SPBRG value (decimal) KBAUD 255 129 32 15 3 2 0 0 255 FOSC = 5.0688 MHz NA 1.202 2.404 9.615 19.23 83.33 NA NA NA 250 0.977 10 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 +0.16 +0.16 +8.51 - 207 103 25 12 2 0 255 NA 1.202 2.404 9.766 19.53 78.13 NA NA NA 156.3 0.6104 % ERROR +0.16 +0.16 +1.73 +1.73 +1.73 - NA 1.203 2.380 9.322 18.64 NA NA NA NA 111.9 0.437 +0.23 -0.83 -2.90 -2.90 - 92 46 11 5 0 255 32.768 kHz 1 MHz 3.579545 MHz 4 MHz 129 64 15 7 1 0 255 BAUD RATE (K) SPBRG SPBRG SPBRG SPBRG SPBRG % value % % % % value value value value KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW 0.31 1.2 2.4 9.9 19.8 79.2 NA NA NA 79.2 0.3094 +3.13 0 0 +3.13 +3.13 +3.13 - DS30275B-page 100 255 65 32 7 3 0 0 255 0.3005 1.202 2.404 NA NA NA NA NA NA 62.500 3.906 -0.17 +1.67 +1.67 - 207 51 25 0 255 0.301 1.190 2.432 9.322 18.64 NA NA NA NA 55.93 0.2185 +0.23 -0.83 +1.32 -2.90 -2.90 - 185 46 22 5 2 0 255 Advance Information 0.300 1.202 2.232 NA NA NA NA NA NA 15.63 0.0610 +0.16 +0.16 -6.99 - 51 12 6 0 255 0.256 NA NA NA NA NA NA NA NA 0.512 0.0020 -14.67 - 1 0 255 1999-2013 Microchip Technology Inc. 774.book Page 101 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 9-5 BAUD RATE (K) 9.6 19.2 38.4 57.6 115.2 250 625 1250 BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz KBAUD % ERROR 9.615 19.230 37.878 56.818 113.636 250 625 1250 +0.16 +0.16 -1.36 -1.36 -1.36 0 0 0 16 MHz SPBRG value (decimal) KBAUD 129 64 32 21 10 4 1 0 9.615 19.230 38.461 58.823 111.111 250 NA NA 10 MHz SPBRG % value ERROR (decimal) KBAUD +0.16 +0.16 +0.16 +2.12 -3.55 0 - 103 51 25 16 8 3 - 9.615 18.939 39.062 56.818 125 NA 625 NA 7.16 MHz SPBRG value % (decimal) KBAUD ERROR % ERROR +0.16 -1.36 +1.7 -1.36 +8.51 0 - 64 32 15 10 4 0 - 9.520 19.454 37.286 55.930 111.860 NA NA NA -0.83 +1.32 -2.90 -2.90 -2.90 - SPBRG value (decimal) 46 22 11 7 3 - FOSC = 5.068 MHz KBAUD 32.768 kHz 1 MHz 3.579 MHz 4 MHz SPBRG SPBRG SPBRG SPBRG SPBRG % % % % % value value value value value ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 9.6 19.2 9.6 18.645 0 -2.94 32 16 NA 1.202 38.4 57.6 115.2 250 625 1250 39.6 52.8 105.6 NA NA NA +3.12 -8.33 -8.33 - 7 5 2 - 2.403 9.615 19.231 NA NA NA 1999-2013 Microchip Technology Inc. +0.17 +0.13 +0.16 +0.16 - 207 9.727 18.643 +1.32 -2.90 22 11 8.928 20.833 -6.99 +8.51 6 2 NA NA - - 103 25 12 - 37.286 -2.90 55.930 -2.90 111.860 -2.90 223.721 -10.51 NA NA - 5 3 1 0 - 31.25 62.5 NA NA NA NA -18.61 +8.51 - 1 0 - NA NA NA NA NA NA - - Advance Information DS30275B-page 101 774.book Page 102 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.2 USART Asynchronous Mode (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. In this mode, the USART uses standard nonreturn-tozero (NRZ) format (one start bit, eight or nine data bits and one stop bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART’s transmitter and receiver are functionally independent but use the same data format and baud rate. The baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Note 1: The TSR register is not mapped in data memory so it is not available to the user. Note 2: Flag bit TXIF is set when enable bit TXEN is set. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: Steps to follow when setting up an Asynchronous Transmission: • • • • 1. Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver 9.2.1 2. 3. USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 9-3. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register FIGURE 9-3: 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 9.1) Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb LSb (8) Pin Buffer and Control 0 TSR register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG Baud Rate Generator TX9 TX9D DS30275B-page 102 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 103 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-4: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Stop Bit WORD 1 Transmit Shift Reg TRMT bit (Transmit shift reg. empty flag) FIGURE 9-5: Bit 7/8 WORD 1 TXIF bit (Transmit buffer reg. empty flag) ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit TXIF bit (interrupt reg. flag) TRMT bit (Transmit shift reg. empty flag) Word 2 Bit 0 Bit 1 WORD 1 Bit 7/8 Stop Bit Start Bit Bit 0 WORD 2 WORD 1 Transmit Shift Reg. WORD 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 9-6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Address Name Bit 7 Bit 6 0Ch PIR1 PSPIF(1) ADIF RCIF 18h RCSTA SPEN RX9 SREN 19h TXREG 8Ch PIE1 98h TXSTA 99h SPBRG Bit 5 Bit 4 Value on: POR, BOR Value on all other Resets Bit 3 Bit 2 Bit 1 Bit 0 TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 USART Transmit Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 103 774.book Page 104 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 9-6. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. The USART module has a special provision for multiprocessor communication. When the RX9 bit is set in the RCSTA register, 9-bits are received and the ninth bit is placed in the RX9D status bit of the RSTA register. The port can be programmed such that when the stop bit is received, the serial port interrupt will only be activated if the RX9D bit = 1. This feature is enabled by setting the ADDEN bit RCSTA<3> in the RCSTA register. This feature can be used in a multi-processor system as follows: A master processor intends to transmit a block of data to one of many slaves. It must first send out an address byte that identifies the target slave. An address byte is identified by the RX9D bit being a ‘1’ (instead of a ‘0’ for a data byte). If the ADDEN bit is set in the slave’s RCSTA register, all data bytes will be ignored. However, if the ninth received bit is equal to a ‘1’, indicating that the received byte is an address, the slave will be interrupted and the contents of the RSR register will be transferred into the receive buffer. This allows the slave to be interrupted only by addresses, so that the slave can examine the received byte to see if it is addressed. The addressed slave will then clear its ADDEN bit and prepare to receive data bytes from the master. 9.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT Steps to follow when setting up an Asynchronous Reception with Address Detect Enabled: • Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • If interrupts are desired, then set enable bit RCIE. • Set bit RX9 to enable 9-bit reception. • Set ADDEN to enable address detect. • Enable the reception by setting enable bit CREN. • Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable bit RCIE was set. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. • Read the 8-bit received data by reading the RCREG register, to determine if the device is being addressed. • If any error occurred, clear the error by clearing enable bit CREN. • If the device has been addressed, clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer, and interrupt the CPU. When ADDEN is set, all data bytes are ignored. Following the STOP bit, the data will not be loaded into the receive buffer, and no interrupt will occur. If another byte is shifted into the RSR register, the previous data byte will be lost. The ADDEN bit will only take effect when the receiver is configured in 9-bit mode. The receiver block diagram is shown in Figure 9-6. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). DS30275B-page 104 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 105 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK FERR OERR CREN SPBRG 64 or 16 Baud Rate Generator RSR register MSb Stop (8) 7 1 LSb 0 Start RC7/RX/DT Pin Buffer and Control Data Recovery RX9 8 SPEN RX9 Enable Load of ADDEN Receive Buffer RX9 ADDEN RSR<8> 8 RX9D RCREG register FIFO 8 RCIF Interrupt Data Bus RCIE FIGURE 9-7: RC7/RX/DT (pin) ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT Start bit bit0 bit1 bit8 Stop bit Start bit bit0 bit8 Stop bit Load RSR Bit8 = 0, Data Byte Bit8 = 1, Address Byte WORD 1 RCREG Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 105 774.book Page 106 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST Start bit RC7/RX/DT (pin) bit0 bit1 bit8 Stop bit Start bit bit0 bit8 Stop bit Load RSR Bit8 = 1, Address Byte Bit8 = 0, Data Byte WORD 1 RCREG Read RCIF Note: This timing diagram shows an address byte followed by a data byte. The data byte is not read into the RCREG (receive buffer) because ADEN was not updated and still = 0. TABLE 9-7 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Address Name Bit 7 Bit 6 0Ch PIR1 PSPIF(1) ADIF RCIF 18h RCSTA SPEN RX9 SREN 1Ah RCREG 8Ch PIE1 98h TXSTA 99h SPBRG Bit 5 Bit 4 Value on: POR, BOR Value on all other Resets Bit 3 Bit 2 Bit 1 Bit 0 TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x USART Receive Register 0000 0000 0000 0000 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. DS30275B-page 106 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 107 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner i.e. transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>). 9.3.1 USART SYNCHRONOUS MASTER TRANSMISSION Address Name 0Ch PIR1 18h RCSTA 2. 3. 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate (Section 9.1). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 PSPIF(1) ADIF SPEN RX9 Bit 3 Bit 2 Bit 1 Bit 0 RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 FERR OERR RX9D 0000 000x 0000 000x SREN CREN ADDEN TXREG USART Transmit Register PIE1 98h TXSTA CSRC TX9 Value on all other Resets Bit 4 8Ch PSPIE(1) ADIE Value on: POR, BOR Bit 5 19h 99h Steps to follow when setting up a Synchronous Master Transmission: 1. The USART transmitter block diagram is shown in Figure 9-3. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and interrupt bit, TXIF (PIR1<4>) is set. The interrupt can be TABLE 9-8 enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. RCIE TXIE SSPIE TXEN SYNC — CCP1IE TMR2IE TMR1IE BRGH TRMT SPBRG Baud Rate Generator Register TX9D 0000 0000 0000 0000 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 107 774.book Page 108 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 9-9: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4Q1 Q2 Q3Q4 RC7/RX/DT pin Bit 0 Bit 1 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Bit 2 Bit 7 Bit 0 Bit 1 Bit 7 WORD 2 WORD 1 RC6/TX/CK pin Write to TXREG reg Write word1 Write word2 TXIF bit (Interrupt flag) TRMT TRMT bit TXEN bit '1' '1' Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words. FIGURE 9-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS30275B-page 108 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 109 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.3.2 3. 4. Ensure bits CREN and SREN are clear. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set then CREN takes precedence. Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate. (Section 9.1) Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. 2. TABLE 9-9 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Address Name Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x Bit 7 Bit 6 PSPIF(1) SPEN 0Ch PIR1 18h RCSTA 1Ah RCREG USART Receive Register 8Ch PIE1 98h TXSTA 99h PSPIE(1) ADIE CSRC SPBRG TX9 RCIE TXIE SSPIE TXEN SYNC — CCP1IE TMR2IE TMR1IE BRGH TRMT TX9D Baud Rate Generator Register 0000 0000 0000 0000 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 109 774.book Page 110 Tuesday, January 29, 2013 12:02 PM PIC16C77X 9.4 USART Synchronous Slave Mode Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 9.4.2 USART SYNCHRONOUS SLAVE RECEPTION The operation of the synchronous master and slave modes is identical except in the case of the SLEEP mode. Also, bit SREN is a don't care in slave mode. The operation of the synchronous master and slave modes are identical except in the case of the SLEEP mode. If receive is enabled, by setting bit CREN, prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h). If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: Steps to follow when setting up a Synchronous Slave Reception: a) 1. 9.4.1 b) c) d) e) USART SYNCHRONOUS SLAVE TRANSMIT The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). Steps to follow when setting up a Synchronous Slave Transmission: 1. 2. 3. 4. 5. 6. 7. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. DS30275B-page 110 2. 3. 4. 5. 6. 7. 8. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 111 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 9-10 Address Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 Bit 7 Bit 6 PSPIF(1) SPEN 0Ch PIR1 18h RCSTA 19h TXREG USART Transmit Register 8Ch PIE1 98h 99h TXSTA PSPIE(1) ADIE CSRC TX9 RCIE TXEN TXIE SYNC SSPIE — CCP1IE TMR2IE BRGH TRMT SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. TABLE 9-11 Address Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PSPIF(1) SPEN ADIF RCIF TXIF SSPIF RX9 SREN CREN ADDEN 0Ch PIR1 18h RCSTA 1Ah RCREG USART Receive Register 8Ch PIE1 98h TXSTA 99h SPBRG PSPIE(1) ADIE CSRC TX9 RCIE TXEN TXIE SYNC SSPIE — Bit 2 Bit 1 CCP1IF TMR2IF FERR OERR Bit 0 Value on: POR, BOR Value on all other Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE BRGH TRMT Baud Rate Generator Register TX9D 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 111 774.book Page 112 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 112 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 113 Tuesday, January 29, 2013 12:02 PM PIC16C77X 10.0 VOLTAGE REFERENCE MODULE AND LOW-VOLTAGE DETECT The source for the reference voltages comes from the bandgap reference circuit. The bandgap circuit is energized anytime the reference voltage is required by the other sub-modules, and is powered down when not in use. The control registers for this module are LVDCON and REFCON, as shown in Figure 10-1 and Figure 10-2. The Voltage Reference module provides reference voltages for the Brown-out Reset circuitry, the Low-voltage Detect circuitry and the A/D converter. FIGURE 10-1: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — BGST LVDEN LV3 LV2 LV1 LV0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5: BGST: Bandgap Stable Status Flag bit 1 = Indicates that the bandgap voltage is stable, and LVD interrupt is reliable 0 = Indicates that the bandgap voltage is not stable, and LVD interrupt should not be enabled bit 4: LVDEN: Low-voltage Detect Power Enable bit 1 = Enables LVD, powers up bandgap circuit and reference generator 0 = Disables LVD, powers down bandgap circuit if unused by BOR or VRH/VRL bit 3-0: LV3:LV0: Low Voltage Detection Limit bits (1) 1111 = External analog input is used 1110 = 4.5V 1101 = 4.2V 1100 = 4.0V 1011 = 3.8V 1010 = 3.6V 1001 = 3.5V 1000 = 3.3V 0111 = 3.0V 0110 = 2.8V 0101 = 2.7V 0100 = 2.5V Note 1: These are the minimum trip points for the LVD, see Table 15-3 for the trip point tolerances. Selection of an unused setting may result in an inadvertant interrupt. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 113 774.book Page 114 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 10-2: REFCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 VRHEN VRLEN VRHOEN VRLOEN — — — — bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: VRHEN: Voltage Reference High Enable bit (VRH = 4.096V) 1 = Enabled, powers up reference generator 0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL bit 6: VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V) 1 = Enabled, powers up reference generator 0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRH bit 5: VRHOEN: High Voltage Reference Output Enable bit 1 = Enabled, VRH analog reference is presented on RA3 if enabled (VRHEN = 1) 0 = Disabled, analog reference is used internally only bit 4: VRLOEN: Low Voltage Reference Output Enable bit 1 = Enabled, VRL analog reference is presented on RA2 if enabled (VRLEN = 1) 0 = Disabled, analog reference is used internally only bit 3-0: Unimplemented: Read as '0’ 10.1 Bandgap Voltage Reference Each voltage reference can source/sink up to 5 mA of current. The bandgap module generates a stable voltage reference of 1.22V over a range of temperatures and device supply voltages. This module is enabled anytime any of the following are enabled: • Brown-out Reset • Low-voltage Detect • Either of the internal analog references (VRH, VRL) Each reference, if enabled, can be presented on an external pin by setting the VRHOEN (high reference output enable) or VRLOEN (low reference output enable) control bit. If the reference is not enabled, the VRHOEN and VRLOEN bits will have no effect on the corresponding pin. The device specific pin can then be used as general purpose I/O. Note: Whenever the above are all disabled, the bandgap module is disabled and draws no current. 10.2 Internal VREF for A/D Converter The bandgap output voltage is used to generate two stable references for the A/D converter module. These references are enabled in software to provide the user with the means to turn them on and off in order to minimize current consumption. Each reference can be individually enabled. If VRH or VRL is enabled and the other reference (VRL or VRH), the BOR, and the LVD modules are not enabled, the bandgap will require a start-up time of no more than 50 s before the bandgap reference is stable. Before using the internal VRH or VRL reference, ensure that the bandgap reference voltage is stable by monitoring the BGST bit in the LVDCON register. The voltage references will not be reliable until the bandgap is stable as shown by BGST being set. The 4.096V reference (VRH) is enabled with control bit VRHEN (REFCON<7>). When this bit is set, the gain amplifier is enabled. After a specified start-up time a stable reference of 4.096V is generated and can be used by the A/D converter as the VRH input. The 2.048V reference (VRL) is enabled by setting control bit VRLEN (REFCON<6>). When this bit is set, the gain amplifier is enabled. After a specified start up time a stable reference of 2.048V is generated and can be used by the A/D converter as the VRL input. DS30275B-page 114 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 115 Tuesday, January 29, 2013 12:02 PM PIC16C77X 10.3 Low-voltage Detect (LVD) This module is used to generate an interrupt when the supply voltage falls below a specified “trip” voltage. This module operates completely under software control. This allows a user to power the module on and off to periodically monitor the supply voltage, and thus minimize total current consumption. FIGURE 10-3: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT VDD LVDCON VDD LVDEN VRxEN 16 to 1 MUX RB3/AN9/LVDIN REFCON LVD A/D Ref = 4.096V BODEN BGAP A/D Ref = 2.048V EN The LVD module is enabled by setting the LVDEN bit in the LVDCON register. The “trip point” voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to or less than the trip point, the module will generate an interrupt signal setting interrupt flag bit LVDIF. If interrupt enable bit LVDIE was set, then an interrupt is generated. The LVD interrupt can wake the device from sleep. The "trip point" voltage is software programmable to any one of 16 values, five of which are reserved (See Figure 10-1). The trip point is selected by programming the LV3:LV0 bits (LVDCON<3:0>). Note: The LVDIF bit can not be cleared until the supply voltage rises above the LVD trip point. If interrupts are enabled, clear the LVDIE bit once the first LVD interrupt occurs to prevent reentering the interrupt service routine immediately after exiting the ISR. If the bandgap reference voltage is previously unused by either the brown-out circuitry or the voltage reference circuitry, then the bandgap circuit requires a time to start-up and become stable before a low voltage condition can be reliably detected. The low-voltage interrupt flag is prevented from being set until the bandgap has reached a stable reference voltage. When the bandgap is stable the BGST (LVDCON<5>) bit is set indicating that the low-voltage interrupt flag bit is released to be set if VDD is equal to or less than the LVD trip point. 10.3.1 EXTERNAL ANALOG VOLTAGE INPUT The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when LV3:LV0 = 1111. When these bits are set the comparator input is multiplexed from an external input pin (RB3/AN9/LVDIN. Once the LV bits have been programmed for the specified trip voltage, the low-voltage detect circuitry is then enabled by setting the LVDEN (LVDCON<4>) bit. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 115 774.book Page 116 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 116 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 117 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: • • • • The analog-to-digital (A/D) converter module has six inputs for the PIC16C773 and ten for the PIC16C774. The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 12-bit digital number. The A/D module has up to 10 analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltages are software selectable to either the device’s analog positive and negative supply voltages (AVDD/AVSS), the voltage level on the VREF+ and VREF- pins, or internal voltage references if available (VRH, VRL). The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. A/D Result Register Low ADRESL A/D Result Register High ADRESH A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A device reset forces all registers to their reset state. This forces the A/D module to be turned off and any conversion is aborted. 11.1 Control Registers The ADCON0 register, shown in Figure 11-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 11-2, configures the functions of the port pins, the voltage reference configuration and the result format. The port pins can be configured as analog inputs or as digital I/O. The combination of the ADRESH and ADRESL registers contain the result of the A/D conversion. The register pair is referred to as the ADRES register. When the A/D conversion is complete, the result is loaded into ADRES, the GO/DONE bit (ADCON0<2>) is cleared, and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 11-3. FIGURE 11-1: ADCON0 REGISTER (ADDRESS 1Fh). R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 bit7 bit 7:6 R/W-0 ADON bit 0 R= W= -n= Readable bit Writable bit Value at POR reset ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = Fosc/2 01 = Fosc/8 10 = Fosc/32 11 = FRC (clock derived from an RC oscillator = 1 MHz max) bit 5:3,1 CHS3:CHS0: Analog Channel Select bits 0000 = channel 00 (AN0) 0001 = channel 01 (AN1) 0010 = channel 02 (AN2) 0011 = channel 03 (AN3) 0100 = channel 04 (AN4) (Reserved on 28-pin devices, do not use) 0101 = channel 05 (AN5) (Reserved on 28-pin devices, do not use) 0110 = channel 06 (AN6) (Reserved on 28-pin devices, do not use) 0111 = channel 07 (AN7) (Reserved on 28-pin devices, do not use) 1000 = channel 08 (AN8) 1001 = channel 09 (AN9) 1010, 1011, 1100, 1101, 1110,1111 are reserved, do not select. bit 2: GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter is shutoff and consumes no operating current 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 117 774.book Page 118 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 11-2: ADCON1 REGISTER (ADDRESS 9Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit7 bit 0 bit 7: ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6:4 VCFG2:VCFG0: Voltage reference configuration bits A/D VREFH bit 3:0 R= W= U= -n= Readable bit Writable bit Unimplemented bit, read as ‘0’ Value at POR reset A/D VREFL 000 AVDD AVSS 001 External VREF+ External VREF- 010 Internal VRH Internal VRL 011 External VREF+ AVSS 100 Internal VRH AVSS 101 AVDD External VREF- 110 AVDD Internal VRL 111 Internal VRL AVSS PCFG3:PCFG0: A/D Port Configuration bits(1) AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0000 A A A A A A A A A A 0001 A A A A A A A A A A 0010 A A A A A A A A A A 0011 A A A A A A A A A A 0100 A A A A A A A A A A 0101 A A A A A A A A A A 0110 D A A A A A A A A A 0111 D D A A A A A A A A 1000 D D D A A A A A A A 1001 D D D D A A A A A A 1010 D D D D D A A A A A 1011 D D D D D D A A A A 1100 D D D D D D D A A A 1101 D D D D D D D D A A 1110 D D D D D D D D D A 1111 D D D D D D D D D D A = Analog input D= Digital I/O Note 1: Selection of an unimplemented channel produces a result of 0xFFFFFF. DS30275B-page 118 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 119 Tuesday, January 29, 2013 12:02 PM PIC16C77X The value that is in the ADRESH and ADRESL registers are not modified for a Power-on Reset. The ADRESH and ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 11.6. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 11.2 Configuring the A/D Module 11.3 Configuring Analog Port Pins The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the PORTA or PORTE register, all pins configured as analog input channels will read as cleared (a low level). When reading the PORTB register, all pins configured as analog input channels will read as set (a high level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the ANx pins), may cause the input buffer to consume current that is out of the devices specification. 11.3.1 CONFIGURING THE REFERENCE VOLTAGES After the A/D module has been configured as desired. and the analog input channels have their corresponding TRIS bits selected for port inputs, the selected channel must be acquired before conversion is started. The A/D conversion cycle can be initiated by setting the GO/DONE bit. The A/D conversion begins, and lasts for 13TAD. The following steps should be followed for performing an A/D conversion: 1. 2. 3. 4. 5. Configure the A/D module • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure A/D interrupt (if required) • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit Wait the required acquisition time (3TAD) Start conversion • Set GO/DONE bit (ADCON0) Wait 13TAD until A/D conversion is complete, by either: • Polling for the GO/DONE bit to be cleared OR 6. 7. • Waiting for the A/D interrupt Read A/D Result registers (ADRESH and ADRESL), clear ADIF if required. For next conversion, go to step 1, step 2 or step 3 as required. Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRESH and ADRESL registers WILL be updated with the partially completed A/D conversion value. That is, the ADRESH and ADRESL registers WILL contain the value of the current incomplete conversion. Note: The VCFG bits in the ADCON1 register configure the A/D module reference inputs. The reference high input can come from an internal reference (VRH) or (VRL), an external reference (VREF+), or AVDD. The low reference input can come from an internal reference (VRL), an external reference (VREF-), or AVSS. If an external reference is chosen for the reference high or reference low inputs, the port pin that multiplexes the incoming external references is configured as an analog input, regardless of the values contained in the A/D port configuration bits (PCFG3:PCFG0). 1999-2013 Microchip Technology Inc. Advance Information Do not set the ADON bit and the GO/DONE bit in the same instruction. Doing so will cause the GO/DONE bit to be automatically cleared. DS30275B-page 119 774.book Page 120 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 11-3: A/D BLOCK DIAGRAM CHS3:CHS0 RB3/AN9 RB2/AN8 RE2/AN7(1) RE1/AN6(1) VAIN RE0/AN5(1) (Input voltage) RA5/AN4(1) RA3/AN3/VREF+/VRH RA2/AN2/VREF-/VRL RA1/AN1 AVDD VREFH RA0/AN0 VRH VRL (Reference voltage) VCFG2:VCFG0 A/D Converter VREFL VRL (Reference voltage) AVSS VCFG2:VCFG0 Note 1: Not available on 28-pin devices. DS30275B-page 120 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 121 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.4 Selecting the A/D Conversion Clock The A/D conversion cycle requires 13TAD: 1 TAD for settling time, and 12 TAD for conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: • • • • 2 TOSC 8 TOSC 32 TOSC Internal RC oscillator TABLE 11-1 2 TOSC 8 TOSC 32 TOSC RC For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 11-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. The ADIF bit is set on the rising edge of the 14th TAD. The GO/DONE bit is cleared on the falling edge of the 14th TAD. TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Operation Note that these options are the same as those of the 8-bit A/D. Device Frequency ADCS<1:0> 20 MHz 5 MHz 4 MHz 1.25 MHz 00 01 10 11 100 ns(2) 800 ns(2) 1.6 s 2 - 6 s(1,4) 400 ns(2) 1.6 s 6.4 s 2 - 6 s(1,4) 500 ns(2) 2.0 s 8.0 s(3) 2 - 6 s(1,4) 1.6 s 6.4 s 24 s(3) 2 - 6 s(1,4) Note 1: The RC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only recommended if the conversion will be performed during sleep. 11.5 A/D Conversions Figure 11-5 shows an example that performs an A/D conversion. The port pins are configured as analog inputs. The analog reference VREF+ is the device AVDD and the analog reference VREF- is the device AVSS. The A/D interrupt is enabled, and the A/D conversion clock is TRC. The conversion is performed on the AN0 channel. FIGURE 11-4: PERFORMING AN A/D CONVERSION BCF BSF CLRF BSF BCF MOVLW PIR1, ADIF STATUS, RP0 ADCON1 PIE1, ADIE STATUS, RP0 0xC1 MOVWF BSF BSF ADCON0 INTCON, PEIE INTCON, GIE ;Clear A/D Int Flag ;Select Page 1 ;Configure A/D Inputs ;Enable A/D interrupt ;Select Page 0 ;RC clock, A/D is on, ;Ch 0 is selected ; ;Enable Peripheral ;Enable All Interrupts ; ; Ensure that the required sampling time for the ; selected input channel has lapsed. Then the ; conversion may be started. BSF ADCON0, GO ;Start A/D Conversion : ;The ADIF bit will be ;set and the GO/DONE bit : ;cleared upon completion;of the A/D conversion. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 121 774.book Page 122 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 11-5: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Sample Selected Channel Yes GO = 0? No A/D Clock = RC? Yes Start of A/D Conversion Delayed 1 Instruction Cycle Finish Conversion GO = 0 ADIF = 1 No No SLEEP Yes Instruction? SLEEP Yes Instruction? Abort Conversion GO = 0 ADIF = 0 Wake-up Yes From Sleep? Finish Conversion GO = 0 ADIF = 1 No No Finish Conversion GO = 0 ADIF = 1 Wait 2 TAD SLEEP Power down A/D Wait 2 TAD Stay in Sleep Powerdown A/D Wait 2 TAD DS30275B-page 122 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 123 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.6 A/D Sample Requirements 11.6.1 RECOMMENDED SOURCE IMPEDANCE The maximum recommended impedance for analog sources is 2.5 k. This value is calculated based on the maximum leakage current of the input pin. The leakage current is 100 nA max., and the analog input voltage cannot be vary by more than 1/4 LSb or 250 mV due to leakage. This places a requirement on the input impedance of 250 V/100 nA = 2.5 k. 11.6.2 SAMPLING TIME CALCULATION For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-8. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 11-8. The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed) this sampling must be done before the conversion can be started. To calculate the minimum sampling time, Equation 11-6 may be used. This equation assumes that 1/4 LSb error is used (16384 steps for the A/D). The 1/4 LSb error is the maximum error allowed for the A/D to meet its specified resolution. The CHOLD is assumed to be 25 pF for the 12-bit A/D. FIGURE 11-6: A/D SAMPLING TIME EQUATION VHOLD =(VREF - VREF/16384) = (VREF) • (1 -e (-TC/C (RIC +RSS + RS)) VREF(1 - 1/16384) = VREF • (1 -e (-TC/C (RIC +RSS + RS)) TC = -CHOLD (1k + RSS + RS) In (1/16384) Figure 11-7 shows the calculation of the minimum time required to charge CHOLD. This calculation is based on the following system assumptions: CHOLD = 25 pF RS = 2.5 k 1/4 LSb error VDD = 5V RSS = 10 k(worst case) Temp (system Max.) = 50C Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 2.5 k. This is required to meet the pin leakage specification. 4: After a conversion has completed, 2 TAD time must be waited before sampling can begin again. During this time the holding capacitor is not connected to the selected A/D input channel. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 123 774.book Page 124 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 11-7: CALCULATING THE MINIMUM REQUIRED SAMPLE TIME TACQ = TACQ = TC = TC = TC = TC = TC = TC = Amplifier Settling Time + Holding Capacitor Charging Time +Temperature Coefficient † 5 s + TC + [(Temp - 25C)(0.05s/C)] † + Holding Capacitor Charging Time (CHOLD) (RIC + RSS + RS) In (1/16384) -25 pF (1 k +10 k + 2.5 k) In (1/16384) -25 pF (13.5 k) In (1/16384) -0.338 (-9.704)s 3.3s TACQ = 5s + 3.3 s + [(50C - 25C)(0.05s / C)] TACQ = TACQ = 8.3 s + 1.25s 9.55 s † The temperature coefficient is only required for temperatures > 25C. FIGURE 11-8: ANALOG INPUT MODEL VDD Rs Port Pin CPIN 5 pF VA Sampling Switch VT = 0.6V VT = 0.6V RIC 1k SS RSS ILEAKAGE 100 nA CHOLD = 25 pF VSS Legend CPIN = input capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions RIC SS CHOLD DS30275B-page 124 = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) 6V 5V VDD 4V 3V 2V Advance Information 5 6 7 8 9 10 11 Sampling Switch ( k ) 1999-2013 Microchip Technology Inc. 774.book Page 125 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.7 Use of the CCP Trigger 11.9 An A/D conversion can be started by the “special event trigger” of the CCP module. This requires that the CCPnM<3:0> bits be programmed as 1011b and that the A/D module is enabled (ADON is set). When the trigger occurs, the GO/DONE bit will be set on Q2 to start the A/D conversion and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D conversion cycle, with minimal software overhead (moving the ADRESH and ADRESL to the desired location). The appropriate analog input channel must be selected before the “special event trigger” sets the GO/DONE bit (starts a conversion cycle). If the A/D module is not enabled (ADON is cleared), then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter. 11.8 Effects of a RESET A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRESH and ADRESL registers are not modified. The ADRESH and ADRESL registers will contain unknown data after a Power-on Reset. Faster Conversion - Lower Resolution Trade-off Not all applications require a result with 12-bits of resolution, but may instead require a faster conversion time. The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same. To speed up the conversion, the A/D module may be halted by clearing the GO/DONE bit after the desired number of bits in the result have been converted. Once the GO/DONE bit has been cleared, all of the remaining A/D result bits are ‘0’. The equation to determine the time before the GO/DONE bit can be switched is as follows: Conversion time = N•TAD + 1TAD Where: N = number of bits of resolution required, and 1TAD is the amplifier settling time. Since TAD is based from the device oscillator, the user must use some method (a timer, software loop, etc.) to determine when the A/D GO/DONE bit may be cleared. Table 11-2 shows a comparison of time required for a conversion with 4-bits of resolution, versus the normal 12-bit resolution conversion. The example is for devices operating at 20 MHz. The A/D clock is programmed for 32 TOSC. TABLE 11-2 4-BIT vs. 12-BIT CONVERSION TIMES Freq. (MHz) Tosc TAD = 32 Tosc 1TAD+N•TAD 1999-2013 Microchip Technology Inc. Advance Information 20 20 20 Resolution 4-bit 50 ns 1.6 s 8 s 12-bit 50 ns 1.6 s 20.8 s DS30275B-page 125 774.book Page 126 Tuesday, January 29, 2013 12:02 PM PIC16C77X 11.10 A/D Operation During Sleep Turning off the A/D places the A/D module in its lowest current consumption state. The A/D module can operate during SLEEP mode. This requires that the A/D clock source be configured for RC (ADCS1:ADCS0 = 11b). With the RC clock source selected, when the GO/DONE bit is set the A/D module waits one instruction cycle before starting the conversion cycle. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise during the sample and conversion. When the conversion cycle is completed the GO/DONE bit is cleared, and the result loaded into the ADRESH and ADRESL registers. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction causes the present conversion to be aborted and the A/D module is turned off, though the ADON bit will remain set. TABLE 11-3 Address Note: 11.11 For the A/D module to operate in SLEEP, the A/D clock source must be configured to RC (ADCS1:ADCS0 = 11b). Connection Considerations Since the analog inputs employ ESD protection, they have diodes to VDD and VSS. This requires that the analog input must be between VDD and VSS. If the input voltage exceeds this range by greater than 0.3V (either direction), one of the diodes becomes forward biased and it may damage the device if the input current specification is exceeded. An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 2.5 k recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. SUMMARY OF A/D REGISTERS Name 0Bh,8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Ch PIR1 PSPIF 8Ch PIE1 PSPIE(1) 1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu 9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu 9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ---- 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000 9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 05h PORTA — — PORTA5(2) --0x 0000 --0u 0000 06h PORTB xxxx 11xx uuuu 11uu 09h(2) PORTE — — ---- -000 ---- -000 85h TRISA — — --11 1111 --11 1111 86h TRISB 1111 1111 1111 1111 89h(2) TRISE 0000 -111 0000 -111 PORTA Data Latch when written: PORTA<4:0> pins when read PORTB Data Latch when written: PORTB pins when read — bit5(2) — — RE2 RE1 PORTA Data Direction Register PORTB Data Direction Register IBF OBF IBOV PSPMODE — PORTE Data Direction Bits RE0 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 2: These bits/registers are not implemented on the 28-pin devices, read as '0'. DS30275B-page 126 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 127 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.0 SPECIAL FEATURES OF THE CPU These PICmicro devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: • Oscillator Selection • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Low-voltage detection • SLEEP • Code protection • ID locations • In-circuit serial programming Some of the core features provided may not be necessary to each application that a device may be used for. The configuration word bits allow these features to be configured/enabled/disabled as necessary. These features include code protection, brown-out reset and its trippoint, the power-up timer, the watchdog timer and the devices oscillator mode. As can be seen in Figure 12-1, some additional configuration word bits have been provided for brown-out reset trippoint selection. These devices have a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up type resets only (POR, BOR), designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. Additional information on special features is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). 12.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 127 774.book Page 128 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 12-1: CONFIGURATION WORD CP1 CP0 BORV1 BORV0 CP1 bit13 12 11 10 9 CP0 - BODEN CP1 8 7 6 5 CP0 PWRTE 4 3 WDTE FOSC1 2 1 FOSC0 Register: Address CONFIG 2007h bit0 (2) bit 13-12: CP1:CP0: Code Protection bits bit 9-8: 11 = Program memory code protection off bit 5-4: 10 = 0800h-0FFFh code protected 01 = 0400h-0FFFh code protected 00 = 0000h-0FFFh code protected bit 11-10: BORV1:BORV0: Brown-out Reset Voltage bits(3) 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 7: Unimplemented, Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 3: These are the minimum trip points for the BOR, see Table 15-4 for the trip point tolerances. Selection of an unused setting may result in an inadvertant interrupt. 12.2 Oscillator Configurations 12.2.1 OSCILLATOR TYPES 12.2.2 The PIC16C77X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor DS30275B-page 128 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 12-2). The PIC16C77X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. A difference from the other mid-range devices may be noted in that the device can be driven from an external clock only when configured in HS mode (Figure 12-3). Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 129 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 12-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) C1(1) OSC1 XTAL C2 Note1: 2: 3: To internal logic RF(3) RS(2) PIC16C77X See Table 12-1 and Table 12-2 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen. PIC16C77X Open TABLE 12-1 OSC2 CERAMIC RESONATORS Ranges Tested: Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz HS HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Cap. Range C1 Cap. Range C2 33 pF 32 kHz 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes at bottom of page. Crystals Used 32 kHz Epson C-001R32.768K-A ± 20 PPM 200 kHz STD XTL 200.000KHz ± 20 PPM 1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM 20 MHz EPSON CA-301 20.000M-C ± 30 PPM OSC1 Clock from ext. system Mode XT SLEEP FIGURE 12-3: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) XT Osc Type LP OSC2 (1) TABLE 12-2 OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 12-1). 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. These values are for design guidance only. See notes at bottom of page. Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5% All resonators used did not have built-in capacitors. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 129 774.book Page 130 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.2.3 RC OSCILLATOR For timing insensitive applications the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. These factors and the variation due to tolerances of external R and C components used need to be taken into account for each application. Figure 12-4 shows how the R/C combination is connected to the PIC16C77X. FIGURE 12-4: RC OSCILLATOR MODE VDD Rext OSC1 Cext Internal clock PIC16C77X VSS Fosc/4 DS30275B-page 130 OSC2/CLKOUT Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 131 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.3 Reset The PIC16C77X devices have several different resets. These resets are grouped into two classifications; power-up and non-power-up. The power-up type resets are the power-on and brown-out resets which assume the device VDD was below its normal operating range for the device’s configuration. The non-power up type resets assume normal operating limits were maintained before/during and after the reset. • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) Some registers are not affected in any reset condition. Their status is unknown on a power-up reset and unchanged in any other reset. Most other registers are placed into an initialized state upon reset, however they are not affected by a WDT reset during sleep because this is considered a WDT Wakeup, which is viewed as the resumption of normal operation. Several status bits have been provided to indicate which reset occurred (see Table 12-4). See Table 12-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 12-5. These devices have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. FIGURE 12-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset S BODEN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 131 774.book Page 132 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.4 Power-On Reset (POR) 12.5 A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. For a slow rise time, see Figure 12-6. Two delay timers have been provided which hold the device in reset after a POR (dependant upon device configuration) so that all operational parameters have been met prior to releasing to device to resume/begin normal operation. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the startup conditions, or if necessary an external POR circuit may be implemented to delay end of reset for as long as needed. FIGURE 12-6: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) R R1 MCLR C PIC16C77X Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device’s electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). DS30275B-page 132 The Power-up Timer provides a fixed 72 ms nominal time-out on power-up type resets only. For a POR, the PWRT is invoked when the POR pulse is generated. For a BOR, the PWRT is invoked when the device exits the reset condition (VDD rises above BOR trippoint). The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT’s time delay is designed to allow VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT for the POR only. For a BOR the PWRT is always available regardless of the configuration bit setting. The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 12.6 Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on a power-up type reset or a wake-up from SLEEP. 12.7 Brown-Out Reset (BOR) The Brown-out Reset module is used to generate a reset when the supply voltage falls below a specified trip voltage. The trip voltage is configurable to any one of four voltages provided by the BORV1:BORV0 configuration word bits. VDD D Power-up Timer (PWRT) Configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below the specified trippoint for greater than parameter #35 in the electrical specifications section, the brown-out situation will reset the chip. A reset may not occur if VDD falls below the trippoint for less than parameter #35. The chip will remain in Brownout Reset until VDD rises above BVDD. The Power-up Timer will be invoked at that point and will keep the chip in RESET an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above BVDD, the Power-up Timer will again begin a 72 ms time delay. Even though the PWRT is always enabled when brown-out is enabled, the PWRT configuration word bit should be cleared (enabled) when brown-out is enabled. Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 133 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.8 Time-out Sequence Table 12-5 shows the reset conditions for some special function registers, while Table 12-6 shows the reset conditions for all the registers. On power-up the time-out sequence is as follows: First PWRT time-out is invoked by the POR pulse. When the PWRT delay expires the Oscillator Start-up Timer is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 12-7, Figure 12-8, Figure 129 and Figure 12-10 depict time-out sequences on power-up. 12.9 The Power Control/Status Register, PCON has two status bits that provide indication of which power-up type reset occurred. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is set on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR cleared, indicating a BOR occurred. However, if the brown-out circuitry is disabled, the BOR bit is a "Don’t Care" bit and is considered unknown upon a POR. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 12-9). This is useful for testing purposes or to synchronize more than one PICmicro microcontroller operating in parallel. TABLE 12-3 Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Configuration Brown-out Wake-up from SLEEP 1024TOSC 72 ms + 1024TOSC 1024TOSC — 72 ms — PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC RC 72 ms TABLE 12-4 Power Control/Status Register (PCON) STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 1 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 12-5 RESET CONDITION FOR SPECIAL REGISTERS Condition Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --01 MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu PC + 1 uuu0 0uuu ---- --uu 000h 0001 1uuu ---- --u0 uuu1 0uuu ---- --uu WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP PC + 1 (1) Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 133 774.book Page 134 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 12-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt uuuu uuuu W 773 774 xxxx xxxx uuuu uuuu INDF 773 774 N/A N/A N/A TMR0 773 774 xxxx xxxx uuuu uuuu uuuu uuuu PCL 773 774 0000h 0000h STATUS 773 774 0001 1xxx 000q quuu(3) uuuq quuu(3) PC + 1(2) FSR 773 774 xxxx xxxx uuuu uuuu uuuu uuuu PORTA 773 774 --0x 0000 --0u 0000 --uu uuuu PORTB 773 774 xxxx 11xx uuuu 11uu uuuu uuuu PORTC 773 774 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 773 774 xxxx xxxx uuuu uuuu uuuu uuuu PORTE 773 774 ---- -000 ---- -000 ---- -uuu PCLATH 773 774 ---0 0000 ---0 0000 ---u uuuu INTCON 773 774 0000 000x 0000 000u uuuu uuuu(1) PIR1 773 774 r000 0000 r000 0000 ruuu uuuu(1) 773 774 0000 0000 0000 0000 uuuu uuuu(1) PIR2 773 774 0--- 0--0 0--- 0--0 u--- u--u(1) TMR1L 773 774 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 773 774 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 773 774 --00 0000 --uu uuuu --uu uuuu TMR2 773 774 0000 0000 0000 0000 uuuu uuuu T2CON 773 774 -000 0000 -000 0000 -uuu uuuu SSPBUF 773 774 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 773 774 0000 0000 0000 0000 uuuu uuuu CCPR1L 773 774 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 773 774 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 773 774 --00 0000 --00 0000 --uu uuuu RCSTA 773 774 0000 000x 0000 000x uuuu uuuu TXREG 773 774 0000 0000 0000 0000 uuuu uuuu RCREG 773 774 0000 0000 0000 0000 uuuu uuuu CCPR2L 773 774 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 773 774 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 773 774 --00 0000 --00 0000 --uu uuuu ADRESH 773 774 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 773 774 0000 0000 0000 0000 uuuu uuuu OPTION_REG 773 774 1111 1111 1111 1111 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for reset value for specific condition. DS30275B-page 134 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 135 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 12-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d) Register Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt 773 774 ---1 1111 ---1 1111 ---u uuuu 773 774 --11 1111 --11 1111 --uu uuuu TRISB 773 774 1111 1111 1111 1111 uuuu uuuu TRISC 773 774 1111 1111 1111 1111 uuuu uuuu TRISD 773 774 1111 1111 1111 1111 uuuu uuuu TRISE 773 774 0000 -111 0000 -111 uuuu -uuu PIE1 773 774 r000 0000 r000 0000 ruuu uuuu 773 774 0000 0000 0000 0000 uuuu uuuu PIE2 773 774 0--- 0--0 0--- 0--0 u--- u--u PCON 773 774 ---- --qq ---- --uu ---- --uu PR2 773 774 1111 1111 1111 1111 1111 1111 SSPADD 773 774 0000 0000 0000 0000 uuuu uuuu SSPSTAT 773 774 0000 0000 0000 0000 uuuu uuuu TXSTA 773 774 0000 -010 0000 -010 uuuu -uuu SPBRG 773 774 0000 0000 0000 0000 uuuu uuuu REFCON 773 774 0000 ---- 0000 ---- uuuu ---- LVDCON 773 774 --00 0101 --00 0101 --uu uuuu ADRESL 773 774 xxxx xxxx uuuu uuuu uuuu uuuu ADCON1 773 774 0000 000 0000 0000 uuuu uuuu TRISA Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for reset value for specific condition. FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 135 774.book Page 136 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-10: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30275B-page 136 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 137 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The PIC16C77X family has up to 14 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. FIGURE 12-11: INTERRUPT LOGIC LVDIF LVDIE PSPIF PSPIE ADIF ADIE Wake-up (If in SLEEP mode) T0IF T0IE RCIF RCIE INTF INTE TXIF TXIE Interrupt to CPU RBIF RBIE SSPIF SSPIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE BCLIF BCLIE The following table shows which devices have which interrupts. LVDIF BCLIF CCP2IF PIC16C773 Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16C774 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 137 774.book Page 138 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.10.1 INT INTERRUPT 12.10.3 PORTB INTCON CHANGE External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 12.13 for details on SLEEP mode. An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2) 12.10.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 4.0) 12.11 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, i.e., W register and STATUS register. This will have to be implemented in software. Example 12-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The example: a) b) c) d) e) f) Stores the W register. Stores the STATUS register in bank 0. Stores the PCLATH register. Executes the interrupt service routine code (User-generated). Restores the STATUS register (and bank select bit). Restores the W and PCLATH registers. EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF BCF MOVF MOVWF : :(ISR) : MOVF MOVWF SWAPF W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH STATUS, IRP FSR, W FSR_TEMP ;Copy W to TEMP register, could be bank one or zero ;Swap status to be saved into W ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 ;Save status to bank zero STATUS_TEMP register ;Only required if using pages 1, 2 and/or 3 ;Save PCLATH into W ;Page zero, regardless of current page ;Return to Bank 0 ;Copy FSR to W ;Copy FSR from W to FSR_TEMP PCLATH_TEMP, W PCLATH STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W DS30275B-page 138 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 139 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.12 Watchdog Timer (WDT) The WDT can be permanently disabled by clearing configuration bit WDTE (Section 12.1). The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler may be assigned using the OPTION_REG register. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. . FIGURE 12-12: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 4-2) 0 WDT Timer Postscaler M U X 1 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Section 4-2) 0 1 MUX Note: PSA and PS2:PS0 are bits in the OPTION_REG register. PSA WDT Time-out FIGURE 12-13: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name 2007h Config. bits 81h,181h OPTION_REG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 12-1 for the full description of the configuration word bits. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 139 774.book Page 140 Tuesday, January 29, 2013 12:02 PM PIC16C77X 12.13 Power-down Mode (SLEEP) Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 12.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some Peripheral Interrupts. External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. 7. 8. 9. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 12.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. PSP read or write. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP capture mode interrupt. Special event trigger (Timer1 in asynchronous mode using an external clock). SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in slave mode (SPI/I2C). USART RX or TX (synchronous slave mode). A/D conversion (when A/D clock source is RC). Low-voltage detect. DS30275B-page 140 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 141 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 12-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 12.14 PC+1 PC+2 Inst(PC + 2) SLEEP Inst(PC + 1) 12.15 PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference. Program Verification/Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: PC+2 Inst(PC + 1) Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. 12.16 In-Circuit Serial Programming PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSP™) Guide, (DS30277). For ROM devices, these values are submitted along with the ROM code. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 141 774.book Page 142 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 142 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 143 Tuesday, January 29, 2013 12:02 PM PIC16C77X 13.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 13-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 13-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. Table 13-2 lists the instructions recognized by the MPASM assembler. Figure 13-1 shows the general formats that the instructions can have. Note: All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) OPCODE FIELD DESCRIPTIONS Field Description f Register file address (0x00 to 0x7F) Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label General x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 13 Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 PC Program Counter TO Time-out bit PD Power-down bit 0 b = 3-bit bit address f = 7-bit file register address W d 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. TABLE 13-1 To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions. Literal and control operations 8 7 OPCODE 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 0 k (literal) k = 11-bit immediate value The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations A description of each instruction is available in the PICmicro™ Mid-Range Reference Manual, (DS33023). All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 143 774.book Page 144 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 13-2 PIC16CXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z C C C,DC,Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk 1,2 1,2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W C,DC,Z Z TO,PD Z TO,PD C,DC,Z Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30275B-page 144 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 145 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.0 DEVELOPMENT SUPPORT 14.1 Development Tools The PICmicro microcontrollers are supported with a full range of hardware and software development tools: • MPLAB -ICEReal-Time In-Circuit Emulator • ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator • PRO MATE II Universal Programmer • PICSTART Plus Entry-Level Prototype Programmer • SIMICE • PICDEM-1 Low-Cost Demonstration Board • PICDEM-2 Low-Cost Demonstration Board • PICDEM-3 Low-Cost Demonstration Board • MPASM Assembler • MPLABSIM Software Simulator • MPLAB-C17 (C Compiler) • Fuzzy Logic Development System (fuzzyTECHMP) • KEELOQ® Evaluation Kits and Programmer 14.2 MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB IDE The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). MPLAB-ICE is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip microcontrollers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. 14.3 ICEPIC: Low-Cost PICmicro In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through Pentium based machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation. 14.4 PRO MATE II: Universal Programmer The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode. 14.5 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant. MPLAB-ICE is available in two versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PICmicro MCU. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 145 774.book Page 146 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.6 SIMICE Entry-Level Hardware Simulator 14.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip’s simulator MPLAB™-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entrylevel system development. The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad. 14.7 14.9 PICDEM-1 Low-Cost PICmicro Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. DS30275B-page 146 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 147 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.10 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: • A full featured editor • Three operating modes - editor - emulator - simulator • A project manager • Customizable tool bar and key mapping • A status bar with project information • Extensive on-line help 14.12 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. MPLAB allows you to: 14.13 • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) • Debug using: - source files - absolute listing file The MPLAB-C17 Code Development System is a complete ANSI ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 14.11 Assembler (MPASM) The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from MPLABICE, Microchip’s Universal Emulator System. MPASM has the following features to assist in developing software for specific use applications. • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability. • Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems. • Supports Hex (default), Decimal and Octal source and listing formats. MPLAB-C17 Compiler For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display. 14.14 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems. Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. 14.15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 147 774.book Page 148 Tuesday, January 29, 2013 12:02 PM PIC16C77X 14.16 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters. DS30275B-page 148 Advance Information 1999-2013 Microchip Technology Inc. Emulator Products Software Tools 1999-2013 Microchip Technology Inc. Programmers Advance Information HCS200 HCS300 HCS301 KEELOQ Transponder Kit 24CXX 25CXX 93CXX KEELOQ® Evaluation Kit PICDEM-3 PICDEM-2 PICDEM-1 PICDEM-14A SIMICE SEEVAL Designers Kit KEELOQ Programmer PRO MATE II Universal Programmer PICSTARTPlus Low-Cost Universal Dev. Kit Total Endurance Software Model fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev. Tool MPLAB C17* Compiler MPLAB Integrated Development Environment PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX ICEPIC Low-Cost In-Circuit Emulator MPLAB™-ICE PIC14000 TABLE 14-1 Demo Boards PIC12C5XX 774.book Page 149 Tuesday, January 29, 2013 12:02 PM PIC16C77X DEVELOPMENT TOOLS FROM MICROCHIP DS30275B-page 149 774.book Page 150 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 150 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 151 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +8.5V Voltage on RA4 with respect to Vss ..................................................................................................................0 to +8.5V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (combined) (Note 3)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) ..................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3) .............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE are not implemented on the PIC16C773. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 15-1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C773-04 PIC16C774-04 OSC PIC16C773-20 PIC16C774-20 PIC16LC773-04 PIC16LC774-04 JW Devices RC VDD: IDD: IPD: Freq: 4.0V to 5.5V 5 mA max. at 5.5V 16 A max. at 4V 4 MHz max. VDD: IDD: IPD: Freq: 4.5V to 5.5V 2.7 mA typ. at 5.5V 1.5 A typ. at 4V 4 MHz max. VDD: IDD: IPD: Freq: 2.5V to 5.5V 3.8 mA max. at 3.0V 5 A max. at 3V 4 MHz max. VDD: IDD: IPD: Freq: 4.0V to 5.5V 5 mA max. at 5.5V 16 A max. at 4V 4 MHz max. XT VDD: IDD: IPD: Freq: 4.0V to 5.5V 5 mA max. at 5.5V 16 A max. at 4V 4 MHz max. VDD: IDD: IPD: Freq: 4.5V to 5.5V 2.7 mA typ. at 5.5V 1.5 A typ. at 4V 4 MHz max. VDD: IDD: IPD: Freq: 2.5V to 5.5V 3.8 mA max. at 3.0V 5 A max. at 3V 4 MHz max. VDD: IDD: IPD: Freq: 4.0V to 5.5V 5 mA max. at 5.5V 16 A max. at 4V 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. LP VDD: 4.5V to 5.5V Not tested for functionality Freq: 20 MHz max. VDD: 4.0V to 5.5V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Not tested for functionality IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 151 774.book Page 152 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.1 DC Characteristics: PIC16C77X (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 — — 5.5 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR — 1.5 — V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR — VSS — V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 — — D010 Supply Current (Note 2) IDD — 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) — 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V — — 1.5 1.5 16 19 A A VDD = 4.0V, -0C to +70C VDD = 4.0V, -40C to +85C D013 D020 D020A Power-down Current (Note 3) IPD XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details. PWRT enabled Module Differential Current (Note 5) Watchdog Timer IWDT — 6.0 20 A VDD = 4.0V Brown-out Reset Current (Note 5) D023B* Bandgap voltage generator IBOR TBD 200 — A BOR enabled, VDD = 5.0V IBG6 — D025* Timer1 oscillator IT1OSC — 5 9 A VDD = 4.0V A/D Converter IAD — 300 — A VDD = 5.5V, A/D on, not converting D021 D023* D026* * † Note 1: 2: 3: 4: 5: 6: 40A TBD A These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. The current is the additional current consumed when the peripheral is enabled. This current should be added to the base (IPD or IDD) current. The bandgap voltate reference provides 1.22V to the VRL, VRH, LVD and BOR circuits. When calculating current consumption use the following formula: IVRL + IVRH + ILVD + IBOR + IBG. Any of the IVRL, IVRH, ILVD or IBOR can be 0. DS30275B-page 152 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 153 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.2 DC Characteristics:PIC16LC77X-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ† Max Units Conditions D001 Supply Voltage VDD 2.5 — 5.5 V D002* RAM Data Retention Voltage (Note 1) VDR — 1.5 — V D003 VPOR VDD start voltage to ensure internal Power-on Reset signal — VSS — V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 — — D010 Supply Current (Note 2) IDD — 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) — 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled — — 0.9 0.9 5 5 A A VDD = 3.0V, 0C to +70C VDD = 3.0V, -40C to +85C — 6 20 A VDD = 3.0V TBD 200 — A BOR enabled, VDD = 5.0V D010A D020 D020A Power-down Current (Note 3) IPD LP, XT, RC osc configuration (DC - 4 MHz) See section on Power-on Reset for details V/ms See section on Power-on Reset for details. PWRT enabled Module Differential Current (note5) IWDT D021 Watchdog Timer D023* Brown-out Reset Current IBOR (Note 5) D025* Timer1 oscillator IT1OSC — 1.5 3 A VDD = 3.0V D026* A/D Converter IAD — 300 — A VDD = 5.5V, A/D on, not converting * † Note 1: 2: 3: 4: 5: These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. The current is the additional current consumed when the peripheral is enabled. This current should be added to the base (IPD or IDD) current. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 153 774.book Page 154 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.3 DC Characteristics: PIC16C77X (Commercial, Industrial) DC CHARACTERISTICS Param No. D030 D030A D031 Characteristic Input Low Voltage I/O ports with TTL buffer VIL with Schmitt Trigger buffer RC3 and RC4 All others MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer D032 D033 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Sym Min Typ† Max Units Conditions D060 MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports (digital) D060A I/O ports (RA0-RA3, RA5, RB2, RB3 analog) D061 MCLR, RA4/T0CKI D063 OSC1 D080 Output Low Voltage I/O ports D083 OSC2/CLKOUT (RC osc config) — 0.15VDD 0.8V V V For entire VDD range 4.5V VDD 5.5V VSS VSS — — 0.3VDD 0.2VDD V I2C compliant For entire VDD range VSS VSS — 0.2VDD 0.3VDD V V Note1 — — 2.0 0.25VDD + 0.8V — — VDD VDD V V 4.5V VDD 5.5V For entire VDD range 0.7VDD 0.8VDD — — VDD VDD V V I2C compliant For entire VDD range 0.8VDD 0.7VDD 0.9VDD 50 IPURB — 250 VDD VDD VDD 400 V V V A with Schmitt Trigger buffer RC3 and RC4 All others D042 D042A D043 D070 — VIH D040 D040A D041 VSS VSS — — IIL — — 1 A IIL — — 100 nA — — — — 5 5 A A — — 0.6 V — — 0.6 V VOL Note1 VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C77X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30275B-page 154 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 155 Tuesday, January 29, 2013 12:02 PM PIC16C77X DC CHARACTERISTICS Param No. Characteristic D090 Output High Voltage I/O ports (Note 3) D092 OSC2/CLKOUT (RC osc config) D150* Open-Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin D100 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Sym Min Typ† Max Units Conditions VOH VDD - 0.7 — — V VDD - 0.7 — — V VOD — — 8.5 V COSC2 — — 15 pF IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. — — CIO 50 pF — — 400 pF CB mode) SCL, SDA in I2C mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C77X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. D101 D102 All I/O pins and OSC2 (in RC 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 155 774.book Page 156 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.4 DC Characteristics: VREF TABLE 15-2 ELECTRICAL CHARACTERISTICS: VREF DC CHARACTERISTICS Param No. D400 D401A D401B D402 D404 D405 D406 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Characteristic Output Voltage VRL Quiescent Supply Current VRH Quiescent Supply Current Ouput Voltage Drift External Load Source External Load Sink Load Regulation Symbol Min Typ† Max Units VRL VRH IVRL IVRH TCVOUT IVREFSO IVREFSI 2.0 4.0 — 2.048 4.096 70 70 15* — — — — V V A A ppm/°C mA mA — 1 2.1 4.2 TBD TBD 50* 5* -5* TBD* VOUT/ IOUT D407 Line Regulation VOUT/ VDD — — — 1 TBD* — — 50* mV/mA Conditions VDD 2.5V VDD 4.5V No load on VRL. No load on VRH. Note 1 Isource = 0 mA to 5 mA Isink = 0 mA to 5 mA V/V * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Production tested at TAMB = 25°C. Specifications over temp limits guaranteed by characterization. DS30275B-page 156 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 157 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-1: LOW-VOLTAGE DETECT CHARACTERISTICS VDD VLHYS VLVD (LVDIF set by hardware) LVDIF (LVDIF can be cleared in software anytime during the gray area) TABLE 15-3 ELECTRICAL CHARACTERISTICS: LVD DC CHARACTERISTICS Param No. D420 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Characteristic LVD Voltage LVV = 0100 LVV = 0101 LVV = 0110 LVV = 0111 LVV = 1000 LVV = 1001 LVV = 1010 LVV = 1011 LVV = 1100 LVV = 1101 LVV = 1110 Symbol Min Typ† Max Units 2.5 2.7 2.8 3.0 3.3 3.5 3.6 3.8 4.0 4.2 4.5 2.58 2.78 2.89 3.1 3.41 3.61 3.72 3.92 4.13 4.33 4.64 10 15 2.66 2.86 2.98 3.2 3.52 3.72 3.84 4.04 4.26 4.46 4.78 20 50 V V V V V V V V V V V A ppm/°C Conditions — Supply Current ILVD — LVD Voltage Drift Temperature TCVOUT coefficient — — 50 V/V VLVD/ D423* LVD Voltage Drift with respect to VDD VDD Regulation TBD — 100 mV D424* Low-voltage Detect Hysteresis VLHYS * These parameters are characterized but not tested. Note 1: Production tested at Tamb = 25°C. Specifications over temp limits ensured by characterization. D421 D422* 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 157 774.book Page 158 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-2: BROWN-OUT RESET CHARACTERISTICS VDD (device not in Brown-out Reset) VBHYS VBOR (device in Brown-out Reset) RESET (due to BOR) TABLE 15-4 72 ms time out ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Characteristic Symbol Min Typ Max Units Conditions 2.5 2.58 2.66 BORV1:0 = 11 BORV1:0 = 10 2.7 2.78 2.86 VBOR V BORV1:0 = 01 4.2 4.33 4.46 BORV1:0 = 00 4.5 4.64 4.78 — 15 50 ppm/°C D006* BOR Voltage Drift Temperature coef- TCVOUT ficient — — 50 V/V VBOR/ D006A* BOR Voltage Drift with respect to VDD VDD Regulation TBD — 100 mV D007 Brown-out Hysteresis VBHYS — 10 20 A D022A Supply Current IBOR * These parameters are characterized but not tested. Note 1: Production tested at TAMB = 25°C. Specifications over temp limits ensured by characterization. D005 BOR Voltage DS30275B-page 158 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 159 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.5 AC Characteristics: PIC16C77X (Commercial, Industrial) 15.5.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition 1999-2013 Microchip Technology Inc. T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition Advance Information DS30275B-page 159 774.book Page 160 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-3: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C773. DS30275B-page 160 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 161 Tuesday, January 29, 2013 12:02 PM PIC16C77X 15.5.2 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKOUT TABLE 15-5 Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) Max Units Conditions DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode 0.1 — 4 MHz XT osc mode 4 5 — — 20 200 MHz kHz HS osc mode LP osc mode 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC TosL, TosH External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator 2.5 — — s LP oscillator TosR, TosF External Clock in (OSC1) Rise or Fall Time 2 TCY 3* 4* Typ† 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 161 774.book Page 162 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-5: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 15-3 for load conditions. TABLE 15-6 CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No. Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT 0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT 0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16C77X 100 — — ns PIC16LC77X 200 — — ns ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — 20* TioR Port output rise time PIC16C77X — 10 25 ns PIC16LC77X — — 60 ns PIC16C77X — 10 25 ns PIC16LC77X — — 60 ns 21* TioF Port output fall time 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns Note 1 * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30275B-page 162 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 163 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 15-3 for load conditions. FIGURE 15-7: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 15-7 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER,POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic Min 30* TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40°C to +85°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +85°C 32* Tost 33* Tpwrt 34* 35* * † Typ† Max Units Conditions Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C TIOZ I/O Hi-impedance from MCLR Low or Watchdog Timer Reset — — 100 ns TBOR Brown-out Reset pulse width 100 — — s VDD VBOR (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 163 774.book Page 164 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-8: BANDGAP START-UP TIME VBGAP = 1.2V VBGAP Enable Bandgap TBGAP Bandgap stable TABLE 15-8 BANDGAP START-UP TIME Parameter No. Sym 36* TBGAP * † Characteristic Bandgap start-up time Min Typ† Max Units Conditions — 30 TBD s Defined as the time between the instant that the bandgap is enabled and the moment that the bandgap reference voltage is stable. These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30275B-page 164 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 165 Tuesday, January 29, 2013 12:02 PM PIC16C77X TABLE 15-9 Param No. Sym A01 NR A03 A/D CONVERTER CHARACTERISTICS: Characteristic Min Typ† Max Units Conditions Resolution — — 12 bits bit Min. resolution for A/D is 1 mV, VREF+ = AVDD = 4.096V, VREF- = AVSS = 0V, VREF- VAIN VREF+ EIL Integral error — — +/-2 LSb — VREF+ = AVDD = 4.096V, VREF- = AVSS = 0V, VREF- VAIN VREF+ A04 EDL Differential error — — +2 LSb -1 LSb — No missing codes to 12-bits VREF+ = AVDD = 4.096V, VREF- = AVSS = 0V, VREF- VAIN VREF+ A06 EOFF Offset error — — less than 2 LSb — VREF+ = AVDD = 4.096V, VREF- = AVSS = 0V, VREF- VAIN VREF+ A07 EGN Gain Error — — +/- 2LSb LSb VREF+ = AVDD = 4.096V, VREF- = AVSS = 0V, VREF- VAIN VREF+ A10 — Monotonicity — guaranteed(3) — — AVSS VAIN VREF+ A20 VREF Reference voltage (VREF+ VREF-) 4.096 — VDD +0.3V V Absolute minimum electrical spec to ensure 12-bit accuracy. A21 VREF+ Reference V High (AVDD or VREF+) VREF- — AVDD V Min. resolution for A/D is 1 mV A22 VREF- Reference V Low (AVSS or VREF-) AVSS — VREF+ V Min. resolution for A/D is 1 mV A25 VAIN Analog input voltage VREFL — VREFH V A30 ZAIN Recommended impedance of analog voltage source — — 2.5 k A50 IREF VREF input current (Note 2) — — 10 A During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD see Section 11.0. During A/D conversion cycle. * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power down current spec includes any such leakage from the A/D module. 2: VREF current is from External VREF+, OR VREF-, or AVSS, or AVDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 165 774.book Page 166 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-9: A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1/2 Tcy 134 131 Q4 130 A/D CLK 9 A/D DATA 8 7 6 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE 132 SAMPLE Note 1: SAMPLING STOPPED If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-10 A/D CONVERSION REQUIREMENTS Parameter No. Sym Characteristic Min Typ† Max Units 130* TAD A/D clock period 1.6 — — s Tosc based, VREF 2.5V 3.0 — — s Tosc based, VREF full range 130* TAD A/D Internal RC oscillator period 3.0 6.0 9.0 s 2.0 4.0 6.0 s At VDD = 5.0V — 13TAD — TAD Set GO bit to new data in A/D result register Note 2 11.5 — s 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1LSb (i.e 1mV @ 4.096V) from the last sampled voltage (as stated on CHOLD). — TOSC/2 — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 131* TCNV Conversion time (not including acquisition time) (Note 1) 132* TACQ Acquisition Time 134* TGO Q4 to A/D clock start Conditions ADCS1:ADCS0 = 11 (RC mode) At VDD = 2.5V * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 11.6 for minimum conditions. DS30275B-page 166 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 167 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-10: A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 131 Q4 130 A/D CLK 9 A/D DATA 8 7 6 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-11 A/D CONVERSION REQUIREMENTS Parameter No. Sym Characteristic 130* TAD A/D clock period 130* TAD A/D Internal RC oscillator period 131* TCNV Conversion time (not including acquisition time)(Note 1) 132* TACQ Acquisition Time 134* SAMPLING STOPPED TGO Q4 to A/D clock start Min Typ† Max Units Conditions 1.6 — — s VREF 2.5V TBD — — s VREF full range 3.0 6.0 9.0 s ADCS1:ADCS0 = 11 (RC mode) At VDD = 3.0V 2.0 4.0 6.0 s At VDD = 5.0V — 13TAD — — Note 2 11.5 — s 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1LSb (i.e 1mV @ 4.096V) from the last sampled voltage (as stated on CHOLD). — TOSC/2 + TCY — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 11.6 for minimum conditions. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 167 774.book Page 168 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 15-3 for load conditions. TABLE 15-12 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.5TCY + 20 — — ns 10 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — ns — — — — — 50 ns ns kHz — 7Tosc — 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C77X 15 Prescaler = PIC16LC77X 25 2,4,8 Asynchronous PIC16C77X 30 PIC16LC77X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C77X 15 Prescaler = PIC16LC77X 25 2,4,8 Asynchronous PIC16C77X 30 PIC16LC77X 50 Tt1P T1CKI input period Synchronous PIC16C77X Greater of: 30 OR TCY + 40 N PIC16LC77X Greater of: 50 OR TCY + 40 N Asynchronous PIC16C77X 60 PIC16LC77X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Tt0L Typ† Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30275B-page 168 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 169 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-12: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 15-3 for load conditions. TABLE 15-13 Parameter No. 50* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic TccL CCP1 and CCP2 input low time Min No Prescaler PIC16C77X With Prescaler PIC16LC77X 51* TccH CCP1 and CCP2 input high time No Prescaler PIC16C77X With Prescaler PIC16LC77X 52* TccP CCP1 and CCP2 input period 53* TccR CCP1 and CCP2 output fall time 54* * † TccF CCP1 and CCP2 output fall time Typ† Max Units Conditions 0.5TCY + 20 — — ns 10 — — ns ns 20 — — 0.5TCY + 20 — — ns 10 — — ns 20 — — ns 3TCY + 40 N — — ns PIC16C77X — 10 25 ns PIC16LC77X — 25 45 ns PIC16C77X — 10 25 ns PIC16LC77X — 25 45 ns N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 169 774.book Page 170 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-13: PARALLEL SLAVE PORT TIMING (PIC16C774) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 15-3 for load conditions. TABLE 15-14 Parameter No. 62* 63* PARALLEL SLAVE PORT REQUIREMENTS (PIC16C774) Sym Characteristic Min Typ† Max Units TdtV2wrH Data in valid before WR or CS (setup time) TwrH2dtI WR or CS to data–in invalid (hold time) PIC16C774 PIC16LC774 64* 65* * † TrdL2dtV TrdH2dtI RD and CS to data–out valid RD or CS to data–out invalid 20 25 — — — — ns ns 20 — — ns 35 — — ns — — — — 80 90 ns ns 10 — 30 ns Conditions Extended Temperature Range Only Extended Temperature Range Only These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30275B-page 170 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 171 Tuesday, January 29, 2013 12:02 PM PIC16C77X FIGURE 15-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 15-3 for load conditions. TABLE 15-15 Param No. 120* USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Sym Characteristic TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid Min Typ† Max Units Conditions PIC16C774/773 — — 80 PIC16LC774/773 — — 100 ns ns 121* Tckrf Clock out rise time and fall time PIC16C774/773 (Master Mode) PIC16LC774/773 — — 45 ns — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16C774/773 — — 45 ns PIC16LC774/773 — — 50 ns * †: These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 15-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 15-3 for load conditions. TABLE 15-16 Parameter No. * †: USART SYNCHRONOUS RECEIVE REQUIREMENTS Sym Characteristic Min Typ† Max Units Conditions 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK (DT hold time) 15 — — ns These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 171 774.book Page 172 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 172 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 173 Tuesday, January 29, 2013 12:02 PM PIC16C77X 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'min' represents (mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range. Graphs and Tables not available at this time. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 173 774.book Page 174 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 174 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 175 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example PIC16C773-20/SP XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX AABBCDE 28-Lead CERDIP Windowed 1317HAT Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX AABBCDE 28-Lead SOIC PIC16C774/JW 1305HAT Example XXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXX AABBCDE 28-Lead SSOP PIC16C773-20/SO 1310SAA Example XXXXXXXXXXXX XXXXXXXXXXXX PIC16C773 20I/SS AABBCAE Legend: MM...M XX...X AA BB C D E Note: * 9817SBP Microchip part number information Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5” Line S = 6” Line H = 8” Line Mask revision number Assembly code of the plant or country of origin in which part was assembled In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 175 774.book Page 176 Tuesday, January 29, 2013 12:02 PM PIC16C77X Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX AABBCDE PIC16C774-04/P 1312SAA 40-Lead CERDIP Windowed Example XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX AABBCDE 44-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE 44-Lead MQFP XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE 44-Lead PLCC XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE DS30275B-page 176 PIC16C774/JW 1305HAT Example PIC16C774 -04/PT 1311HAT Example PIC16C774 -20/PQ 1304SAT Example PIC16C774 -04/L 1303SAT Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 177 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.2 K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E D 2 n 1 E1 A1 A R L c B1 A2 eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom p B INCHES* NOM 0.300 28 0.100 0.019 0.016 0.053 0.040 0.005 0.000 0.010 0.008 0.150 0.140 0.090 0.070 0.020 0.015 0.130 0.125 1.365 1.345 0.288 0.280 0.270 0.283 0.320 0.350 5 10 5 10 MIN n p B B1† R c A A1 A2 L D‡ E‡ E1 eB MAX 0.022 0.065 0.010 0.012 0.160 0.110 0.025 0.135 1.385 0.295 0.295 0.380 15 15 MILLIMETERS NOM MAX 7.62 28 2.54 0.48 0.41 0.56 1.33 1.02 1.65 0.13 0.00 0.25 0.25 0.20 0.30 3.81 3.56 4.06 2.29 1.78 2.79 0.51 0.38 0.64 3.30 3.18 3.43 34.67 34.16 35.18 7.11 7.30 7.49 6.86 7.18 7.49 8.13 8.89 9.65 5 10 15 5 10 15 MIN * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 177 774.book Page 178 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.3 K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E D W2 2 n 1 W1 E1 A R A1 L c eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Width Window Length B1 B A2 MIN n p B B1 R c A A1 A2 L D E E1 eB W1 W2 0.098 0.016 0.050 0.010 0.008 0.170 0.107 0.015 0.135 1.430 0.285 0.255 0.345 0.130 0.290 INCHES* NOM 0.300 28 0.100 0.019 0.058 0.013 0.010 0.183 0.125 0.023 0.140 1.458 0.290 0.270 0.385 0.140 0.300 p MAX 0.102 0.021 0.065 0.015 0.012 0.195 0.143 0.030 0.145 1.485 0.295 0.285 0.425 0.150 0.310 MILLIMETERS NOM MAX 7.62 28 2.54 2.59 2.49 0.47 0.53 0.41 1.46 1.65 1.27 0.32 0.38 0.25 0.25 0.30 0.20 4.32 4.64 4.95 3.63 3.18 2.72 0.76 0.57 0.00 3.68 3.56 3.43 37.72 37.02 36.32 7.49 7.37 7.24 7.24 6.86 6.48 10.80 9.78 8.76 0.15 0.14 0.13 0.31 0.3 0.29 MIN * Controlling Parameter. DS30275B-page 178 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 179 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.4 K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E p D B 2 1 n X 45 ° L R2 c A Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A1 R1 L1 A2 INCHES* NOM 0.050 28 0.093 0.099 0.048 0.058 0.004 0.008 0.700 0.706 0.292 0.296 0.394 0.407 0.010 0.020 0.005 0.005 0.005 0.005 0.011 0.016 0 4 0.010 0.015 0.009 0.011 0.014 0.017 0 12 0 12 MIN p n A A1 A2 D‡ E‡ E1 X R1 R2 L L1 c B† MAX 0.104 0.068 0.011 0.712 0.299 0.419 0.029 0.010 0.010 0.021 8 0.020 0.012 0.019 15 15 MILLIMETERS NOM MAX 1.27 28 2.36 2.50 2.64 1.22 1.47 1.73 0.10 0.19 0.28 17.93 17.78 18.08 7.42 7.51 7.59 10.01 10.33 10.64 0.25 0.50 0.74 0.13 0.13 0.25 0.13 0.13 0.25 0.28 0.41 0.53 8 0 4 0.25 0.38 0.51 0.23 0.27 0.30 0.36 0.42 0.48 0 12 15 0 12 15 MIN * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 179 774.book Page 180 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.5 K04-073 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E p D B 2 1 n L A R2 c A1 R1 A2 L1 Units Dimension Limits Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom INCHES NOM 0.026 28 0.068 0.073 0.026 0.036 0.002 0.005 0.396 0.402 0.205 0.208 0.301 0.306 0.005 0.005 0.005 0.005 0.015 0.020 0 4 0.000 0.005 0.005 0.007 0.010 0.012 0 5 0 5 MIN p n A A1 A2 D‡ E‡ E1 R1 R2 L L1 c B† MAX 0.078 0.046 0.008 0.407 0.212 0.311 0.010 0.010 0.025 8 0.010 0.009 0.015 10 10 MILLIMETERS* NOM MAX 0.65 28 1.73 1.86 1.99 0.66 0.91 1.17 0.05 0.13 0.21 10.07 10.20 10.33 5.20 5.29 5.38 7.65 7.78 7.90 0.13 0.13 0.25 0.13 0.13 0.25 0.38 0.51 0.64 0 4 8 0.00 0.13 0.25 0.13 0.18 0.22 0.25 0.32 0.38 0 5 10 0 5 10 MIN * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” DS30275B-page 180 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 181 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.6 K04-016 40-Lead Plastic Dual In-line (P) – 600 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E D 2 1 n A1 E1 A R L c B1 eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom A2 INCHES* NOM 0.600 40 0.100 0.016 0.018 0.045 0.050 0.000 0.005 0.009 0.010 0.110 0.160 0.093 0.073 0.020 0.020 0.125 0.130 2.018 2.013 0.530 0.535 0.545 0.565 0.630 0.610 5 10 5 10 MIN n p B B1† R c A A1 A2 L D‡ E‡ E1 eB p B MAX 0.020 0.055 0.010 0.011 0.160 0.113 0.040 0.135 2.023 0.540 0.585 0.670 15 15 MILLIMETERS NOM MAX 15.24 40 2.54 0.46 0.51 0.41 1.40 1.14 1.27 0.00 0.13 0.25 0.23 0.25 0.28 2.79 4.06 4.06 1.85 2.36 2.87 0.51 0.51 1.02 3.18 3.30 3.43 51.13 51.26 51.38 13.46 13.59 13.72 13.84 14.35 14.86 16.00 15.49 17.02 5 10 15 5 10 15 MIN * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 181 774.book Page 182 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.7 K04-014 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E W D 2 1 n A1 E1 A R L c B1 B eB A2 Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Radius to Radius Width Overall Row Spacing Window Diameter * MIN n p B B1 R c A A1 A2 L D E E1 eB W 0.098 0.016 0.050 0.000 0.008 0.190 0.117 0.030 0.135 2.040 0.514 0.560 0.610 0.340 INCHES* NOM 0.600 40 0.100 0.020 0.053 0.005 0.011 0.205 0.135 0.045 0.140 2.050 0.520 0.580 0.660 0.350 MAX 0.102 0.023 0.055 0.010 0.014 0.220 0.153 0.060 0.145 2.060 0.526 0.600 0.710 0.360 p MILLIMETERS NOM MAX 15.24 40 2.49 2.54 2.59 0.41 0.50 0.58 1.40 1.27 1.33 0.00 0.13 0.25 0.20 0.28 0.36 4.83 5.21 5.59 2.97 3.43 3.89 1.52 0.00 1.14 3.43 3.56 3.68 51.82 52.07 52.32 13.06 13.21 13.36 14.22 14.73 15.24 15.49 16.76 18.03 8.64 8.89 9.14 MIN Controlling Parameter. DS30275B-page 182 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 183 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.8 K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E # leads = n1 p D D1 2 1 B n X x 45° L A R2 c L1 R1 Units Dimension Limits Pitch Number of Pins Pins along Width Overall Pack. Height Shoulder Height Standoff Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Outside Tip Length Outside Tip Width Molded Pack. Length Molded Pack. Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom MIN p n n1 A A1 A2 R1 R2 L L1 c B† D1 E1 D‡ E‡ X 0.039 0.015 0.002 0.003 0.003 0.005 0 0.003 0.004 0.012 0.463 0.463 0.390 0.390 0.025 5 5 A1 A2 INCHES NOM 0.031 44 11 0.043 0.025 0.004 0.003 0.006 0.010 3.5 0.008 0.006 0.015 0.472 0.472 0.394 0.394 0.035 10 12 MAX 0.047 0.035 0.006 0.010 0.008 0.015 7 0.013 0.008 0.018 0.482 0.482 0.398 0.398 0.045 15 15 MILLIMETERS* NOM MAX 0.80 44 11 1.20 1.00 1.10 0.89 0.38 0.64 0.15 0.05 0.10 0.25 0.08 0.08 0.20 0.08 0.14 0.38 0.25 0.13 7 0 3.5 0.33 0.08 0.20 0.20 0.09 0.15 0.45 0.30 0.38 12.25 11.75 12.00 12.25 11.75 12.00 9.90 10.00 10.10 10.10 9.90 10.00 1.14 0.64 0.89 5 15 10 5 15 12 MIN * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent:MS-026 ACB 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 183 774.book Page 184 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.9 K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E # leads = n1 p D D1 2 1 B n X x 45° L R2 c A R1 L1 Units Dimension Limits Pitch Number of Pins Pins along Width Overall Pack. Height Shoulder Height Standoff Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Outside Tip Length Outside Tip Width Molded Pack. Length Molded Pack. Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom MIN p n n1 A A1 A2 R1 R2 L L1 c B† D1 E1 D‡ E‡ X 0.079 0.032 0.002 0.005 0.005 0.015 0 0.011 0.005 0.012 0.510 0.510 0.390 0.390 0.025 5 5 A1 A2 INCHES NOM 0.031 44 11 0.086 0.044 0.006 0.005 0.012 0.020 3.5 0.016 0.007 0.015 0.520 0.520 0.394 0.394 0.035 10 12 MAX 0.093 0.056 0.010 0.010 0.015 0.025 7 0.021 0.009 0.018 0.530 0.530 0.398 0.398 0.045 15 15 MILLIMETERS* NOM MAX 0.80 44 11 2.00 2.18 2.35 0.81 1.11 1.41 0.05 0.15 0.25 0.13 0.25 0.13 0.13 0.30 0.38 0.51 0.38 0.64 3.5 7 0 0.41 0.28 0.53 0.13 0.18 0.23 0.37 0.30 0.45 13.20 13.45 12.95 13.20 13.45 12.95 10.10 9.90 10.00 10.10 9.90 10.00 0.89 1.143 0.635 15 5 10 15 5 12 MIN * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent:MS-022 AB DS30275B-page 184 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 185 Tuesday, January 29, 2013 12:02 PM PIC16C77X 17.10 K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 E # leads = n1 D D1 n 12 CH2 x 45° A3 CH1 x 45° R1 L 35° A1 R2 c A B1 B A2 p E2 Units Dimension Limits Number of Pins Pitch Overall Pack. Height Shoulder Height Standoff Side 1 Chamfer Dim. Corner Chamfer (1) Corner Chamfer (other) Overall Pack. Width Overall Pack. Length Molded Pack. Width Molded Pack. Length Footprint Width Footprint Length Pins along Width Lead Thickness Upper Lead Width Lower Lead Width Upper Lead Length Shoulder Inside Radius J-Bend Inside Radius Mold Draft Angle Top Mold Draft Angle Bottom D2 INCHES* NOM 44 0.050 0.165 0.173 0.095 0.103 0.015 0.023 0.024 0.029 0.040 0.045 0.000 0.005 0.685 0.690 0.685 0.690 0.650 0.653 0.650 0.653 0.610 0.620 0.610 0.620 11 0.008 0.010 0.026 0.029 0.015 0.018 0.050 0.058 0.003 0.005 0.015 0.025 0 5 0 5 MIN n p A A1 A2 A3 CH1 CH2 E1 D1 E‡ D‡ E2 D2 n1 c B1† B L R1 R2 MAX 0.180 0.110 0.030 0.034 0.050 0.010 0.695 0.695 0.656 0.656 0.630 0.630 0.012 0.032 0.021 0.065 0.010 0.035 10 10 MILLIMETERS NOM MAX 44 1.27 4.19 4.57 4.38 2.41 2.60 2.79 0.38 0.76 0.57 0.61 0.74 0.86 1.02 1.27 1.14 0.00 0.13 0.25 17.40 17.53 17.65 17.40 17.53 17.65 16.51 16.59 16.66 16.51 16.66 16.59 15.49 15.75 16.00 15.49 15.75 16.00 11 0.20 0.25 0.30 0.66 0.74 0.81 0.38 0.46 0.53 1.27 1.46 1.65 0.08 0.13 0.25 0.38 0.64 0.89 0 5 10 0 5 10 MIN * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent:MO-047 AC 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 185 774.book Page 186 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 186 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 187 Tuesday, January 29, 2013 12:02 PM PIC16C77X APPENDIX A: REVISION HISTORY Version Date Revision Description A 1999 This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C7X Data Sheet, DS30390E. B 2013 Added a note to each package drawing. APPENDIX B: DEVICE DIFFERENCES The differences between the devices in this data sheet are listed in Table B-1. TABLE B-1: DEVICE DIFFERENCES Difference PIC16C773 PIC16C774 A/D 6 channels, 12 bits 10 channels, 12 bits Parallel Slave Port no yes Packages 28-pin PDIP, 28-pin windowed CERDIP, 28-pin SOIC, 28-pin SSOP 40-pin PDIP, 40-pin windowed CERDIP, 44-pin TQFP, 44-pin MQFP, 44-pin PLCC APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in the following: RA2 RA3 RA5 Pin 11 Pin 12 RB1 RB2 RB3 Added VREF- and VRL Added VREF+ and VRH Removed SS AVDD vs. VDD AVSS vs. VSS Added SS, SS is now ST vs. TTL Added AN8 Added AN9 and LVDIN PIC16C773 vs. PIC16C73A • • • • • • • RA2 RA3 Pin 7 Pin 8 RB1 RB2 RB3 Added VREF- and VRL Added VREF+ and VRH AVDD vs. removed RA5/SS/AN4 AVSS vs. VSS Added SS, SS is now ST vs. TTL Added AN8 Added AN9 and LVDIN 1999-2013 Microchip Technology Inc. none Data Memory Differences PIC16C774 vs. PIC16C74A • • • • • • • • Program Memory Differences 1. 2. Data memory size has increased to 256 from 192 by adding bank 2. Bank 1 locations 0xF0 - 0xFF are now common RAM locations across banks 0-3. Peripheral Differences 1. 2. 3. 4. 5. 6. 12-bit A/D replaces 8-bit A/D. Master Synchronous Serial Port replace Synchronous Serial Port. USART adds 9-bit address mode to module. Bandgap Voltage Reference added. Low-voltage Detect Module added. Selectable Brown-out Reset voltages added. Advance Information DS30275B-page 187 774.book Page 188 Tuesday, January 29, 2013 12:02 PM PIC16C77X NOTES: DS30275B-page 188 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 189 Tuesday, January 29, 2013 12:02 PM PIC16C77X INDEX C A Capture (CCP Module) ...................................................... 48 Block Diagram ........................................................... 48 CCP Pin Configuration .............................................. 48 CCPR1H:CCPR1L Registers .................................... 48 Changing Between Capture Prescalers .................... 48 Software Interrupt ...................................................... 48 Timer1 Mode Selection .............................................. 48 Capture/Compare/PWM (CCP) ......................................... 47 CCP1 ......................................................................... 47 CCP1CON Register ........................................... 47 CCPR1H Register ............................................. 47 CCPR1L Register .............................................. 47 Enable (CCP1IE Bit) .......................................... 19 Flag (CCP1IF Bit) .............................................. 20 RC2/CCP1 Pin ................................................. 7, 9 CCP2 ......................................................................... 47 CCP2CON Register ........................................... 47 CCPR2H Register ............................................. 47 CCPR2L Register .............................................. 47 Enable (CCP2IE Bit) .......................................... 21 Flag (CCP2IF Bit) .............................................. 22 RC1/T1OSI/CCP2 Pin ..................................... 7, 9 Interaction of Two CCP Modules ............................... 47 Timer Resources ....................................................... 47 CCP1CON ......................................................................... 15 CCP1CON Register ........................................................... 47 CCP1M3:CCP1M0 Bits ............................................. 47 CCP1X:CCP1Y Bits ................................................... 47 CCP2CON ......................................................................... 15 CCP2CON Register ........................................................... 47 CCP2M3:CCP2M0 Bits ............................................. 47 CCP2X:CCP2Y Bits ................................................... 47 CCPR1H Register ........................................................ 13, 15 CCPR1L Register .............................................................. 15 CCPR2H Register ........................................................ 13, 15 CCPR2L Register ........................................................ 13, 15 CKE ................................................................................... 54 CKP ................................................................................... 55 Clock Polarity Select bit, CKP ............................................ 55 Code Examples Loading the SSPBUF register ................................... 58 Code Protection ....................................................... 127, 141 Compare (CCP Module) .................................................... 49 Block Diagram ........................................................... 49 CCP Pin Configuration .............................................. 49 CCPR1H:CCPR1L Registers .................................... 49 Software Interrupt ...................................................... 49 Special Event Trigger .......................................... 43, 49 Timer1 Mode Selection .............................................. 49 Configuration Bits ............................................................ 127 Conversion Considerations .............................................. 187 A/D ................................................................................... 117 A/D Converter Enable (ADIE Bit) ............................... 19 A/D Converter Flag (ADIF Bit) ................................... 20 ADCON0 Register .................................................... 117 ADCON1 Register ............................................ 117, 118 ADRES Register ...................................................... 117 Analog Port Pins ...................................... 7, 8, 9, 36, 37 Block Diagram .......................................................... 120 Configuring Analog Port ........................................... 119 Conversion time ....................................................... 125 Conversions ............................................................. 121 converter characteristics .................. 156, 157, 158, 165 Faster Conversion - Lower Resolution Tradeoff ...... 125 Internal Sampling Switch (Rss) Impedence ............. 123 Operation During Sleep ........................................... 126 Sampling Requirements ........................................... 123 Sampling Time ......................................................... 123 Source Impedance ................................................... 123 Special Event Trigger (CCP) ...................................... 49 A/D Conversion Clock ...................................................... 121 ACK .................................................................................... 64 Acknowledge Data bit, AKD ............................................... 56 Acknowledge Pulse ............................................................ 64 Acknowledge Sequence Enable bit, AKE .......................... 56 Acknowledge Status bit, AKS ............................................ 56 ADCON0 Register ............................................................ 117 ADCON1 Register .................................................... 117, 118 ADRES ............................................................................. 117 ADRES Register .......................................... 13, 14, 117, 126 AKD .................................................................................... 56 AKE .................................................................................... 56 AKS .............................................................................. 56, 79 Application Note AN578, "Use of the SSP Module in the I2C Multi-Master Environment." ................... 63 Architecture PIC16C63A/PIC16C73B Block Diagram ...................... 5 PIC16C65B/PIC16C74B Block Diagram ...................... 6 Assembler MPASM Assembler .................................................. 147 B Banking, Data Memory ................................................ 11, 16 Baud Rate Generator ......................................................... 73 BF .................................................................... 54, 64, 79, 82 Block Diagrams Baud Rate Generator ................................................. 73 I2C Master Mode ........................................................ 71 I2C Module ................................................................. 63 SSP (I2C Mode) ......................................................... 63 SSP (SPI Mode) ......................................................... 57 BOR. See Brown-out Reset BRG ................................................................................... 73 Brown-out Reset (BOR) ................... 127, 131, 132, 133, 134 BOR Status (BOR Bit) ................................................ 23 Buffer Full bit, BF ............................................................... 64 Buffer Full Status bit, BF .................................................... 54 Bus Arbitration ................................................................... 90 Bus Collision Section ....................................................................... 90 Bus Collision During a RESTART Condition ...................... 93 Bus Collision During a Start Condition ............................... 91 Bus Collision During a Stop Condition ............................... 94 1999-2013 Microchip Technology Inc. D D/A ..................................................................................... 54 Data Memory ..................................................................... 11 Bank Select (RP1:RP0 Bits) ................................ 11, 16 General Purpose Registers ....................................... 11 Register File Map ...................................................... 12 Special Function Registers ........................................ 13 Data/Address bit, D/A ........................................................ 54 DC Characteristics PIC16C73 ................................................................ 152 PIC16C74 ................................................................ 152 Development Support ...................................................... 145 Development Tools .......................................................... 145 Device Differences ........................................................... 187 Direct Addressing .............................................................. 25 DS30275B-page 189 774.book Page 190 Tuesday, January 29, 2013 12:02 PM PIC16C77X E Errata ................................................................................... 4 External Power-on Reset Circuit ...................................... 132 F Firmware Instructions ....................................................... 143 Flowcharts Acknowledge .............................................................. 86 Master Receiver ......................................................... 83 Master Transmit ......................................................... 80 Restart Condition ....................................................... 77 Start Condition ........................................................... 75 Stop Condition ........................................................... 88 FSR Register .......................................................... 13, 14, 15 Fuzzy Logic Dev. System (fuzzyTECH-MP) .................. 147 G GCE ................................................................................... 56 General Call Address Sequence ........................................ 69 General Call Address Support ........................................... 69 General Call Enable bit, GCE ............................................ 56 I I/O Ports ............................................................................. 27 I2C ...................................................................................... 63 I2C Master Mode Receiver Flowchart ................................ 83 I2C Master Mode Reception ............................................... 82 I2C Master Mode Restart Condition ................................... 76 I2C Mode Selection ............................................................ 63 I2C Module Acknowledge Flowchart ............................................. 86 Acknowledge Sequence timing .................................. 85 Addressing ................................................................. 64 Baud Rate Generator ................................................. 73 Block Diagram ............................................................ 71 BRG Block Diagram ................................................... 73 BRG Reset due to SDA Collision ............................... 92 BRG Timing ............................................................... 73 Bus Arbitration ........................................................... 90 Bus Collision .............................................................. 90 Acknowledge ...................................................... 90 Restart Condition ............................................... 93 Restart Condition Timing (Case1) ...................... 93 Restart Condition Timing (Case2) ...................... 93 Start Condition ................................................... 91 Start Condition Timing ................................. 91, 92 Stop Condition ................................................... 94 Stop Condition Timing (Case1) .......................... 94 Stop Condition Timing (Case2) .......................... 94 Transmit Timing ................................................. 90 Bus Collision timing .................................................... 90 Clock Arbitration ......................................................... 89 Clock Arbitration Timing (Master Transmit) ................ 89 Conditions to not give ACK Pulse .............................. 64 General Call Address Support ................................... 69 Master Mode .............................................................. 71 Master Mode 7-bit Reception timing .......................... 84 Master Mode Operation ............................................. 72 Master Mode Start Condition ..................................... 74 Master Mode Transmission ........................................ 79 Master Mode Transmit Sequence .............................. 72 Master Transmit Flowchart ........................................ 80 Multi-Master Communication ..................................... 90 Multi-master Mode ..................................................... 72 Operation ................................................................... 63 Repeat Start Condition timing .................................... 76 DS30275B-page 190 Restart Condition Flowchart ...................................... 77 Slave Mode ................................................................ 64 Slave Reception ........................................................ 65 Slave Transmission ................................................... 65 SSPBUF .................................................................... 64 Start Condition Flowchart .......................................... 75 Stop Condition Flowchart ........................................... 88 Stop Condition Receive or Transmit timing ............... 87 Stop Condition timing ................................................. 87 Waveforms for 7-bit Reception .................................. 65 Waveforms for 7-bit Transmission ............................. 66 2 I C Module Address Register, SSPADD ........................... 64 2 I C Slave Mode .................................................................. 64 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ......... 145 ID Locations ............................................................. 127, 141 In-Circuit Serial Programming (ICSP) ...................... 127, 141 INDF .................................................................................. 15 INDF Register .............................................................. 13, 14 Indirect Addressing ............................................................ 25 FSR Register ............................................................. 11 Instruction Format ............................................................ 143 Instruction Set .................................................................. 143 Summary Table ....................................................... 144 INTCON ............................................................................. 15 INTCON Register ............................................................... 18 GIE Bit ....................................................................... 18 INTE Bit ..................................................................... 18 INTF Bit ..................................................................... 18 PEIE Bit ..................................................................... 18 RBIE Bit ..................................................................... 18 RBIF Bit ............................................................... 18, 30 T0IE Bit ...................................................................... 18 T0IF Bit ...................................................................... 18 Inter-Integrated Circuit (I2C) .............................................. 53 internal sampling switch (Rss) impedence ...................... 123 Interrupt Sources ..................................................... 127, 137 Block Diagram ......................................................... 137 Capture Complete (CCP) ........................................... 48 Compare Complete (CCP) ......................................... 49 Interrupt on Change (RB7:RB4 ) ............................... 30 RB0/INT Pin, External ...................................... 7, 8, 138 TMR0 Overflow .................................................. 40, 138 TMR1 Overflow .................................................... 41, 43 TMR2 to PR2 Match .................................................. 46 TMR2 to PR2 Match (PWM) ................................ 45, 50 USART Receive/Transmit Complete ......................... 97 Interrupts, Context Saving During .................................... 138 Interrupts, Enable Bits A/D Converter Enable (ADIE Bit) ............................... 19 CCP1 Enable (CCP1IE Bit) ................................. 19, 48 CCP2 Enable (CCP2IE Bit) ....................................... 21 Global Interrupt Enable (GIE Bit) ....................... 18, 137 Interrupt on Change (RB7:RB4) Enable (RBIE Bit) ........................................................... 18, 138 Peripheral Interrupt Enable (PEIE Bit) ....................... 18 PSP Read/Write Enable (PSPIE Bit) ......................... 19 RB0/INT Enable (INTE Bit) ........................................ 18 SSP Enable (SSPIE Bit) ............................................ 19 TMR0 Overflow Enable (T0IE Bit) ............................. 18 TMR1 Overflow Enable (TMR1IE Bit) ........................ 19 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19 USART Receive Enable (RCIE Bit) ........................... 19 USART Transmit Enable (TXIE Bit) ........................... 19 1999-2013 Microchip Technology Inc. 774.book Page 191 Tuesday, January 29, 2013 12:02 PM PIC16C77X Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) ................................... 20 CCP1 Flag (CCP1IF Bit) ................................ 20, 48, 49 CCP2 Flag (CCP2IF Bit) ............................................ 22 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ..................................................... 18, 30, 138 PSP Read/Write Flag (PSPIF Bit) .............................. 20 RB0/INT Flag (INTF Bit) ............................................. 18 SSP Flag (SSPIF Bit) ................................................. 20 TMR0 Overflow Flag (T0IF Bit) .......................... 18, 138 TMR1 Overflow Flag (TMR1IF Bit) ............................ 20 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 20 USART Receive Flag (RCIF Bit) ................................ 20 USART Transmit Flag (TXIE Bit) ............................... 20 K KeeLoq Evaluation and Programming Tools ................. 148 M Master Clear (MCLR) ....................................................... 7, 8 MCLR Reset, Normal Operation .............. 131, 133, 134 MCLR Reset, SLEEP ............................... 131, 133, 134 Memory Organization Data Memory ............................................................. 11 Program Memory ....................................................... 11 MPLAB Integrated Development Environment Software . 147 Multi-Master Communication ............................................. 90 Multi-Master Mode ............................................................. 72 O OPCODE Field Descriptions ............................................ 143 OPTION_REG Register ..................................................... 17 INTEDG Bit ................................................................ 17 PS2:PS0 Bits ....................................................... 17, 39 PSA Bit ................................................................. 17, 39 RBPU Bit .................................................................... 17 T0CS Bit ............................................................... 17, 39 T0SE Bit ............................................................... 17, 39 OSC1/CLKIN Pin ............................................................. 7, 8 OSC2/CLKOUT Pin ......................................................... 7, 8 Oscillator Configuration .................................................... 128 HS .................................................................... 128, 133 LP ..................................................................... 128, 133 RC ............................................................ 128, 130, 133 XT .................................................................... 128, 133 Oscillator, Timer1 ......................................................... 41, 43 Oscillator, WDT ................................................................ 139 P P ......................................................................................... 54 Packaging ........................................................................ 175 Paging, Program Memory ............................................ 11, 24 Parallel Slave Port (PSP) ......................................... 9, 34, 37 Block Diagram ............................................................ 37 RE0/RD/AN5 Pin .............................................. 9, 36, 37 RE1/WR/AN6 Pin ............................................. 9, 36, 37 RE2/CS/AN7 Pin .............................................. 9, 36, 37 Read Waveforms ....................................................... 38 Read/Write Enable (PSPIE Bit) .................................. 19 Read/Write Flag (PSPIF Bit) ...................................... 20 Select (PSPMODE Bit) .................................. 34, 35, 37 Write Waveforms ....................................................... 37 PCL Register ................................................................ 13, 14 PCLATH Register .................................................. 13, 14, 15 1999-2013 Microchip Technology Inc. PCON Register .......................................................... 23, 133 BOR Bit ...................................................................... 23 POR Bit ...................................................................... 23 PICDEM-1 Low-Cost PICmicro Demo Board .................. 146 PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 146 PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 146 PICSTART Plus Entry Level Development System ...... 145 PIE1 Register .................................................................... 19 ADIE Bit ..................................................................... 19 CCP1IE Bit ................................................................ 19 PSPIE Bit ................................................................... 19 RCIE Bit ..................................................................... 19 SSPIE Bit ................................................................... 19 TMR1IE Bit ................................................................ 19 TMR2IE Bit ................................................................ 19 TXIE Bit ..................................................................... 19 PIE2 Register .................................................................... 21 CCP2IE Bit ................................................................ 21 Pinout Descriptions PIC16C63A/PIC16C73B .............................................. 7 PIC16C65B/PIC16C74B .............................................. 8 PIR1 Register .................................................................... 20 ADIF Bit ..................................................................... 20 CCP1IF Bit ................................................................. 20 PSPIF Bit ................................................................... 20 RCIF Bit ..................................................................... 20 SSPIF Bit ................................................................... 20 TMR1IF Bit ................................................................ 20 TMR2IF Bit ................................................................ 20 TXIF Bit ...................................................................... 20 PIR2 Register .................................................................... 22 CCP2IF Bit ................................................................. 22 Pointer, FSR ...................................................................... 25 POR. See Power-on Reset PORTA ...................................................................... 7, 8, 15 Analog Port Pins ...................................................... 7, 8 Initialization ................................................................ 27 PORTA Register ........................................................ 27 RA3:RA0 and RA5 Port Pins ..................................... 28 RA4/T0CKI Pin .................................................. 7, 8, 28 RA5/SS/AN4 Pin .......................................................... 8 TRISA Register .......................................................... 27 PORTA Register ........................................................ 13, 126 PORTB ...................................................................... 7, 8, 15 Initialization ................................................................ 29 PORTB Register ........................................................ 29 Pull-up Enable (RBPU Bit) ......................................... 17 RB0/INT Edge Select (INTEDG Bit) .......................... 17 RB0/INT Pin, External ..................................... 7, 8, 138 RB3:RB0 Port Pins .................................................... 29 RB7:RB4 Interrupt on Change ................................. 138 RB7:RB4 Interrupt on Change Enable (RBIE Bit) .... 18, 138 RB7:RB4 Interrupt on Change Flag (RBIF Bit) ... 18, 30, 138 RB7:RB4 Port Pins .................................................... 30 TRISB Register .......................................................... 29 PORTB Register ........................................................ 13, 126 PORTC ...................................................................... 7, 9, 15 Block Diagram ........................................................... 32 Initialization ................................................................ 32 PORTC Register ........................................................ 32 RC0/T1OSO/T1CKI Pin ........................................... 7, 9 RC1/T1OSI/CCP2 Pin ............................................. 7, 9 RC2/CCP1 Pin ......................................................... 7, 9 RC3/SCK/SCL Pin ................................................... 7, 9 DS30275B-page 191 774.book Page 192 Tuesday, January 29, 2013 12:02 PM PIC16C77X RC4/SDI/SDA Pin .................................................... 7, 9 RC5/SDO Pin ........................................................... 7, 9 RC6/TX/CK Pin .................................................. 7, 9, 98 RC7/RX/DT Pin ............................................ 7, 9, 98, 99 TRISC Register .................................................... 32, 97 PORTC Register ................................................................ 13 PORTD ..................................................................... 9, 15, 37 Block Diagram ............................................................ 34 Parallel Slave Port (PSP) Function ............................ 34 PORTD Register ........................................................ 34 TRISD Register .......................................................... 34 PORTD Register ................................................................ 13 PORTE ........................................................................... 9, 15 Analog Port Pins .............................................. 9, 36, 37 Block Diagram ............................................................ 35 Input Buffer Full Status (IBF Bit) ................................ 35 Input Buffer Overflow (IBOV Bit) ................................ 35 Output Buffer Full Status (OBF Bit) ............................ 35 PORTE Register ........................................................ 35 PSP Mode Select (PSPMODE Bit) ................ 34, 35, 37 RE0/RD/AN5 Pin .............................................. 9, 36, 37 RE1/WR/AN6 Pin ............................................. 9, 36, 37 RE2/CS/AN7 Pin .............................................. 9, 36, 37 TRISE Register .......................................................... 35 PORTE Register ........................................................ 13, 126 Postscaler, Timer2 Select (TOUTPS3:TOUTPS0 Bits) ............................ 45 Postscaler, WDT ................................................................ 39 Assignment (PSA Bit) .......................................... 17, 39 Block Diagram ............................................................ 40 Rate Select (PS2:PS0 Bits) ................................. 17, 39 Switching Between Timer0 and WDT ........................ 40 Power-on Reset (POR) .................... 127, 131, 132, 133, 134 Oscillator Start-up Timer (OST) ....................... 127, 132 POR Status (POR Bit) ................................................ 23 Power Control (PCON) Register .............................. 133 Power-down (PD Bit) ................................................. 16 Power-on Reset Circuit, External ............................. 132 Power-up Timer (PWRT) ................................. 127, 132 Time-out (TO Bit) ....................................................... 16 Time-out Sequence .................................................. 133 Time-out Sequence on Power-up .................... 135, 136 PR2 Register ...................................................................... 14 Prescaler, Capture ............................................................. 48 Prescaler, Timer0 ............................................................... 39 Assignment (PSA Bit) .......................................... 17, 39 Block Diagram ............................................................ 40 Rate Select (PS2:PS0 Bits) ................................. 17, 39 Switching Between Timer0 and WDT ........................ 40 Prescaler, Timer1 ............................................................... 42 Select (T1CKPS1:T1CKPS0 Bits) .............................. 41 Prescaler, Timer2 ............................................................... 50 Select (T2CKPS1:T2CKPS0 Bits) .............................. 45 PRO MATE II Universal Programmer ............................ 145 Product Identification System ........................................... 199 Program Counter PCL Register .............................................................. 24 PCLATH Register .............................................. 24, 138 Reset Conditions ...................................................... 133 Program Memory ............................................................... 11 Interrupt Vector .......................................................... 11 Paging .................................................................. 11, 24 Program Memory Map ............................................... 11 Reset Vector .............................................................. 11 Program Verification ......................................................... 141 Programming Pin (Vpp) .................................................... 7, 8 DS30275B-page 192 Programming, Device Instructions ................................... 143 PWM (CCP Module) .......................................................... 50 Block Diagram ........................................................... 50 CCPR1H:CCPR1L Registers ..................................... 50 Duty Cycle ................................................................. 50 Example Frequencies/Resolutions ............................ 51 Output Diagram ......................................................... 50 Period ........................................................................ 50 Set-Up for PWM Operation ........................................ 51 TMR2 to PR2 Match ............................................ 45, 50 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 20 Q Q-Clock .............................................................................. 50 R R/W .................................................................................... 54 R/W bit ............................................................................... 64 R/W bit ............................................................................... 65 RCE,Receive Enable bit, RCE ........................................... 56 RCREG .............................................................................. 15 RCSTA Register .......................................................... 15, 98 CREN Bit ................................................................... 98 FERR Bit .................................................................... 98 OERR Bit ................................................................... 98 RX9 Bit ...................................................................... 98 RX9D Bit .................................................................... 98 SPEN Bit .............................................................. 97, 98 SREN Bit ................................................................... 98 Read/Write bit, R/W ........................................................... 54 Receive Overflow Indicator bit, SSPOV ............................. 55 Register File ....................................................................... 11 Register File Map ............................................................... 12 Registers FSR Summary ........................................................... 15 INDF Summary ........................................................... 15 INTCON Summary ........................................................... 15 PCL Summary ........................................................... 15 PCLATH Summary ........................................................... 15 PORTB Summary ........................................................... 15 SSPSTAT .................................................................. 54 STATUS Summary ........................................................... 15 Summary ................................................................... 13 TMR0 Summary ........................................................... 15 TRISB Summary ........................................................... 15 Reset ....................................................................... 127, 131 Block Diagram ......................................................... 131 Reset Conditions for All Registers ........................... 134 Reset Conditions for PCON Register ...................... 133 Reset Conditions for Program Counter .................... 133 Reset Conditions for STATUS Register ................... 133 Restart Condition Enabled bit, RSE ................................... 56 Revision History ............................................................... 187 RSE ................................................................................... 56 1999-2013 Microchip Technology Inc. 774.book Page 193 Tuesday, January 29, 2013 12:02 PM PIC16C77X S SAE .................................................................................... 56 SCK .................................................................................... 57 SCL .................................................................................... 64 SDA .................................................................................... 64 SDI ..................................................................................... 57 SDO ................................................................................... 57 SEEVAL Evaluation and Programming System ............ 147 Serial Clock, SCK .............................................................. 57 Serial Clock, SCL ............................................................... 64 Serial Data Address, SDA .................................................. 64 Serial Data In, SDI ............................................................. 57 Serial Data Out, SDO ......................................................... 57 Slave Select Synchronization ............................................ 60 Slave Select, SS ................................................................ 57 SLEEP ............................................................. 127, 131, 140 SMP ................................................................................... 54 Software Simulator (MPLAB-SIM) ................................... 147 SPBRG Register ................................................................ 14 SPE .................................................................................... 56 Special Features of the CPU ........................................... 127 Special Function Registers ................................................ 13 PIC16C73 .................................................................. 13 PIC16C73A ................................................................ 13 PIC16C74 .................................................................. 13 PIC16C74A ................................................................ 13 PIC16C76 .................................................................. 13 PIC16C77 .................................................................. 13 Speed, Operating ................................................................. 1 SPI Master Mode .............................................................. 59 Serial Clock ................................................................ 57 Serial Data In ............................................................. 57 Serial Data Out .......................................................... 57 Serial Peripheral Interface (SPI) ................................ 53 Slave Select ............................................................... 57 SPI clock .................................................................... 59 SPI Mode ................................................................... 57 SPI Clock Edge Select, CKE ............................................. 54 SPI Data Input Sample Phase Select, SMP ...................... 54 SPI Master/Slave Connection ............................................ 58 SPI Module Master/Slave Connection ........................................... 58 Slave Mode ................................................................ 60 Slave Select Synchronization .................................... 60 Slave Synch Timnig ................................................... 60 SS ...................................................................................... 57 SSP .................................................................................... 53 Block Diagram (SPI Mode) ........................................ 57 Enable (SSPIE Bit) ..................................................... 19 Flag (SSPIF Bit) ......................................................... 20 RA5/SS/AN4 Pin .......................................................... 8 RC3/SCK/SCL Pin ................................................... 7, 9 RC4/SDI/SDA Pin .................................................... 7, 9 RC5/SDO Pin ........................................................... 7, 9 SPI Mode ................................................................... 57 SSPADD .................................................................... 64 SSPBUF ............................................................... 59, 64 SSPCON1 .................................................................. 55 SSPCON2 .................................................................. 56 SSPSR ................................................................. 59, 64 SSPSTAT ............................................................. 54, 64 TMR2 Output for Clock Shift ................................ 45, 46 SSP I2C SSP I2C Operation ..................................................... 63 1999-2013 Microchip Technology Inc. SSP Module SPI Master Mode ....................................................... 59 SPI Master./Slave Connection ................................... 58 SPI Slave Mode ......................................................... 60 SSPCON1 Register ................................................... 63 SSP Overflow Detect bit, SSPOV ...................................... 64 SSPADD Register .............................................................. 14 SSPBUF ...................................................................... 15, 64 SSPBUF Register .............................................................. 13 SSPCON Register ............................................................. 13 SSPCON1 ................................................................... 55, 63 SSPCON2 ......................................................................... 56 SSPEN .............................................................................. 55 SSPIF ................................................................................ 65 SSPM3:SSPM0 ................................................................. 55 SSPOV .................................................................. 55, 64, 82 SSPSTAT .................................................................... 54, 64 SSPSTAT Register ............................................................ 14 Stack .................................................................................. 24 Start bit (S) ........................................................................ 54 Start Condition Enabled bit, SAE ....................................... 56 STATUS Register ...................................................... 16, 138 C Bit ........................................................................... 16 DC Bit ........................................................................ 16 IRP Bit ....................................................................... 16 PD Bit ........................................................................ 16 RP1:RP0 Bits ............................................................. 16 TO Bit ........................................................................ 16 Z Bit ........................................................................... 16 Stop bit (P) ......................................................................... 54 Stop Condition Enable bit .................................................. 56 Synchronous Serial Port .................................................... 53 Synchronous Serial Port Enable bit, SSPEN ..................... 55 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 ................................................................. 55 T T1CON .............................................................................. 15 T1CON Register .......................................................... 15, 41 T1CKPS1:T1CKPS0 Bits ........................................... 41 T1OSCEN Bit ............................................................ 41 T1SYNC Bit ............................................................... 41 TMR1CS Bit ............................................................... 41 TMR1ON Bit .............................................................. 41 T2CON Register .......................................................... 15, 45 T2CKPS1:T2CKPS0 Bits ........................................... 45 TMR2ON Bit .............................................................. 45 TOUTPS3:TOUTPS0 Bits ......................................... 45 Timer0 ............................................................................... 39 Block Diagram ........................................................... 39 Clock Source Edge Select (T0SE Bit) ................. 17, 39 Clock Source Select (T0CS Bit) .......................... 17, 39 Overflow Enable (T0IE Bit) ........................................ 18 Overflow Flag (T0IF Bit) .................................... 18, 138 Overflow Interrupt .............................................. 40, 138 RA4/T0CKI Pin, External Clock ............................... 7, 8 Timer1 ............................................................................... 41 Block Diagram ........................................................... 42 Capacitor Selection ................................................... 43 Clock Source Select (TMR1CS Bit) ........................... 41 External Clock Input Sync (T1SYNC Bit) ................... 41 Module On/Off (TMR1ON Bit) ................................... 41 Oscillator .............................................................. 41, 43 Oscillator Enable (T1OSCEN Bit) .............................. 41 Overflow Enable (TMR1IE Bit) .................................. 19 Overflow Flag (TMR1IF Bit) ....................................... 20 DS30275B-page 193 774.book Page 194 Tuesday, January 29, 2013 12:02 PM PIC16C77X Overflow Interrupt ................................................ 41, 43 RC0/T1OSO/T1CKI Pin ........................................... 7, 9 RC1/T1OSI/CCP2 Pin .............................................. 7, 9 Special Event Trigger (CCP) ................................ 43, 49 T1CON Register ........................................................ 41 TMR1H Register ........................................................ 41 TMR1L Register ......................................................... 41 Timer2 Block Diagram ............................................................ 46 PR2 Register ........................................................ 45, 50 SSP Clock Shift .................................................... 45, 46 T2CON Register ........................................................ 45 TMR2 Register ........................................................... 45 TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19 TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 20 TMR2 to PR2 Match Interrupt ........................ 45, 46, 50 Timing Diagrams Acknowledge Sequence Timing ................................. 85 Baud Rate Generator with Clock Arbitration .............. 73 BRG Reset Due to SDA Collision .............................. 92 Brown-out Reset ...................................................... 163 Bus Collision Start Condition Timing ....................................... 91 Bus Collision During a Restart Condition (Case 1) .... 93 Bus Collision During a Restart Condition (Case2) ..... 93 Bus Collision During a Start Condition (SCL = 0) ...... 92 Bus Collision During a Stop Condition ....................... 94 Bus Collision for Transmit and Acknowledge ............. 90 Capture/Compare/PWM ........................................... 169 CLKOUT and I/O ...................................................... 162 External Clock Timing .............................................. 161 I2C Master Mode First Start bit timing ........................ 74 I2C Master Mode Reception timing ............................ 84 I2C Master Mode Transmission timing ....................... 81 Master Mode Transmit Clock Arbitration .................... 89 Power-up Timer ....................................................... 163 Repeat Start Condition ............................................... 76 Reset ........................................................................ 163 Slave Synchronization ............................................... 60 Start-up Timer .......................................................... 163 Stop Condition Receive or Transmit .......................... 87 Time-out Sequence on Power-up .................... 135, 136 Timer0 ...................................................................... 168 Timer1 ...................................................................... 168 USART Asynchronous Master Transmission ........... 103 USART Synchronous Receive ................................. 171 USART Synchronous Reception .............................. 109 USART Synchronous Transmission ................ 108, 171 USART, Asynchronous Reception ........................... 105 Wake-up from SLEEP via Interrupt .......................... 141 Watchdog Timer ....................................................... 163 TMR0 ................................................................................. 15 TMR0 Register ................................................................... 13 TMR1H ............................................................................... 15 TMR1H Register ................................................................ 13 TMR1L ............................................................................... 15 TMR1L Register ................................................................. 13 TMR2 ................................................................................. 15 TMR2 Register ................................................................... 13 TRISA Register .......................................................... 14, 126 TRISB Register .......................................................... 14, 126 TRISC Register .................................................................. 14 TRISD Register .................................................................. 14 TRISE Register .................................................... 14, 35, 126 IBF Bit ........................................................................ 35 IBOV Bit ..................................................................... 35 OBF Bit ...................................................................... 35 DS30275B-page 194 PSPMODE Bit ................................................ 34, 35, 37 TXREG .............................................................................. 15 TXSTA Register ................................................................. 97 BRGH Bit ............................................................. 97, 99 CSRC Bit ................................................................... 97 SYNC Bit ................................................................... 97 TRMT Bit .................................................................... 97 TX9 Bit ....................................................................... 97 TX9D Bit .................................................................... 97 TXEN Bit .................................................................... 97 U UA ...................................................................................... 54 Universal Synchronous Asynchronous Receiver Transmitter (USART) Asynchronous Receiver Setting Up Reception ....................................... 104 Timing Diagram ............................................... 105 Update Address, UA .......................................................... 54 USART ............................................................................... 97 Asynchronous Mode ................................................ 102 Master Transmission ....................................... 103 Receive Block Diagram ................................... 105 Transmit Block Diagram .................................. 102 Baud Rate Generator (BRG) ..................................... 99 Baud Rate Error, Calculating ............................. 99 Baud Rate Formula ........................................... 99 Baud Rates, Asynchronous Mode (BRGH=0) . 100 Baud Rates, Asynchronous Mode (BRGH=1) . 101 Baud Rates, Synchronous Mode ..................... 100 High Baud Rate Select (BRGH Bit) ............. 97, 99 Sampling ............................................................ 99 Clock Source Select (CSRC Bit) ................................ 97 Continuous Receive Enable (CREN Bit) .................... 98 Framing Error (FERR Bit) .......................................... 98 Mode Select (SYNC Bit) ............................................ 97 Overrun Error (OERR Bit) .......................................... 98 RC6/TX/CK Pin ........................................................ 7, 9 RC7/RX/DT Pin ........................................................ 7, 9 RCSTA Register ........................................................ 98 Receive Data, 9th bit (RX9D Bit) ............................... 98 Receive Enable (RCIE Bit) ........................................ 19 Receive Enable, 9-bit (RX9 Bit) ................................. 98 Receive Flag (RCIF Bit) ............................................. 20 Serial Port Enable (SPEN Bit) ............................. 97, 98 Single Receive Enable (SREN Bit) ............................ 98 Synchronous Master Mode ...................................... 107 Reception ........................................................ 109 Transmission ................................................... 108 Synchronous Slave Mode ........................................ 110 Transmit Data, 9th Bit (TX9D) ................................... 97 Transmit Enable (TXEN Bit) ...................................... 97 Transmit Enable (TXIE Bit) ........................................ 19 Transmit Enable, Nine-bit (TX9 Bit) ........................... 97 Transmit Flag (TXIE Bit) ............................................ 20 Transmit Shift Register Status (TRMT Bit) ................ 97 TXSTA Register ......................................................... 97 1999-2013 Microchip Technology Inc. 774.book Page 195 Tuesday, January 29, 2013 12:02 PM PIC16C77X W W Register ....................................................................... 138 Wake-up from SLEEP .............................................. 127, 140 Interrupts .......................................................... 133, 134 MCLR Reset ............................................................ 134 Timing Diagram ........................................................ 141 WDT Reset .............................................................. 134 Watchdog Timer (WDT) ........................................... 127, 139 Block Diagram .......................................................... 139 Enable (WDTE Bit) ................................................... 139 Programming Considerations .................................. 139 RC Oscillator ............................................................ 139 Time-out Period ....................................................... 139 WDT Reset, Normal Operation ................ 131, 133, 134 WDT Reset, SLEEP ......................................... 133, 134 Waveform for General Call Address Sequence ................. 69 WCOL .................................................. 55, 74, 79, 82, 85, 87 WCOL Status Flag ............................................................. 74 Write Collision Detect bit, WCOL ....................................... 55 WWW, On-Line Support ...................................................... 4 1999-2013 Microchip Technology Inc. DS30275B-page 195 774.book Page 196 Tuesday, January 29, 2013 12:02 PM PIC16C77X BIT/REGISTER CROSS-REFERENCE LIST ADCS1:ADCS0 ..................................ADCON0<7:6> ADIE ...................................................PIE1<6> ADIF ...................................................PIR1<6> ADON .................................................ADCON0<0> BF .......................................................SSPSTAT<0> BOR ...................................................PCON<0> BRGH .................................................TXSTA<2> C .........................................................STATUS<0> CCP1IE ..............................................PIE1<2> CCP1IF ..............................................PIR1<2> CCP1M3:CCP1M0 .............................CCP1CON<3:0> CCP1X:CCP1Y ..................................CCP1CON<5:4> CCP2IE ..............................................PIE2<0> CCP2IF ..............................................PIR2<0> CCP2M3:CCP2M0 .............................CCP2CON<3:0> CCP2X:CCP2Y ..................................CCP2CON<5:4> CHS2:CHS0 .......................................ADCON0<5:3> CKE ....................................................SSPSTAT<6> CKP ....................................................SSPCON<4> CREN .................................................RCSTA<4> CSRC .................................................TXSTA<7> D/A .....................................................SSPSTAT<5> DC ......................................................STATUS<1> FERR .................................................RCSTA<2> GIE .....................................................INTCON<7> GO/DONE ..........................................ADCON0<2> IBF ......................................................TRISE<7> IBOV ...................................................TRISE<5> INTE ...................................................INTCON<4> INTEDG ..............................................OPTION_REG<6> INTF ...................................................INTCON<1> IRP .....................................................STATUS<7> OBF ....................................................TRISE<6> OERR .................................................RCSTA<1> P .........................................................SSPSTAT<4> PCFG2:PCFG0 ..................................ADCON1<2:0> PD ......................................................STATUS<3> PEIE ...................................................INTCON<6> POR ...................................................PCON<1> PS2:PS0 .............................................OPTION_REG<2:0> PSA ....................................................OPTION_REG<3> PSPIE .................................................PIE1<7> PSPIF .................................................PIR1<7> PSPMODE .........................................TRISE<4> R/W ....................................................SSPSTAT<2> RBIE ...................................................INTCON<3> RBIF ...................................................INTCON<0> RBPU .................................................OPTION_REG<7> RCIE ...................................................PIE1<5> RCIF ...................................................PIR1<5> RP1:RP0 ............................................STATUS<6:5> RX9 ....................................................RCSTA<6> RX9D ..................................................RCSTA<0> S .........................................................SSPSTAT<3> SMP ...................................................SSPSTAT<7> SPEN .................................................RCSTA<7> SREN .................................................RCSTA<5> SSPEN ...............................................SSPCON<5> SSPIE .................................................PIE1<3> SSPIF .................................................PIR1<3> SSPM3:SSPM0 ..................................SSPCON<3:0> SSPOV ...............................................SSPCON<6> SYNC .................................................TXSTA<4> DS30275B-page 196 T0CS .................................................. OPTION_REG<5> T0IE ................................................... INTCON<5> T0IF ................................................... INTCON<2> T0SE .................................................. OPTION_REG<4> T1CKPS1:T1CKPS0 .......................... T1CON<5:4> T1OSCEN .......................................... T1CON<3> T1SYNC ............................................. T1CON<2> T2CKPS1:T2CKPS0 .......................... T2CON<1:0> TMR1CS ............................................ T1CON<1> TMR1IE .............................................. PIE1<0> TMR1IF .............................................. PIR1<0> TMR1ON ............................................ T1CON<0> TMR2IE .............................................. PIE1<1> TMR2IF .............................................. PIR1<1> TMR2ON ............................................ T2CON<2> TO ...................................................... STATUS<4> TOUTPS3:TOUTPS0 ......................... T2CON<6:3> TRMT ................................................. TXSTA<1> TX9 .................................................... TXSTA<6> TX9D .................................................. TXSTA<0> TXEN ................................................. TXSTA<5> TXIE ................................................... PIE1<4> TXIF ................................................... PIR1<4> UA ...................................................... SSPSTAT<1> WCOL ................................................ SSPCON<7> Z ......................................................... STATUS<2> 1999-2013 Microchip Technology Inc. 774.book Page 197 Tuesday, January 29, 2013 12:02 PM PIC16C77X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 1999-2013 Microchip Technology Inc. DS30275B-page 197 774.book Page 198 Tuesday, January 29, 2013 12:02 PM PIC16C77X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C77X Y N Literature Number: DS30275B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30275B-page 198 1999-2013 Microchip Technology Inc. 774.book Page 199 Tuesday, January 29, 2013 12:02 PM PIC16C77X PIC16C77X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X -XX Frequency Temperature Range Range /XX XXX Package Pattern Examples: g) h) Device PIC16C77X(1), PIC16C77XT(2);VDD range 4.0V to 5.5V PIC16LC77X(1), PIC16LC77XT(2);VDD range 2.5V to 5.5V Frequency Range 04 20 i) PIC16C774 -04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. PIC16LC773 - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. PIC16C774 - 20I/P = Industrial temp., PDIP package, 20MHz, normal VDD limits. = 4 MHz = 20 MHz Note 1: (3) = 0C to = -40C to 70C +85C (Commercial) (Industrial) Temperature Range b I Package JW PQ PT SO SP P L SS Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) 2: = = = = = = = = C = CMOS LC = Low Power CMOS T = in tape and reel - SOIC, SSOP, PLCC, MQFP, TQFP packages only. b = blank Windowed CERDIP/Ceramic MQFP (Metric PQFP) TQFP (Thin Quad Flatpack) SOIC Skinny plastic dip PDIP PLCC SSOP * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1999-2013 Microchip Technology Inc. Advance Information DS30275B-page 199 774.book Page 200 Tuesday, January 29, 2013 12:02 PM PIC16C77X DS30275B-page 200 Advance Information 1999-2013 Microchip Technology Inc. 774.book Page 201 Tuesday, January 29, 2013 12:02 PM Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1999-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769263 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 1999-2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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