TI SN74ABT273DBR

SN54ABT273, SN74ABT273
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997
D
D
D
D
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Plastic (N) and Ceramic (J) DIPs, and
Ceramic Flat (W) Package
SN54ABT273 . . . J OR W PACKAGE
SN74ABT273 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
description
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ABT273 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
CLR
VCC
The ’ABT273 are 8-bit positive-edge-triggered
D-type flip-flops with a direct clear (CLR) input.
They are particularly suitable for implementing
buffer and storage registers, shift registers, and
pattern generators.
2D
2Q
3Q
3D
4D
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
4Q
GND
CLK
5Q
5D
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
the clock (CLK) input is at either the high or low
level, the D input signal has no effect at the output.
8Q
D
The SN54ABT273 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT273 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
H or L
X
Q0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT273, SN74ABT273
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997
logic symbol†
CLR
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
R
11
C1
3
2
1D
4
5
7
6
8
9
13
12
14
15
17
16
18
19
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
2D
1D
CLK
11
3
3D
4
7
5D
8
6D
13
7D
14
8D
17
18
CLK(I)
1D
1D
C1
1
1D
C1
R
CLR
4D
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
R
2
1Q
5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT273, SN74ABT273
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997
recommended operating conditions (see Note 3)
SN54ABT273
SN74ABT273
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
VCC
–24
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
85
°C
High-level input voltage
2
2
0.8
Input voltage
0
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
–55
125
V
0.8
0
–40
V
VCC
–32
V
V
mA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
Vhys
II
Ioff
ICEX
IO‡
VCC = 4
4.5
5V
MIN
TA = 25°C
TYP†
MAX
SN54ABT273
MIN
–1.2
MAX
SN74ABT273
MIN
–1.2
MAX
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOL = 64 mA
V
0.55
0.55*
0.55
100
VI = VCC or GND
VI or VO ≤ 4.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VO = 5.5 V
VO = 2.5 V
±1
∆ICC¶
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
±1
µA
µA
50
–200§
µA
–100
Outputs high
1
400§
400§
400§
µA
Outputs low
24
30
30
30
mA
1.5
1.5
1.5
mA
–50
50
–200§
±1
±100
50
–200§
–50
VCC = 5.5 V,, IO = 0,,
VI = VCC or GND
V
mV
±100
Outputs high
ICC
V
2
0.55
VCC = 5.5 V,
VCC = 0,
UNIT
–50
Ci
VI = 2.5 V or 0.5 V
7
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§ This data sheet limit may vary among suppliers.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mA
pF
3
SN54ABT273, SN74ABT273
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
fclock
Clock frequency
tw
Pulse duration
Setup time before CLK↑
↑
th
Hold time after CLK↑
† This data sheet limit may vary among suppliers.
SN74ABT273
MIN
MAX
MIN
MAX
MIN
MAX
0
150
0
150
0
150
UNIT
MHz
CLK high or low
3.3
3.3
3.3
CLR low
3.3
3.3
3.3
2
2
2
Data low
2.5
2.5
2.5
ns
CLR high
2
1.2†
2
1.4†
2
1.2†
ns
Data high
tsu
SN54ABT273
Data high or low
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
FROM
(INPUT)
TO
(OUTPUT)
MIN
SN54ABT273
MAX
150
CLK
Q
CLR
† This data sheet limit may vary among suppliers.
Q
tPHL
tPHL
VCC = 5 V,
TA = 25°C
MIN
150
MHz
2.5
6
2.5
7
3.3
6.8
7.5†
3.3
7.5
2.5
8.2
2.5
UNIT
MAX
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
FROM
(INPUT)
TO
(OUTPUT)
Q
CLR
† This data sheet limit may vary among suppliers.
Q
4
MIN
SN74ABT273
MAX
150
CLK
tPHL
tPHL
VCC = 5 V,
TA = 25°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
150
MHz
2.5
6
2.5
6.5
3.3
6.8
6.7†
3.3
7.3
7.4†
2.5
2.5
UNIT
MAX
ns
ns
SN54ABT273, SN74ABT273
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR
SCBS185B – FEBRUARY 1991 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
Data Input
0V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
3V
1.5 V
Input
Output
Control
1.5 V
0V
1.5 V
1.5 V
VOL
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
VOH
Output
1.5 V
tPZL
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2007
PACKAGING INFORMATION
(1)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-9321701Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9321701QRA
ACTIVE
CDIP
J
20
1
TBD
1
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
Call TI
N / A for Pkg Type
TBD
A42
N / A for Pkg Type
TBD
Call TI
5962-9321701QSA
ACTIVE
CFP
W
20
SN74ABT273DBLE
OBSOLETE
SSOP
DB
20
SN74ABT273DBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273DBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273DW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273DWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273DWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273DWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ABT273NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ABT273NSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273NSRE4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273NSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273PWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273PWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273PWLE
OBSOLETE
TSSOP
PW
20
SN74ABT273PWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273PWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT273PWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54ABT273FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54ABT273J
ACTIVE
CDIP
J
20
1
TBD
Call TI
N / A for Pkg Type
SNJ54ABT273W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
TBD
The marketing status values are defined as follows:
Addendum-Page 1
Call TI
Call TI
Call TI
POST-PLATE N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
16-Jul-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74ABT273DBR
DB
20
MLA
330
16
8.2
7.5
2.5
12
16
Q1
SN74ABT273DWR
DW
20
MLA
330
24
10.8
13.0
2.7
12
24
Q1
SN74ABT273NSR
NS
20
MLA
330
24
8.2
13.0
2.5
12
24
Q1
SN74ABT273PWR
PW
20
MLA
330
16
6.95
7.1
1.6
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74ABT273DBR
DB
20
MLA
346.0
346.0
33.0
SN74ABT273DWR
DW
20
MLA
333.2
333.2
31.75
SN74ABT273NSR
NS
20
MLA
333.2
333.2
31.75
SN74ABT273PWR
PW
20
MLA
346.0
346.0
33.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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