ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 12-Bit, 40-kSPS, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER with Internal Reference and Serial Interface FEATURES APPLICATIONS • 40-kHz Minimum Sampling Rate • Very Low Power: 25 mW • ±3.33-V, ±5-V, ±10-V, 4-V, and 10-V Input Ranges • 73.9-dB SINAD with 10-kHz Input • ±0.5 LSB Max INL • ±0.5 LSB Max DNL, 12-Bit NMC • ±5-mV BPZ, ±2 ppm/°C BPZ Drift • 72-dB Min SINAD, 80-dB Min SFDR • Uses Internal or External 2.5-V Reference • No External Calibration Resistors Required • Single 5-V Analog Supply: – 32.5-mW Max Power Dissipation – 50-µW Max Power-Down Mode • SPI™-Compatible Serial Port up to 20MHz, with Master/Slave Feature • Global CONV and 3-Stated Bus for Multi-Chip Simultaneous S/H Operation • Pin-Compatible with ADS7812 and 16-Bit ADS7813/8513 • SO-16 Package • • • • • • 1 234 Industrial Process Control Test Equipment Robotics DSP Servo Control Medical Instrumentation Portable Data Acquisition Systems DESCRIPTION The ADS8512 is a complete low-power, single 5-V supply, 12-bit sampling analog-to-digital (A/D) converter. It contains a complete 12-bit capacitor-based, successive approximation register (SAR) A/D converter with sample-and-hold (S/H), clock, reference, and serial data interface. The converter can be configured for a variety of input ranges including ±10 V, ±5 V, 0 V to 10 V, and 0.5 V to 4.5 V. A high-impedance, 0.3-V to 2.8-V input is also available with input impedance greater than 10 MΩ. For most input ranges, the input voltage can swing to 25 V or –25 V without damage to the converter. An SPI-compatible serial interface allows data to be synchronized to an internal or external clock. The ADS8512 is specified at 40-kHz sampling rate over the –40°C to +85°C industrial temperature range. Successive Approximation Register Clock EXT/INT CDAC 40 kW R1IN 8 kW R2IN 20 kW R3IN Comparator Serial Data Out and Control PWRD BUSY CS CONV SDATA DATACLK BUF CAP Buffer 4 kW REF Internal +2.5 V Ref 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320 is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM INL (LSB) NO MISSING CODES MINIMUM SINAD (dB) SPECIFIED TEMPERATURE RANGE PACKAGELEAD PACKAGE DESIGNATOR ADS8512IB ±0.5 12 72 -40°C to +85°C SO-16 DW ADS8512I ±1 12 70 -40°C to +85°C SO-16 DW (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS8512IBDW Tube, 20 ADS8512IBDWR Tape and Reel, 1000 ADS8512IDW Tube, 20 ADS8512IDWR Tape and Reel, 1000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) (2) Over operating free-air temperature range (unless otherwise noted). PARAMETER Analog inputs Ground voltage differences UNIT R1IN ±25 V R2IN ±25 V R3IN ±25 V REF VS + 0.3 V to GND – 0.3 V GND ±0.3 V VS 6V Digital inputs –0.3 V to VS + 0.3 V Maximum junction temperature +165°C Storage temperature range –65°C to +150°C Internal power dissipation 700 mW Lead temperature (soldering, 1,6 mm from case, 10 seconds) +260°C (1) (2) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. ELECTRICAL CHARACTERISTICS At TA = -40°C to +85°C, fS = 40 kHz, VS = 5 V, and using internal reference and fixed resistors, unless otherwise specified. ADS8512I PARAMETER TEST CONDITIONS MIN TYP Resolution ADS8512IB MAX MIN TYP 12 MAX 12 UNIT Bits ANALOG INPUT Voltage ranges See Table 1 See Table 1 V Impedance See Table 1 See Table 1 kΩ Capacitance 45 45 pF THROUGHPUT SPEED Conversion time Complete cycle Throughput rate 2 Acquire and convert 40 Submit Documentation Feedback 20 20 25 25 40 µs µs kHz Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to +85°C, fS = 40 kHz, VS = 5 V, and using internal reference and fixed resistors, unless otherwise specified. ADS8512I PARAMETER TEST CONDITIONS ADS8512IB MIN TYP MAX MIN TYP MAX UNIT DC ACCURACY INL Integral linearity error –1 ±0.1 1 –0.5 ±0.1 0.5 LSB (1) DNL Differential linearity error –1 ±0.1 1 –0.5 ±0.1 0.5 LSB No missing codes 12 Transition noise (2) 12 0.05 Gain error ±0.2 Full scale error (3) (4) -0.5 Full scale error drift External 2.5-V reference Full scale error drift External 2.5-V reference Bipolar zero error (3) Bipolar ranges Bipolar zero error drift Bipolar ranges Unipolar zero error (3) Unipolar ranges Unipolar zero error drift Unipolar ranges Recovery time to rated accuracy from power down (5) 1-µF capacitor to CAP Power-supply sensitivity +4.75 V < VS < +5.25 V –0.5 –0.25 0.5 –0.25 10 0.25 –5 5 –6 % ppm/°C ±2 6 % ppm/°C ±0.5 ±2 –6 % 0.25 ±10 ±0.5 –10 LSB ±0.1 0.5 ±10 Full scale error (3) (4) Bits 0.05 mV ppm/°C 6 mV ±3 ±3 ppm/°C 300 300 µs ±0.75 ±0.75 LSB AC ACCURACY SFDR Spurious-free dynamic range fIN = 1 kHz, ±10 V THD Total harmonic distortion fIN = 1 kHz, ±10 V SINAD Signal-to-(noise+distortion) SNR Signal-to-noise fIN = 1 kHz, ±10 V 80 70 –60 dB input 80 –80 74 72 30 70 dB (6) 98 –98 –80 74 dB 32 dB 130 130 kHz 600 600 kHz Aperture delay 40 40 ns Aperture jitter 20 20 (7) Full-power bandwidth (–3 dB) 74 72 dB 74 Usable bandwidth fIN = 1 kHz, ±10 V 98 –96 SAMPLING DYNAMICS Transient response FS step 5 Overvoltage recovery (8) ps 5 750 750 µs ns REFERENCE Internal reference voltage No load 2.48 (6) (7) (8) 2.48 2.5 2.52 V 1 µA Internal reference drift 8 8 ppm/°C External reference current drain (5) 2.52 1 External reference voltage range for specified linearity (1) (2) (3) (4) 2.5 Internal reference source current (must use external buffer) 2.3 External 2.5-V reference 2.5 2.7 100 2.3 2.5 2.7 V 100 µA LSB means least significant bit. 1 LSB for the ±10 V input range is 305 µV. Typical rms noise at worst-case transitions. As measured with fixed resistors. Adjustable to zero with external potentiometer. Full-scale error is the worst case of –Full Scale or +Full Scale deviation from ideal first and last code transitions, divided by the full-scale range; includes the effect of offset error. Tested at –40°C to +85°C. Time delay after the ADS8512 is brought out of Power-Down mode until all internal settling occurs and the analog input is acquired to rated accuracy. A Convert command after this delay yields accurate results. All specifications in dB are referred to a full-scale input. Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB. Recovers to specified performance after 2 x FS input overvoltage. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 3 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to +85°C, fS = 40 kHz, VS = 5 V, and using internal reference and fixed resistors, unless otherwise specified. ADS8512I PARAMETER TEST CONDITIONS MIN TYP ADS8512IB MAX MIN –0.3 +0.8 2.0 VS + 0.3 TYP MAX UNIT –0.3 +0.8 V 2.0 DIGITAL INPUTS VIL Low-level input voltage VIH High-level input voltage VS + 0.3 V IIL Low-level input current VIL = 0 V ±10 ±10 µA IIH High-level input current VIH = 5 V ±10 ±10 µA 0.4 V DIGITAL OUTPUTS Data format - Serial Data coding - binary 2s complement VOL Low-level output voltage ISINK = 1.6 mA VOH High-level output voltage ISOURCE = 500 µA 0.4 Leakage current High-Z state, VOUT = 0 V to VS ±1 ±1 µA Output capacitance High-Z state 15 15 pF Bus access time RL = 3.3 kΩ, CL = 50 pF 83 83 ns Bus relinquish time RL = 3.3 kΩ, CL = 10 pF 83 83 ns 4 4 V DIGITAL TIMING POWER SUPPLIES VS Analog voltage IDIG Digital current IANA Analog current 4.75 5 5.25 4.75 0.6 4.2 Power dissipation VS = 5 V, fS = 40 kHz 24 PWRD 50 5 5.25 0.6 4.2 32.5 24 V mA mA 32.5 mW µW 50 TEMPERATURE RANGE θJA Specified performance –40 +85 –40 +85 °C Derated performance –55 +125 –55 +125 °C Storage temperature –65 +150 –65 +150 Thermal resistance SO-16 46 46 °C °C/W Table 1. Input Ranges ANALOG INPUT RANGE CONNECT R1IN TO CONNECT R2IN TO CONNECT R3IN TO 4 INPUT IMPEDANCE (kΩ) ±10 V VIN BUF GND 45.7 0.3125V to 2.8125 V VIN VIN VIN > 10,000 ±5 V GND BUF VIN 26.7 0 V to 10 V BUF GND VIN 26.7 0 V to 4 V BUF VIN GND 21.3 ±3.33 V VIN BUF VIN 21.3 0.5 V to 4.5 V GND VIN GND 21.3 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 PIN CONFIGURATION DW PACKAGE SO-16 (TOP VIEW) R1IN 1 16 VS GND 2 15 PWRD R2IN 3 14 BUSY R3IN 4 13 CS BUF 12 CONV 5 CAP 6 11 EXT/INT REF 10 DATA 7 GND 8 9 DATACLK Terminal Functions TERMINAL DIGITAL I/O NAME NO. R1IN 1 Analog input. See Table 1 and Table 3. DESCRIPTION R2IN 3 Analog input. See Table 1 and Table 3. R3IN 4 Analog input. See Table 1 and Table 3. BUF 5 Reference buffer output. Connect to R1IN, R2IN, or R3IN as needed. CAP 6 Reference buffer compensation node. Decouple to ground with a 1-µF tantalum capacitor in parallel with a 0.01-µF ceramic capacitor. REF 7 Reference input/output. Outputs internal 2.5-V reference via a series 4-kΩ resisitor. Decouple this voltage with a 1-µF to 2.2-µF tantalum capacitor to ground. If an external reference voltage is applied to this pin, it overrides the internal reference. DATACLK 9 I/O Data clock pin. With EXT/INT low, this pin is an output and provides the synchrnous clock for the serial data. The output is 3-stated when CS is high. With EXT/INT high, this pin is an input and the serial data clock must be provided externally. DATA 10 O Serial data output. The serial data are always the result of the last completed conversion and are synchronized to DATACLK. If DATACLK is from the internal clock (EXT/INT low), the serial data are valid on both the rising and falling edges of DATACLK. DATA is 3-stated when CS is high. I External/Internal DATACLK pin. Selects the source of the synchronous clock for serial data. if high, the clock must be provided externally. If low, the clock is derived from the internal conversion clock. Note that the clock used to time the conversion is always interna,l regardless of the status of EXT/INT. EXT/INT 11 CONV 12 CS 13 I Chip select. This input 3-states all outputs when high, and enables all outputs when low, including DATA, BUSY, and DATACLK (when EXT/INT is low). Note that a falling edge on CONV will initiate a conversion even when CS is high. BUSY 14 O Busy output. When a conversion starts, BUSY goes low and remains low throughout the conversion. If EXT/INT is low, data are serially transmitted while BUSY is low. BUSY is 3-stated when CS is high. I Power down input. When high, the majority of the ADS8512 is placed in a low-power mode, and power consumption is significantly reduced. CONV must be taken low before PWRD goes in order to achieve the lowest power consumption. The time required for the ADS8512 to return to normal operation after power down depends on a number of factors. Consult the Power-Down section for more information. Convert input. A falling edge on this input puts the internal sample/hold into the hold state and starts a conversion regardless of the state of CS. If a conversion is already in progress, the falling edge is ignored. If EXT/INT is low, data from the previous conversion will be serially transmitted during the current conversion. PWRD 15 GND 2, 8 Ground. VS 16 +5-V supply input. For best performance, decouple to ground with a 0.1-µF ceramic capacitor in parallel with a 10-µF tantalum capacitor. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 5 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS POWER-SUPPLY CURRENT vs FREE-AIR TEMPERATURE HISTOGRAM 6 0 2.52 Vref - Internal Reference Voltage - V 16384 Power Supply Current - mA Bipolar Range, VIN = 0 V in ±10 V INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 5.5 5 4.5 2.51 2.5 2.49 0 FFF 000 4 -45 -25 001 -5 15 35 55 75 95 2.48 -45 -25 115 TA - Free Air Temperature - °C 115 Figure 1. Figure 2. Figure 3. POWER-SUPPLY CURRENT vs SAMPLING FREQUENCY BIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE BIPOLAR POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 6 9 0.5 5.5 5 4.5 0.4 6 -10 V to 10 V 0.3 Bipolar Error - %FSR Bipolar Offset Error - mV -10 V to 10 V Power-Supply Current - mA -5 15 35 55 75 95 TA - Free Air Temperature - °C 3 0 -3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 4 10 20 30 fS - Sampling Frequency - kHz -6 -45 40 -0.5 -45 -25 115 -5 15 35 55 75 95 TA - Free Air Temperature - °C 115 Figure 5. Figure 6. BIPOLAR NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE BIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE BIPOLAR POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 5 -10 V to 10 V 4 0.2 -5 V to 5 V -5 V to 5 V 0.15 Bipolar Offset Error - mV 0.3 0.2 0.1 0 -0.1 -0.2 3 2 1 0 -1 -2 -3 -0.4 -4 -5 15 35 55 75 95 TA - Free Air Temperature - °C 115 Figure 7. 0.1 0.05 0 -0.05 -0.1 -0.3 -0.5 -45 -25 Bipolar Error - %FSR 0.4 Bipolar Error - %FSR -5 15 35 55 75 95 TA - Free Air Temperature - °C Figure 4. 0.5 6 -25 -5 -45 -25 -0.15 -5 15 35 55 75 95 TA - Free Air Temperature - °C 115 Figure 8. Submit Documentation Feedback -0.2 -45 -25 -5 15 35 55 75 95 115 TA - Free Air Temperature - °C Figure 9. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 TYPICAL CHARACTERISTICS (continued) BIPOLAR NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE UNIPOLAR POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE UNIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE 0.2 2 -5 V to 5 V 0.15 1.5 0.4 0 V to 4 V 0 V to 4 V Bipolar Error - %FSR 0.1 0.05 0 -0.05 1 Unipolar Error - %FSR Unipolar Offset Error - mV 0.3 0.5 0 -0.5 -0.1 -1 0.2 0.1 0 -0.1 -0.15 -1.5 -0.2 -45 -25 -5 15 35 55 75 95 TA - Free Air Temperature - °C -2 -45 -25 115 15 35 55 75 95 -25 -5 15 35 55 75 95 115 TA - Free Air Temperature - °C Figure 10. Figure 11. Figure 12. UNIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE UNIPOLAR POSITIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 0.5 100 SFDR - Spurious Free Dynamic Range - dB 0.4 0 V to 10 V 0 V to 10 V 0.3 Unipolar Error - %FSR 6 3 0 -3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -6 -45 -25 -5 15 35 55 75 95 TA - Free Air Temperature - °C -0.5 -45 115 -25 -5 15 35 55 75 95 TA - Free Air Temperature - °C 115 99 98 97 96 95 94 93 92 91 90 -45 -25 -5 15 35 55 75 95 115 TA - Free Air Temperature - °C Figure 13. Figure 14. Figure 15. TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE 75 -91 74.5 -92 -93 -94 -95 -96 -97 -98 74 73.5 73 72.5 72 71.5 71 70.5 -99 -100 -45 -25 75 SINAD - Signal-to-Noise + Distortion - dB -90 SNR - Signal to Noise Ratio - dB THD - Total Harmonic Distortion - dB -0.2 -45 115 TA - Free Air Temperature - °C 9 Unipolar Offset Error - mV -5 -5 15 35 55 75 95 115 TA - Free Air Temperature - °C Figure 16. 70 -45 -25 -5 15 35 55 75 95 TA - Free Air Temperature - °C Figure 17. 115 74.5 74 73.5 73 72.5 72 71.5 71 70.5 70 -45 -25 -5 15 35 55 75 95 Figure 18. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 115 TA - Free Air Temperature - °C 7 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs FREE-AIR TEMPERATURE 75 90 80 0 dB 70 60 -20 dB 50 40 30 20 -60 dB 10 0 0 2 4 6 8 10 12 14 16 18 20 80 Fs = 10 KHz 74 73 Fs = 30 KHz Fs = 40 KHz 72 71 78 70 -45 -25 76 74 72 70 68 66 64 62 Input Frequency: 10 KHz, 0 dB 60 -5 15 35 55 75 95 115 1 Figure 20. Figure 21. SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY SPURIOUS FREE DYNAMIC RANGE vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 74 72 70 68 66 64 62 60 1 10 100 fi - Frequency - kHz THD - Total Harmonic Distortion - dB 76 -60 100 SFDR - Spurious Free Dynamic Range - dB 78 95 90 85 80 75 70 65 60 -70 -75 -80 -85 -90 -95 -100 1 1000 -65 10 100 fi - Frequency - kHz 1000 1 10 100 fi - Frequency - kHz Figure 22. Figure 23. Figure 24. SPURIOUS FREE DYNAMIC RANGE vs ESR TOTAL HARMONIC DISTORTION vs ESR SIGNAL-TO-NOISE RATIO vs ESR 75 -91 74.5 98 97 96 95 94 93 92 91 1 2 3 4 5 6 7 8 Reference Capacitor ESR - W 9 10 Figure 25. SNR - Signal to Noise Ratio - dB -90 99 THD - Total Harmonic Distortion - dB 100 90 0 1000 Figure 19. 80 SFDR - Spurious Free Dynamic Range - dB 10 100 fi - Input Frequency - kHz TA - Free Air Temperature - °C fi - Frequency - kHz SINAD - Signal-to-Noise + Distortion - dB Fs = 20 KHz SNR - Signal to Noise Ratio - dB SINAD - Signal-to-Noise + Distortion - dB SINAD - Signal-to-Noise + Distortion - dB 100 8 SIGNAL-TO-NOISE RATIO vs FREQUENCY -92 -93 -94 -95 -96 -97 -98 74 73.5 73 72.5 72 71.5 71 70.5 -99 -100 0 1000 70 1 2 3 4 5 6 7 8 9 Reference Capacitor ESR - W Figure 26. Submit Documentation Feedback 10 0 1 2 3 4 5 6 7 8 9 Reference Capacitor ESR - W 10 Figure 27. Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT REJECTION vs POWER-SUPPLY RIPPLE FREQUENCY CONVERSION TIME vs FREE-AIR TEMPERATURE 12 -25 11.95 -30 74 11.9 -35 73.5 Output Rejection - dB 75 74.5 11.85 73 t - Time - ms SINAD - Signal-to-Noise + Distortion - dB SIGNAL-TO-NOISE + DISTORTION vs ESR 72.5 72 11.8 11.75 11.7 -40 -45 -50 -55 71.5 11.65 71 11.6 -65 70.5 11.55 -70 70 0 1 2 3 4 5 6 7 8 Reference Capacitor ESR - W 9 10 11.5 -45 -25 -75 100 -5 15 35 55 75 95 115 TA - Free Air Temperature - °C Figure 28. -60 1k Figure 29. INL 100k 10k f - Frequency - Hz 1M Figure 30. 0.3 INL - LSBs 0.2 0.1 0 -0.1 -0.2 -0.3 0 512 1024 1536 2048 2560 3072 3584 4096 Code Figure 31. DNL 0.3 DNL - LSBs 0.2 0.1 0 -0.1 -0.2 -0.3 0 512 1024 1536 2048 2560 3072 3584 4096 Code Figure 32. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 9 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) FFT -10 8192 Point FFT, fS = 40 kHz, fIN = 20 kHz at 0 dB Amplitude - dB -30 -50 -70 -90 -110 -130 0 5 10 f - Frequency - kHz 15 20 Figure 33. FFT -10 Amplitude - dB -30 8192 Point FFT, fS = 40 kHz, fIN = 10 kHz at 0 dB -50 -70 -90 -110 -130 0 5 10 f - Frequency - kHz 15 20 Figure 34. FFT -10 8192 Point FFT, fS = 40 kHz, fIN = 1 kHz at 0 dB Amplitude - dB -30 -50 -70 -90 -110 -130 0 5 10 f - Frequency - kHz 15 20 Figure 35. 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 BASIC OPERATION INTERNAL DATACLK Figure 36 shows a basic circuit to operate the ADS8512 with a ±10-V input range. To begin a conversion and serial transmission of the results from the previous conversion, a falling edge must be provided to the CONV input. BUSY goes low to indicate that a conversion has started, and stays low until the conversion is complete. During the conversion, the results of the previous conversion are transmitted via DATA while DATACLK provides the synchronous clock for the serial data. The data format is 12-bit, binary twos complement, MSB first. Each data bit is valid on both the rising and falling edge of DATACLK. BUSY is low during the entire serial transmission and can be used as a frame synchronization signal. C2 C1 0.1 µF 10 µF ADS8512 ±10 V C3 1 µF + C4 0.01 µF C5 1 µF + 1 R1IN VS 16 2 GND PWRD 15 3 R2IN BUSY 14 4 R3IN CS 13 5 BUF CONV 12 6 CAP EXT/INT 11 7 REF DATA 10 8 GND DATACLK 9 +5 V + Frame Sync (optional) Convert Pulse 40 ns min Figure 36. Basic Operating Circuit, ±10-V Input Range, Internal DATACLK EXTERNAL DATACLK Figure 37 shows another basic circuit to operate the ADS8512 with a ±10-V input range. To begin a conversion, a falling edge must be provided to the CONV input. BUSY goes low to indicate that a conversion has started and stays low until the conversion is complete. Just before BUSY rises near the end of the conversion, the conversion result held in the internal working register is transferred to the internal shift register. The internal shift register is clocked via the DATACLK input. The recommended method of reading the conversion result is to provide the serial clock after the conversion has completed. See the External DATACLK subsection under the Reading Data section of this data sheet for more information. ADS8512 ±10 V C3 1 µF + C4 0.01 µF C5 1 µF + 1 R1IN VS 16 2 GND PWRD 15 3 R2IN BUSY 14 4 R3IN CS 13 5 BUF CONV 12 6 CAP EXT/INT 11 7 REF DATA 10 8 GND DATACLK 9 C2 C1 0.1 µF 10 µF + +5 V Interrupt (optional) Chip Select (optional(1)) Convert Pulse +5 V 40 ns min External Clock NOTE: (1) Tie CS to GND if the outputs will always be active. Figure 37. Basic Operating Circuit, ±10-V Input Range, External DATACLK Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 11 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com STARTING A CONVERSION If a conversion is not currently in progress, a falling edge on the CONV input places the sample and hold into the hold mode and begins a conversion, as shown in Figure 38 according to the timing shown in Table 2. During the conversion, the CONV input is ignored. Starting a conversion does not depend on the state of CS. A conversion can be started once every 25 µs (40-kHz maximum conversion rate). There is no minimum conversion rate. t1 t2 t3 t4 t5 CONV t6 t7 BUSY t8 t10 t9 MODE Acquire t11 Convert Acquire Convert Figure 38. Basic Conversion Timing Table 2. Conversion and Data Timing, TA = –40°C to +85°C SYMBOL 12 MAX UNIT t1 Conversion plus acquisition time DESCRIPTION MIN TYP 25 µs t2 CONV low to all digital inputs stable 19 µs t3 CONV low to initiate a conversion 12 µs t4 BUSY rising to any digital input active 5 t5 CONV high before start of conversion (CONV high time) 15 t6 BUSY low 12 15 µs t7 CONV low to BUSY low 12 20 ns t8 Aperture delay (CONV falling edge to actual conversion start) 5 t9 Conversion time 12 t10 Conversion complete to BUSY rising 90 t11 Acquisition time t12 CONV low to rising edge of first internal DATACLK t13 Internal DATACLK high 300 355 425 ns t14 Internal DATACLK low 300 355 425 ns t15 Internal DATACLK period 0.6 0.71 0.85 µs t16 DATA valid to internal DATACLK rising 150 204 ns t17 Internal DATACLK falling to DATA not valid 150 208 ns t18 Falling edge of last DATACLK to BUSY rising 1.78 µs t19 External DATACLK rising to DATA not valid 2 12 t20 External DATACLK rising to DATA valid 4 14 t21 External DATACLK high 15 ns t22 External DATACLK low 15 ns t23 External DATACLK period 35 ns t24 CONV low to external DATACLK active 15 t25 External DATACLK low or CS high to BUSY rising t26 CS low to digital outputs enabled 15 ns t27 CS high to digital outputs disabled 15 ns 0.04 ns ns ns 15 ns 13.5 Submit Documentation Feedback µs µs µs 2 ns 20 ns ns 5 µs Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 Even though the CONV input is ignored while a conversion is in progress, this input should be held static during the conversion period. Transitions on this digital input can easily couple into sensitive analog portions of the converter, adversely affecting the conversion results (see the Sensitivity to External Digital Signals section of this data sheet for more information). Ideally, the CONV input should go low and remain low throughout the conversion. It should return high sometime after BUSY goes high. In addition, it should be high before the start of the next conversion for a minimum time period given by t5. This period ensures that the digital transition on the CONV input does not affect the signal that is acquired for the next conversion. An acceptable alternative is to return the CONV input high as soon after the start of the conversion as possible. For example, a negative going pulse 100ns wide would make a good CONV input signal. It is strongly recommended that from time t2 after the start of a conversion until BUSY rises, the CONV input should be held static (either high or low). During this time, the converter is more sensitive to external noise. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 13 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com READING DATA The ADS8512 digital output is in binary twos complement (BTC) format. Table 3 shows the relationship between the digital output word and the analog input voltage under ideal conditions. Table 3. Output Codes and Ideal Input Voltages DIGITAL OUTPUT BINARY TWOS COMPLEMENT DESCRIPTION ANALOG INPUT Full-scale range ±10 Least significant bit (LSB) +Full-Scale (FS - 1LSB) Midscale One LSB below midscale -Full-Scale- BINARY CODE HEX CODE 7FF 0.5 V to 4.5 V 4.88 mV 0.98 mV 9.99512 V 4.49902 V 0111 1111 1111 0V 2.5 V 0000 0000 0000 000 -4.88 mV 2.49902 mV 1111 1111 1111 FFF -10 V 0.5 V 1000 0000 0000 800 Figure 39 shows the relationship between the various digital inputs, digital outputs, and internal logic of the ADS8512. Figure 40 illustrates when the internal shift register of the ADS8512 is updated and how this relates to a single conversion cycle. Together, these two figures highlight very important aspect of the ADS8512: the conversion result is not available until after the conversion is complete. The implications of this constraint are discussed in the following sections. CONV t25 t6 – t25 BUSY NOTE: Update of the internal shift register occurs in the shaded region. If EXT/INT is HIGH, then DATACLK must be LOW or CS must be HIGH during this time. Figure 39. Timing of the Shift Register Update t1 CONV BUSY t13 t12 t15 DATACLK 1 2 t16 3 t18 10 11 12 Bit 2 Bit 1 LSB 1 t14 t17 DATA MSB Bit 10 Bit 9 MSB Figure 40. Serial Data Timing, Internal Clock (EXT/INT and CS Low) 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 Internal DATACLK With EXT/INT tied low, the result from conversion n is serially transmitted during conversion n+1, as shown in Figure 41, with the timing given in Table 2. Serial transmission of data occurs only during a conversion. When a transmission is not in progress, DATA and DATACLK are low. Converter Core REF CDAC CONV Clock Control Logic BUSY Each flip-flop in the working register is latched as the conversion proceeds Working Register D Q D Q D Q D Q D Q ••• W0 W1 W2 W14 W15 Update of the shift register occurs just prior to BUSY rising (1) Shift Register D Q D Q D Q D Q D Q D DATA Q EXT/INT S0 S1 S2 S14 S15 SOUT Delay DATACLK CS NOTE: (1) If EXT/INT is HIGH (external clock), DATACLK is HIGH, and CS is LOW during this time, the shift register will not be updated and the conversion result will be lost. Figure 41. Block Diagram of the ADS8512 Digital Inputs and Outputs During the conversion, the results of the previous conversion are transmitted via DATA, while DATACLK provides the synchronous clock for the serial data. The data format is 12-bit, binary twos complement, MSB first. Each data bit is valid on both the rising and falling edges of DATACLK. BUSY is low during the entire serial transmission and can be used as a frame synchronization signal. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 15 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com External DATACLK With EXT/INT tied high, the result from conversion n is clocked out after the conversion has completed, during the next conversion (n+1), or a combination of these two. Figure 42 shows the case of reading the conversion result after the conversion is complete. Figure 43 describes reading the result during the next conversion. Figure 44 combines the important aspects of Figure 42 and Figure 43 for reading part of the result after the conversion is complete and the balance during the next conversion. The serial transmission of the conversion result is initiated by a rising edge on DATACLK. The data format is 12-bit, binary twos complement, MSB first. Each data bit is valid on the falling edge of DATACLK. In some cases, it might be possible to use the rising edge of the DATACLK signal. However, one extra clock period (not shown in Figure 42, Figure 43, and Figure 44) is needed for the final bit. The external DATACLK signal must be low or CS must be high before BUSY rises (see time t25 in Figure 43 and Figure 44). If this limit is not observed during this time, the output shift register of the ADS8512 is not updated with the conversion result. Instead, the previous contents of the shift register remain and the new result is lost. Before reading the next three paragraphs, consult the Sensitivity to External Digital Signals section of this data sheet. That section explains many of the concerns regarding how and when to apply the external DATACLK signal. External DATACLK Active After the Conversion The preferred method of obtaining the conversion result is to provide the DATACLK signal after the conversion has been completed and before the next conversion starts, as shown in Figure 42. Note that the DATACLK signal should be static before the start of the next conversion. If this limit is not observed, the DATACLK signal could affect the voltage that is acquired. t1 t5 CONV BUSY t21 t4 DATACLK t23 1 2 3 t19 4 10 11 12 t22 t20 DATA MSB Bit 10 Bit 9 Bit 2 Bit 1 LSB Figure 42. Serial Data Timing, External Clock, Clocking After the Conversion Completes (EXT/INT High, CS Low) 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 External DATACLK Active During the Next Conversion Another method of obtaining the conversion result is shown in Figure 43. Because the output shift register is not updated until the end of the conversion, the previous result remains valid during the next conversion. If a fast clock (≥ 2MHz) can be provided to the ADS8512, the result can be read during time t2. During this time, the noise from the DATACLK signal is less likely to affect the conversion result. t1 t2 CONV BUSY t21 t24 t23 DATACLK 1 2 3 t19 t25 4 11 12 1 t22 t20 DATA MSB Bit 10 Bit 9 Bit 1 LSB MSB Figure 43. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT High, CS Low) External DATACLK Active After the Conversion and During the Next Conversion Figure 44 shows a method that combines the two previous approaches. This method works very well for microcontrollers that do serial transfers 8 bits at a time and for slower microcontrollers. For example, if the fastest serial clock that the microcontroller can produce is 1 µs, the approach shown in Figure 42 would result in a diminished throughput (26-kHz maximum conversion rate). The method described in Figure 43 could not be used without risk of affecting the conversion result (the clock would have to be active after time t2). Therefore, the approach in Figure 44 results in an improved throughput rate (33 kHz maximum with a 1-µs clock), and DATACLK is not active after time t2. CONV BUSY t5 t24 t4 DATACLK DATA 1 2 MSB n Bit 10 t25 n+1 Bit n Bit n-1 11 12 Bit 1 LSB Figure 44. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion (EXT/INT High, CS Low) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 17 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com CHIP SELECT The CS input allows the digital outputs of the ADS8512 to be disabled and gates the external DATACLK signal when EXT/INT is high. See Figure 45 for the enable and disable time associated with CS and Figure 41 for a block diagram of the ADS8512 logic. The digital outputs can be disabled at any time. CS t26 BUSY, DATA, DATACLK (1) t27 HI-Z Active HI-Z NOTE: (1) DATACLK is an output only when EXT/INT is LOW. Figure 45. Enable and Disable Timing for Digital Outputs Note that a conversion is initiated on the falling edge of CONV even if CS is high. If the EXT/INT input is low (internal DATACLK) and CS is high during the entire conversion, the previous conversion result is lost (that is, the serial transmission occurs but DATA and DATACLK are disabled). 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 ANALOG INPUT The ADS8512 offers a number of input ranges. This set of options is accomplished by connecting the three input resistors to either the analog input (VIN), to ground (GND), or to the 2.5-V reference buffer output (BUF). Table 1 shows the input ranges that are typically used in most data acquisition applications. These ranges are all specified to meet the specifications given in the Electrical Characteristics table. Table 4 contains a complete list of ideal input ranges, associated input connections, and comments regarding the range. Table 4. Complete list of Ideal Input Ranges ANALOG INPUT RANGE (V) CONNECT R1IN TO CONNECT R2IN TO CONNECT R3IN TO INPUT IMPEDANCE (kΩ) 0.3125 to 2.8125 VIN –0.417 to 2.916 VIN VIN VIN > 10,000 VIN BUF 26.7 0.417 to 3.750 VIN cannot go below GND – 0.3V VIN VIN GND 26.7 Offset and gain not specified ±3.333 VIN BUF VIN 21.3 Specified offset and gain –15 to 5 VIN BUF BUF 45.7 Offset and gain not specified ±10 VIN BUF GND 45.7 Specified offset and gain 0.833 to 7.5 VIN GND VIN 21.3 Offset and gain not specified –2.5 to 17.5 VIN GND BUF 45.7 Offset and gain not specified 2.5 to 22.5 VIN GND GND 45.7 Offset and gain not specified 0 to 2.857 BUF VIN VIN 45.7 Offset and gain not specified –1 to 3 BUF VIN BUF 21.3 VIN cannot go below GND – 0.3V 0 to 4 BUF VIN GND 21.3 Specified offset and gain –6.25 to 3.75 BUF BUF VIN 26.7 Offset and gain not specified 0 to 10 BUF GND VIN 26.7 Specified offset and gain 0.357 to 3.214 GND VIN VIN 45.7 Offset and gain not specified –0.5 to 3.5 GND VIN BUF 21.3 VIN cannot go below GND – 0.3V 0.5 to 4.5 GND VIN GND 21.3 Specified offset and gain ±5 GND BUF VIN 26.7 Specified offset and gain 1.25 to 11.25 GND GND VIN 26.7 Offset and gain not specified COMMENT Specified offset and gain +15 V 2.2 mF 22 pF ADS8512 GND R1IN 100 nF 2 kW Pin 7 2 kW GND Pin 1 Pin 2 VIN 22 pF OPA627 or OPA132 + Pin 3 Pin 4 GND R3IN R2IN Pin 6 BUF 2.2 mF CAP GND REF 1 mF 100 nF 2.2 mF GND GND -15 V GND Figure 46. Typical Driving Circuit (±10 V, No Trim) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 19 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com The input impedance results from the various connections and the internal resistor values (refer to the block diagram on the front page of this data sheet). The internal resistor values are typical and can change by ±30% as a result of process variations. However, the ratio matching of the resistors is considerably better than this range. Thus, the input range only varies a few tenths of a percent from part to part, while the input impedance can vary up to ±30%. The Electrical Characteristics table contains the maximum limits for the variation of the analog input range, but only for those ranges where the comment field shows that the offset and gain are specified (including all the ranges listed in Table 1). For the other ranges, the offset and gain are not tested and are not specified. Three of the input ranges in Table 4 are not recommended for general use. These input ranges involve the connection at R2IN being driven below GND. This input has a reverse-biased ESD protection diode connection to ground. If R2IN is taken below GND – 0.3V, this diode will be forward-biased and will clamp the negative input at –0.4V to –0.7V, depending on the temperature. Since the negative full-scale value of these input ranges exceed –0.4V, they are not recommended. Note that Table 4 assumes that the voltage at the REF pin is +2.5V. This assumption is true if the internal reference is being used or if the external reference is +2.5V. Other reference voltages change the values inTable 4. HIGH IMPEDANCE MODE When R1IN, R2IN, and R3IN are connected to the analog input, the input range of the ADS8512 is 0.3125 V to 2.8125 V and the input impedance is greater than 10 MΩ. This input range can be used to connect the ADS8512 directly to a wide variety of sensors. Figure 47 shows the impedance of the sensor versus the change in INL and DNL of the ADS8512. The performance of the ADS8512 can be improved for higher sensor impedance by allowing more time for acquisition. For example, 10 µs of acquisition time approximately doubles sensor impedance for the same INL/DNL performance. The input impedance and capacitance of the ADS8512 are very stable over temperature. Assuming that this performance is true of the sensor as well, the graph shown in Figure 47 will vary less than a few percent over the ensured temperature range of the ADS8512. If the sensor impedance varies significantly with temperature, the worst-case impedance should be used. LINEARITY ERROR vs SOURCE IMPEDANCE 10 TA = +25°C Acquisition Time = 5 µs Change in Worst-Case Linearity Error (LSBs) 9 DNL 8 7 6 INL 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 External Source Impedance (kW) Figure 47. Linearity Error vs Source Impedance in High Impedance Mode (R1IN = R2IN = R3IN = VIN) 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 DRIVING THE ADS8512 ANALOG INPUT In general, any reasonably fast, high-quality operational or instrumentation amplifier can be used to drive the ADS8512 input. When the converter enters the acquisition mode, there is some charge injection from the converter input to the amplifier output. This charge injection can result in inadequate settling time with slower amplifiers. Be very careful with single-supply amplifiers, particularly if their output is required to swing very close to the supply rails. In addition, be careful with regard to the amplifier linearity. The outputs of single-supply and rail-to-rail amplifiers can saturate as the outputs approach the supply rails. Rather than the amplifier transfer function being a straight line, the curve can become severely S-shaped. Also, watch for the point where the amplifier switches from sourcing current to sinking current. For some amplifiers, the transfer function can be noticeably discontinuous at this point, causing a significant change in the output voltage for a much smaller change on the input. Texas Instruments manufactures a wide variety of operational and instrumentation amplifiers that can be used to drive the input of the ADS8512. These include the OPA627, OPA132, and INA110. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 21 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com REFERENCE The ADS8512 can be operated with its internal 2.5-V reference or an external reference. By applying an external reference voltage to the REF pin, the internal reference voltage is overdriven. The voltage at the REF input is internally buffered by a unity gain buffer. The output of this buffer is present at the BUF and CAP pins. REF The REF pin is the output of the internal 2.5-V reference or the input for an external reference. A 1-µF to 2.2-µF tantulum capacitor should be connected between this pin and ground. The capacitor should be placed as close to the ADS8512 as possible. When using the internal reference, the REF pin should not be connected to any type of significant load. An external load will cause a voltage drop across the internal 4-kΩ resistor that is in series with the internal reference. Even a 40-MΩ external load to ground will cause a decrease in the full-scale range of the converter by 6 LSBs. The range for the external reference is 2.3 V to 2.7 V. The voltage on REF determines the full-scale range of the converter and the corresponding LSB size. Increasing the reference voltage increases the LSB size in relation to the internal noise sources which, in turn, can improve signal-to-noise ratio. Likewise, decreasing the reference voltage reduces the LSB size and signal-to-noise ratio. CAP The CAP pin is used to compensate the internal reference buffer. A 1-µF tantalum capacitor in parallel with a 0.01-µF ceramic capacitor should be connected between this pin and ground, with the ceramic capacitor placed as close to the ADS8512 as possible. The total value of the capacitance on the CAP pin is critical to optimum performance of the ADS8512. A value larger than 2.0 µF could overcompensate the buffer while a value lower than 0.5 µF may not provide adequate compensation. The equivalent series resistance (ESR) of these compensation capacitors is also critical. Keep the total ESR under 3 Ω. See Figure 25 through Figure 28 for how the worst-case INL is affected by ESR. BUF The voltage on the BUF pin is the output of the internal reference buffer. This pin is used to provide +2.5 V to the analog input or inputs for the various input configurations. The BUF output can provide up to 1 mA of current to an external load. The load should be constant because a variable load could affect the conversion result by modulating the BUF voltage. Also note that the BUF output shows significant glitches as each bit decision is made during a conversion. Between conversions, the BUF output is quiet. 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 POWER DOWN The ADS8512 has a power-down mode that is activated by taking CONV low and then PWRD high. This mode will power down all of the analog circuitry including the reference, reducing power dissipation to under 50 µW. To exit the power-down mode, CONV is taken high and then PWRD is taken low. Note that a conversion is initiated if PWRD is taken high while CONV is low. While in the power-down mode, the voltage on the capacitors connected to CAP and REF begins to leak off. The voltage on the CAP capacitor leaks off much more rapidly than on the REF capacitor (the REF input of the ADS8512 becomes high-impedance when PWRD is high—this is not true for the CAP input). When exiting power-down mode, these capacitors must be allowed to recharge and settle to a 12-bit level. Figure 48 shows the amount of time typically required to obtain a valid 12-bit result based on the amount of time spent in power down (at room temperature). This figure assumes that the total capacitance on the CAP pin is 1.01 µF. Figure 49 shows a circuit that can significantly reduce the power-up time if the power down time is fairly brief (a few seconds or less). A low on-resistance MOSFET is used to disconnect the capacitance on the CAP pin from the leakage paths internal to the ADS8512. This disconnection allows the capacitors to retain the respecetive charges for a much longer period of time, reducing the time required to recharge them at power-up. With this circuit, the power-down time can be extended to tens or hundreds of milliseconds with almost instantaneous power-up. Power-Up Time to Rated Accuracy (µs) POWER-DOWN TO POWER-UP RESPONSE 300 TA = +25°C 250 200 150 100 50 0 0.1 1 10 100 Power-Down Duration (ms) Figure 48. Power-Down to Power-Up Response 1RF7604 + 1 µF ADS8512 1 8 1 R1IN VS 16 2 7 2 GND PWRD 15 3 6 3 R2IN BUSY 14 4 5 4 R3IN CS 13 5 BUF CONV 12 6 CAP EXT/INT 11 7 REF DATA 10 8 GND DATACLK 9 0.01 µF Power-Down Signal Figure 49. Improved Power-Up Response Circuit Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 23 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com LAYOUT POWER FOR SO-16 PACKAGE For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the analog and digital grounds together. As noted in the Electrical Characteristics table, the ADS8512 uses 90% of its power for the analog circuitry. The ADS8512 should be considered as an analog component. The +5-V power for the A/D converter should be separate from the +5 V used for the system digital logic. Connecting +VS directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, VS should be tied to the same +5-V source. GROUNDING All the ground pins of the A/D converter should be tied to an analog ground plane (separated from the system digital logic ground) to achieve optimum performance. Both analog and digital ground planes should be tied to the system ground as close to the power supplies as possible. This layout helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. SIGNAL CONDITIONING The FET switches used for the sample-and-hold on many CMOS A/D converters release a significant amount of charge injection that can cause the driving op amp to oscillate. The amount of charge injection due to the sampling FET switch on the ADS8512 is approximately 5% to 10% of the amount on similar A/D converters with the charge redistribution digital-to-analog converter (DAC) CDAC architecture. There is also a resistive front-end that attenuates any released charge. The end result is a minimal requirement for the drive capability on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application is sufficient to drive the ADS8512. The resistive front-end of the ADS8512 also provides a specified ±25-V overvoltage protection. In most cases, this architecture eliminates the need for external over-voltage protection circuitry. SENSITIVITY TO EXTERNAL DIGITAL SIGNALS All successive approximation register-based A/D converters are sensitive to external sources of noise. For the ADS8512 and similar A/D converters, this noise most often originates because of the transition of external digital signals. While digital signals that run near the converter can be the source of the noise, the biggest problem occurs with the digital inputs to the converter itself. In many cases, the system designer may not be aware that there is a problem or a potential for a problem. For a 12-bit system, these problems typically occur at the least significant bits and only at certain places in the converter transfer function. For a 12-bit converter, the problem can be much easier to spot. For example, the timing diagram in Figure 38 shows that the CONV signal should return high sometime during time t2. In fact, the CONV signal can return high at any time during the conversion. However, after time t2, the transition of the CONV signal has the potential of creating a good deal of noise on the ADS8512 die. If this transition occurs at just precisely the wrong time, the conversion results could be affected. In a similar manner, transitions on the DATACLK input could affect the conversion result. For the ADS8512, there are 12 separate bit decisions that are made during the conversion. The most significant bit decision is made first, proceeding to the least significant bit at the end of the conversion. Each bit decision involves the assumption that the bit being tested should be set. This action is combined with the result that has been achieved so far. The converter compares this combined result with the actual input voltage. If the combined result is too high, the bit is cleared. If the result is equal to or lower than the actual input voltage, the bit remains high. This effect is why the basic architecture is referred to as a successive approximation register (SAR). 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 If the result so far is getting very close to the actual input voltage, then the comparison involves two voltages that are very close together. The ADS8512 has been designed so that the internal noise sources are at a minimum just before the comparator result is latched. However, if an external digital signal transitions at this time, a great deal of noise will be coupled into the sensitive analog section of the ADS8512. Even if this noise produces a difference between the two voltages of only 2 mV, the conversion result will be off by 52 counts or least significant bits (LSBs). (The internal LSB size of the ADS8512 is 38 µV, regardless of the input range.) Once a digital transition has caused the comparator to make a wrong bit decision, the decision cannot be corrected (unless some type of error correction is employed). All subsequent bit decisions will then be wrong. Figure 50 shows a successive approximation process that has gone wrong. The dashed line represents what the correct bit decisions should have been. The solid line represents the actual result of the conversion. External Noise SAR Operation after Wrong Bit Decision Actual Input Voltage Converter Full-Scale Input Voltage Range Proper SAR Operation Internal DAC Voltage Wrong Bit Decision Made Here t Conversion Clock Conversion Start (Hold Mode) 1 1 0 0 0 0 Incorrect Result (1 0 1 1 0 1) Correct Result Figure 50. SAR Operation When External Noise Affects the Conversion Keep in mind that the time period when the comparator is most sensitive to noise is fairly small. Also, the peak portion of the noise event produced by a digital transition is fairly brief, because most digital signals transition in a few nanoseconds. The subsequent noise may last for a period of time longer than this and may induce further effects that require a longer settling time. However, in general, the event is over within a few tens of nanoseconds. For the ADS8512, error correction is done when the tenth bit is decided. During this bit decision, it is possible to correct limited errors that may have occurred during previous bit decisions. However, after the tenth bit, no such correction is possible. Note that for the timing diagrams shown in Figure 38, Figure 40, Figure 42, Figure 43, and Figure 44 all external digital signals should remain static from 8 µs after the start of a conversion until BUSY rises. The tenth bit is decided approximately 10 µs to 11 µs into the conversion. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 25 ADS8512 SLAS485 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION AVERAGING Converter noise can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√Hz where n is the number of averages. For example, averaging four conversion results reduces the transition noise (TN) by 1/2 to 0.4 LSBs. Averaging should only be used for input signals with frequencies near dc. For ac signals, a digital filter can be used to low-pass filter and decimate the output codes. This action works in a similar manner to averaging: for every decimation by 2, the signal-to-noise ratio improves 3 dB. ADS8512 AS AN SPI MASTER DEVICE (INT/EXT TIED LOW) Figure 51 shows a simple interface between the ADS8512 and an SPI-equipped microcontroller or TMS320 series digital signal processor (DSP) when using the internal serial data clock. This interface assumes that the microcontroller or DSP is configured as an SPI slave, is capable of receiving 12-bit transfers, and that the ADS8512 is the only serial peripheral on the SPI bus. ADS8512 Microcontroller TOUT CONV SS BUSY MOSI SDATA SCLK DATACLK EXT/INT SPI Slave CS SPI Master NOTE: CPOL = 0 (inactive SCLK is LOW) CPHA = 0 or 1 (data valid on either SCLK edge) Figure 51. ADS8512 as SPI Master To maintain synchronization with the ADS8512, the microcontroller slave select (SS) input should be connected to the BUSY output of the ADS8512. When a transition from high-to-low occurs on BUSY (indicating the current conversion is in process), the ADS8512 internal SCLK begins shifting the previous conversion data into the MOSI pin of the microcontroller. In this scenario, the CONV input to the ADS8512 can be controlled from an external trigger source, or a trigger generated by the microcontroller. The ADS8512 internal SCLK provides 150ns (min) of setup and hold timing on the SDATA output, allowing the microcontroller to sample data on either the rising or falling edge of SCLK. 26 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 ADS8512 www.ti.com ...................................................................................................................................................................................................... SLAS485 – JUNE 2008 ADS8512 AS AN SPI SLAVE DEVICE (INT/EXT TIED HIGH) Figure 52 shows another interface between the ADS8512 and an SPI-equipped microcontroller or DSP in which the host processor acts as an SPI master device. ADS8512 Microcontroller TOUT CONV INT BUSY MOSI SDATA SCLK DATACLK VS EXT/INT CS SPI Master SPI Slave NOTE: CPOL = 0 (inactive SCLK is LOW) CPHA = 1 (data valid on SCLK falling edge) Figure 52. ADS8512 as SPI Slave In this configuration, the data transfer from the ADS8512 is triggered by the rising edge of the serial data clock provided by the SPI master. The SPI interface should be configured to read valid SDATA on the falling edge of SCLK. As noted in the EXTERNAL DATACLK section of this datasheet, when a minimum of 13 SCLKs are provided to the ADS8512, data can be strobed to the host processor on the rising SCLK edge providing a 2ns (min) hold time. When using an external interrupt to facilitate serial data transfers, as shown in Figure 52, there are two options for the configuration of the interrupt service routine (ISR): falling-edge-triggered or rising-edge-triggered. A falling-edge-triggered transfer would initiate an SPI transfer after the falling edge of BUSY, providing the host controller with the previous conversion results, while the current conversion cycle is underway. The timing for this type of interface is described in detail in Figure 43. Care must be taken to ensure the entire 12-bit conversion result is retrieved from the ADS8512 before BUSY returns high to avoid the potential corruption of the current conversion cycle (consult the Sensitivity to External Digital Signals section of this data sheet). A rising-edge-triggered transfer is the preferred method of obtaining the conversion results. This timing is depicted in Figure 42. This method of obtaining data ensures that SCLK is static during the conversion cycle and provides the host processor with current cycle conversion results. 8-BIT SPI INTERFACE For microcontrollers that only support 8-bit SPI transfers, it is recommended to configure the ADS8512 for SPI slave operation, as depicted in Figure 52. With the microcontroller configured as the SPI master, two 8-bit transfers are required to obtain full 12-bit conversion results from the ADS8512. The eight MSBs of the conversion result are considered valid on the falling SCLK edges of the first transfer, with the remaining four LSBs being valid on the first four falling SCLK edges in the second transfer. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8512 27 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS8512IBDW ACTIVE SOIC DW 16 ADS8512IBDWR ACTIVE SOIC DW 16 ADS8512IDW ACTIVE SOIC DW 16 ADS8512IDWR ACTIVE SOIC DW 16 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) Call TI Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) Call TI Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 40 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS8512IDWR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.75 10.7 2.7 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8512IDWR SOIC DW 16 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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