ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS8323 FEATURES 1 • • • • • 2 DESCRIPTION HIGH-SPEED PARALLEL INTERFACE 500kSPS SAMPLING RATE LOW POWER: 85mW at 500kSPS BIPOLAR INPUT RANGE TQFP-32 PACKAGE The ADS8323 is a 16-bit, 500kSPS analog-to-digital converter (ADC) with an internal 2.5V reference. The device includes a 16-bit, capacitor-based successive approximation register (SAR) ADC with inherent sample-and-hold. The ADS8323 offers a full 16-bit interface, or an 8-bit option where data are read using two read cycles. The ADS8323 is available in a TQFP-32 package and is specified over the industrial –40°C to +85°C temperature range. APPLICATIONS • • • • HIGH-SPEED DATA ACQUISITION OPTICAL POWER MONITORING MOTOR CONTROL ATE white space here white space here white space here white space here white space here BYTE SAR ADS8323 Output Latches and 3-State Drivers Parallel Data Output +IN CDAC -IN S/H Amp CLOCK Comparator REFIN REFOUT Internal +2.5V Ref Conversion and Control Logic CONVST CS RD BUSY 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2010, Texas Instruments Incorporated ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) NO MISSING CODES ERROR (LSB) ADS8323Y ±8 14 PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE TQFP-32 PBS –40°C to +85°C PACKAGE MARKING TRANSPORT MEDIA, QUANTITY Tape and reel, 250 Tape and reel, 2000 Tape and reel, 250 ADS8323YB ±6 15 TQFP-32 PBS –40°C to +85°C Tape and reel, 2000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). ADS8323 UNIT Supply voltage, DGND to DVDD –0.3 to 6 V Supply voltage, AGND to AVDD –0.3 to 6 V Analog input voltage range AGND – 0.3 to AVDD + 0.3 V Reference input voltage AGND – 0.3 to AVDD + 0.3 V Digital input voltage range DGND – 0.3 to DVDD + 0.3 V ±0.3 V Ground voltage differences, AGND to DGND Voltage differences, DVDD to AGND –0.3 to 6 V 850 mW Operating virtual junction temperature range, TJ –40 to +150 °C Operating free-air temperature range, TA –40 to +85 °C Storage temperature range –65 to +150 °C Power dissipation (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). PARAMETER MIN NOM MAX UNIT AVDD (1) 4.75 5.0 5.25 V DVDD (1) 4.75 5.0 5.25 V +REFIN V 2.55 V POWER SUPPLY ANALOG/REFERENCE INPUTS Differential analog input voltage, IN+ to IN– –REFIN External reference voltage (1) 1.5 2.5 The voltage difference between AVDD and DVDD terminals cannot exceed 0.3V to maintain performance specifications. DISSIPATION RATINGS (1) 2 PACKAGE TA ≤ +25°C POWER RATING DERATING FACTOR ABOVE TA = +25°C (1) TA = +70°C POWER RATING TA = +85°C POWER RATING TQFP-32 1636mW 13.09mW/°C 1047mW 850mW This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). Thermal resistances are not production tested and are for informational purposes only. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. ADS8323YB (1) ADS8323Y PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT RESOLUTION Resolution 16 16 Bits ANALOG INPUT Full-scale input span (2) Absolute input range +IN – (–IN) –VREF +VREF –VREF +VREF V +IN –0.3 AVDD + 0.3 –0.3 AVDD + 0.3 V –IN –0.3 AVDD + 0.3 –0.3 AVDD + 0.3 V Capacitance 25 25 pF Leakage current ±1 ±1 nA SYSTEM PERFORMANCE No missing codes 14 15 Integral linearity error ±4 Differential linearity error ±3 Offset error Gain error (4) Common-mode rejection ratio ±3 ±1 ±2 ±0.5 ±1.0 mV ±0.25 ±0.50 ±0.12 ±0.25 %FSR ±1 LSB At dc 70 70 VIN = 1VPP at 1MHz 50 50 dB 60 60 μVRMS ±3 ±3 LSBs Noise Power-supply rejection ratio Bits ±6 LSB (3) ±8 At FFFFh output code dB SAMPLING DYNAMICS Conversion time 1.6 Acquisition time 350 1.6 μs 500 kSPS 350 Throughput rate ns 500 Aperture delay 10 10 Aperture jitter 30 30 ns ps Small-signal bandwidth 20 20 MHz Step response 100 100 ns Overvoltage recovery 150 150 ns DYNAMIC CHARACTERISTICS Total harmonic distortion (5) VIN = 5VPP at 100kHz –90 –93 dB SINAD VIN = 5VPP at 100kHz 81 83 dB Spurious free dynamic range VIN = 5VPP at 100kHz 94 96 dB REFERENCE OUTPUT Voltage Source current Drift Line regulation IOUT = 0 2.475 2.50 Static load 2.525 2.48 2.50 10 2.52 V 10 μA IOUT = 0 25 25 ppm/°C 4.75V ≤ VCC ≤ 5.25V 0.6 0.6 mV REFERENCE INPUT Range (1) (2) (3) (4) (5) 1.5 2.55 1.5 2.55 V Shaded cells indicate different specifications from ADS8322Y. Ideal input span; does not include gain or offset error. LSB means least significant bit, with VREF equal to +2.5V; 1LSB = 76μV. Measured relative to an ideal, full-scale input [+In – (–In)] of 4.9999V. Thus, gain error includes the error of the internal voltage reference. Calculated on the first nine harmonics of the input frequency. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 3 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. ADS8323YB (1) ADS8323Y PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family CMOS CMOS Logic levels: VIH IIH ≤ +5μA 3.0 +DVDD 3.0 +DVDD V VIL IIL ≤ –5μA –0.3 0.8 –0.3 0.8 V VOH IOH = –1.6mA 4.0 VOL IOH = +1.6mA Data format 4.0 V 0.4 0.4 Binary twos complement Binary twos complement V POWER-SUPPLY REQUIREMENTS Power-supply voltage +AVDD 4.75 5 5.25 4.75 5 5.25 +DVDD 4.75 5 5.25 4.75 5 5.25 V V Supply current fSAMPLE = 500kSPS 17 25 17 25 mA Power dissipation fSAMPLE = 500kSPS 85 125 85 125 mW +85 °C TEMPERATURE RANGE Specified performance –40 +85 –40 EQUIVALENT INPUT CIRCUITS DVDD AVDD RON 20W C(SAMPLE) 20pF DIN AIN DGND AGND Diode Turn-On Voltage: 0.35V Equivalent Analog Input Circuit 4 Submit Documentation Feedback Equivalent Digital Input Circuit Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 DEVICE INFORMATION REFOUT REFIN NC NC +AVDD AGND +IN -IN PBS PACKAGE TQFP-32 (TOP VIEW) 32 31 30 29 28 27 26 25 DB13 3 22 RD DB12 4 21 CONVST DB11 5 20 CLOCK DB10 6 19 DGND DB9 7 18 +DVDD DB8 8 17 BUSY 9 10 11 12 13 14 15 16 DB0 BYTE DB1 23 DB2 2 DB3 DB14 DB4 CS DB5 24 DB6 1 DB7 DB15 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 5 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com PIN ASSIGNMENTS TERMINAL (1) 6 NO NAME I/O (1) 1 DB15 DO Data Bit 15 (MSB) 2 DB14 DO Data Bit 14 3 DB13 DO Data Bit 13 4 DB12 DO Data Bit 12 5 DB11 DO Data Bit 11 6 DB10 DO Data Bit 10 7 DB9 DO Data Bit 9 8 DB8 DO Data Bit 8 DESCRIPTION 9 DB7 DO Data Bit 7 10 DB6 DO Data Bit 6 11 DB5 DO Data Bit 5 12 DB4 DO Data Bit 4 13 DB3 DO Data Bit 3 14 DB2 DO Data Bit 2 15 DB1 DO Data Bit 1 16 DB0 DO Data Bit 0 (LSB) 17 BUSY DO High when a conversion is in progress. 18 +DVDD P Digital Power Supply, +5VDC. 19 DGND P Digital Ground 20 CLOCK DI An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source. 21 CONVST DI Convert Start 22 RD DI Synchronization pulse for the parallel output. 23 BYTE DI Selects eight most significant bits (low) or eight least significant bits (high). Data valid on pins 9-16. 24 CS DI Chip Select 25 –IN AI Inverting Input Channel 26 +IN AI Noninverting Input Channel 27 AGND P Analog Ground 28 +AVDD P Analog Power Supply, +5VDC. 29 NC — No connection 30 NC — No connection 31 REFIN AI Reference Input. When using the internal 2.5V reference, tie this pin directly to REFOUT. 32 REFOUT AO Reference Output. A 0.1μF capacitor should be connected to this pin when the internal reference is used. AI is analog input, AO is analog output, DI is digital input, DO is digital output, and P is power-supply connection. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 TIMING INFORMATION tC1 tW2 tW1 CLOCK 2 1 3 Acquisition 4 5 17 18 19 Conversion Acquisition tCONV tACQ 20 1 2 3 4 17 18 19 20 tD1 CONVST tW3 BUSY tW4 tD2 tD4 BYTE tD3 tW5 CS tD5 tD6 tD9 tD8 tW7 tW6 RD tD7 DB15-D8 Bits 15-8 Bits 15-8 FF DB7-D0 Bits 7-0 Bits 7-0 Bits 15-8 TIMING CHARACTERISTICS (1) (2) All specifications typical at –40°C to +85°C, +DVDD = +5V. ADS8323 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.6 μs tCONV Conversion Time tAQC Acquisition Time 350 ns tC1 CLOCK Period 100 ns tW1 CLOCK High Time 40 ns tW2 CLOCK Low Time 40 ns tD1 CONVST Low to Clock High 10 ns tW3 CONVST Low Time 20 tD2 CONVST Low to BUSY High tD3 CS Low to CONVST Low 0 tW4 CONVST High 20 tD4 CLOCK High to BUSY Low tW5 CS High 0 ns tD5 CS Low to RD Low 0 ns tD6 RD High to CS High 0 ns tW6 RD Low Time 50 ns tD7 RD Low to Data Valid 40 ns tD8 Data Hold from RD High 5 ns tD9 BYTE Change to RD Low (3) 0 ns tW7 RD High Time 20 ns (1) (2) (3) ns 25 ns ns ns 25 ns All input signals are specified with rise and fall times of 5ns, tR = tF = 5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH) /2. See timing diagram. BYTE is asynchronous; when BYTE is '0', bits 15 through 0 appear at DB15-DB0. When BYTE is '1', bits 15 through 8 appear on DB7-DB0. RD may remain low between changes in BYTE. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 7 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 100.1kHz, –0.2dB) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 0 90 SNR, SINAD (dB) -30 Amplitude (dB) -50 -70 -90 85 SNR 80 SINAD -110 -130 75 0 25 50 75 1 100 125 150 175 200 225 250 10 Frequency (kHz) Figure 1. 250 Figure 2. SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY -100 95 -95 -90 SFDR THD 85 -85 80 -80 0.3 22.9 0.2 15.3 0.1 7.6 0 75 -0.1 -40 -75 1 10 100 250 0 -7.6 -20 0 Frequency (kHz) Figure 3. INL– vs TEMPERATURE 60 80 100 DNL+ vs TEMPERATURE 3.8 0 0.25 19.1 0.15 11.4 0.05 3.8 -0.05 -3.8 -3.8 -0.10 -7.6 -0.15 -11.4 -0.20 -15.3 -40 -20 0 20 40 Temperature (°C) 60 80 100 -0.15 -40 -20 Figure 5. 0 20 40 Temperature (°C) 60 80 Delta (mV) -0.05 Delta (LSB) 0 Delta (mV) Delta (LSB) 20 40 Temperature (°C) Figure 4. 0.05 8 Delta (mV) 90 INL+ vs TEMPERATURE Delta (LSB) 100 THD (dB) SFDR (dB) 100 Frequency (kHz) -11.4 100 Figure 6. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. GAIN ERROR vs TEMPERATURE 762.9 0.4 30.5 8 610.4 0.2 15.3 6 457.8 4 305.2 2 152.6 0 0 0 Delta (LSB) 10 -0.2 -15.3 -0.4 -30.5 0 -45.8 -2 -0.6 Ð40 Ð20 0 20 40 Temperature (°C) 60 80 100 -152.6 -40 0 -20 20 40 Temperature (°C) Figure 7. 80 100 IQ vs TEMPERATURE 2.0 26.2 1.0 13.1 0.8 0 0.4 -13.1 -2.0 -26.2 -3.0 -39.3 -4.0 -52.4 -5.0 -65.5 -6.0 -78.6 -7.0 -91.8 Delta (LSB) -1.0 Delta (mA) 0 Delta (mV) 60 Figure 8. VREF vs TEMPERATURE 0 -0.4 -0.8 -104.9 -8.0 -40 -20 0 20 40 60 80 -1.2 100 Temperature (°C) -40 0 -20 Figure 9. 20 40 60 80 100 Figure 10. BIPOLAR ZERO vs TEMPERATURE POSITIVE FULL-SCALE vs TEMPERATURE 5.4 412.0 1.0 76.3 4.4 335.7 0.6 45.8 3.4 253.4 0.2 15.3 2.4 183.1 -0.2 -15.3 1.4 106.8 -0.6 -45.8 0.4 30.5 -1.0 -40 -20 0 20 40 Temperature (°C) 60 80 -76.3 100 Delta (LSB) 106.8 -0.6 -40 -20 Figure 11. 0 20 40 Temperature (°C) 60 80 Delta (mV) 1.4 Delta (mV) Delta (LSB) Delta (mV) 45.8 Delta (mV) Delta (LSB) DNL– vs TEMPERATURE 0.6 -45.8 100 Figure 12. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 9 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE 0 0 -1 -76.3 -2 -152.6 -3 -228.9 -4 -305.2 -5 -40 -381.5 -20 0 20 40 Temperature (°C) 60 80 100 INL (LSB) 76.3 DNL (LSB) 1 Delta (mV) Delta (LSB) NEGATIVE FULL-SCALE vs TEMPERATURE 4 3 2 1 0 -1 -2 -3 -4 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh Decimal Code Figure 13. 10 Figure 14. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 THEORY OF OPERATION The ADS8322 is a high-speed successive approximation register (SAR) A/D converter with an internal 2.5V bandgap reference that operates from a single +5V supply. The input is fully differential with a typical common-mode rejection of 70dB. The device accepts a differential analog input voltage in the range of –VREF to +VREF, centered on the common-mode voltage (see the Analog Input section). The device also accepts bipolar input ranges when a level shift circuit is used at the front end (see Figure 21). The basic operating circuit for the ADS8323 is shown in Figure 15. The ADS8323 requires an external clock to run the conversion process. This clock can vary between 25kHz (1.25kHz throughput) and 10MHz (500kSPS throughput). The duty cycle of the clock is unimportant as long as the minimum high and low times are at least 40ns and the clock period is at least 100ns. The minimum clock frequency is governed by the parasitic leakage of the Capacitive Digital-to-Analog Converter (CDAC) capacitors internal to the ADS8323. white space here +5V Analog Supply 10mF + 0.1mF 0.1mF + Analog Input 32 31 30 29 28 27 26 25 REFOUT REFIN NC NC +AVDD AGND +IN -IN - CS 24 1 DB15 2 DB14 BYTE 23 3 DB13 RD 22 4 DB12 CONVST 21 Chip Select Read Input Conversion Start ADS8322 +DVDD 18 8 DB8 BUSY 17 DB0 DB9 DB1 7 DB2 DGND 19 DB3 DB10 DB4 6 DB5 CLOCK 20 DB6 DB11 DB7 5 9 10 11 12 13 14 15 16 Clock Input Busy Output Figure 15. Typical Circuit Configuration Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 11 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com The analog input is provided to two input pins, +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. A conversion is initiated on the ADS8323 by bringing CONVST (pin 21) low for a minimum of 20ns. CONVST low places the sample-and-hold amplifier in the hold state and the conversion process is started. The BUSY output (pin 17) goes high when the conversion begins and stays high during the conversion. While a conversion is in progress, both inputs are disconnected from any internal function. When the conversion result is latched into the output register, the BUSY signal goes low. The data can be read from the parallel output bus following the conversion by bringing both RD and CS low. NOTE: This mode of operation is described in more detail in the Timing and Control section of this data sheet. SAMPLE-AND-HOLD SECTION The sample-and-hold on the ADS8323 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 16-bit resolution. The input bandwidth of the sample-and-hold is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the ADC even when the ADC is operated at its maximum throughput rate of 500kSPS. The typical small-signal bandwidth of the sample-and-hold amplifier is 20MHz. The typical aperture delay time, or the time it takes for the ADS8323 to switch from the sample to the hold mode following the negative edge of the CONVST signal, is 10ns. The average delta of repeated aperture delay values is typically 30ps (also known as aperture jitter). These specifications reflect the ability of the ADS8323 to capture ac input signals accurately at the exact same moment in time. REFERENCE If the internal reference is used, REFOUT (pin 32) should be directly connected to REFIN (pin 31); see Figure 15. The ADS8323 can operate, however, with an external reference in the range of 1.5V to 2.55V for a corresponding full-scale range of 3.0V to 5.1V. The internal reference of the ADS8323 is double-buffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to REFOUT (pin 32) (the internal reference can typically source or sink 10μA of current; compensation capacitance should be at least 0.1μF to minimize noise). If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8323: single-ended or differential, as shown in Figure 16 and Figure 17. When the input is single-ended, the –IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + VREF) and the (common-mode – VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 18). -VREF to +VREF peak-to-peak ADS8323 Common Voltage Single-Ended Input VREF peak-to-peak Common Voltage ADS8323 VREF peak-to-peak Differential Input Figure 16. Methods of Driving the ADS8323: Single-Ended or Differential 12 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 +IN CM + VREF +VREF CM Voltage -IN = CM Voltage -VREF t CM - VREF Single-Ended Inputs +IN CM + 1/2VREF +VREF CM Voltage CM - 1/2VREF -VREF -IN t Differential Inputs Common-Mode Voltage (Differential Mode) = Note: (+IN) + (-IN) , Common-Mode Voltage (Single-Ended Mode) = IN-. 2 The maximum differential voltage between +IN and –IN of the ADS8323 is VREF. See Figure 18 and Figure 19 for a further explanation of the common voltage range for single-ended and differential inputs. Figure 17. Using the ADS8323 in the Single-Ended and Differential Input Modes white space here 5 5 AVDD = 5V 4.55 AVDD = 5V 3 2.75 Single-Ended Input 2.25 2 1 4.025 4 3.8 Common Voltage Range (V) Common Voltage Range (V) 4 1.2 3 Differential Input 2 0.975 1 0.45 0 0 -1 -1 1.0 1.5 2.0 2.55 2.5 3.0 1.0 1.5 2.0 2.55 2.5 3.0 VREF (V) VREF (V) Figure 18. Single-Ended Input: Common-Mode Voltage Range vs VREF Figure 19. Differential Input: Common-Mode Voltage Range vs VREF Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 13 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com NOISE R1 Figure 20 shows the transition noise of the ADS8323. A low-level dc input was applied to the analog-input pins and the converter was put through 8192 conversions. The digital output of the ADC varies in output code due to the internal noise of the ADS8323. This characteristic is true for all 16-bit SAR-type ADCs. The ADS8323, with five output codes for the σ distribution, yields a greater than ±0.8LSB transition noise at 5V operation. Remember that to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be less than 50μV. 4kW Bipolar Input +IN (pin 26) OPA132 -IN (pin 25) ADS8323 R2 OPA353 BIPOLAR INPUT ±10V ±5V ±2.5V 5052 20kW R1 R2 1kW 2kW 4kW 5kW 10kW 20kW REFOUT (pin 32) 2.5V Figure 21. Level Shift Circuit for Bipolar Input Ranges 1968 54 0014 DIGITAL INTERFACE 818 TIMING AND CONTROL 0018 See the timing diagram and the Timing Characteristics section for detailed information on timing signals and the respective requirements for each. 300 0015 0016 0017 Code Figure 20. Histogram of 8,192 Conversions of a Low-Level DC Input AVERAGING Averaging the digital codes can compensate the noise of the ADC. By averaging conversion results, transition noise is reduced by a factor of 1/√n, where n is the number of averages. For example, averaging four conversion results reduces the transition noise by 1/2 to ±0.4LSB. Averaging should only be used for input signals with frequencies near dc. For ac signals, a digital filter can be used to low-pass filter and decimate the output codes. This process works in a similar manner to averaging—for every decimation by 2, the signal-to-noise ratio improves by 3dB. BIPOLAR INPUTS The differential inputs of the ADS8323 were designed to accept bipolar inputs (–VREF and +VREF) around the common-mode voltage, which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring four high-precision external resistors, the ADS8323 can be configured to accept bipolar inputs. The conventional ±2.5V, ±5V, and ±10V input ranges could be interfaced to the ADS8323 using the resistor values shown in Figure 21. 14 The ADS8323 uses an external clock (CLOCK, pin 20) that controls the conversion rate of the CDAC. With a 10MHz external clock, the ADC sampling rate is 500kSPS that corresponds to a 2μs maximum throughput time. Conversions are initiated by bringing the CONVST pin low for a minimum of 20ns (after the 20ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8322 switches from Sample-to-Hold mode on the falling edge of the CONVST command. Following the first rising edge of the external clock after a CONVST low, the ADS8322 begins conversion (this first rising edge of the external clock represents the start of clock cycle one; the ADS8322 requires 16 rising clock edges to complete a conversion). The BUSY output goes high immediately following CONVST going low. BUSY stays high through the conversion process and returns low when the conversion has ended. Both RD and CS can be high during and before a conversion (although CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 EXPLANATION OF CLOCK, BUSY AND BYTE PINS CLOCK: An external clock must be provided for the ADS8323. The maximum clock frequency is 10MHz and that provides 500kSPS throughput. The minimum clock frequency is 25kHz and that provides 1.25kHz throughput. The minimum clock cycle is 100ns (see Timing Diagram, tC1), and CLOCK must remain high (see Timing Diagram, tW1) or low (see Timing Diagram, tW2) for at least 40ns. BUSY: Initially, BUSY output is low. Reading data from output register or sampling the input analog signal does not affect the state of the BUSY signal. After the CONVST input goes low and conversion starts, a maximum of 25ns later the BUSY output goes high. That signal stays high during conversion and provides the status of the internal ADC to the DSP or μC. At the end of conversion, on the rising edge of the 17th clock cycle, new data from the internal ADC are latched into the output registers. The BUSY signal goes low a maximum of 25ns later (see Timing Diagram, tD4). BYTE: The output data appear as a full 16-bit word on DB15-DB0 (MSB-LSB or D15-D0) if BYTE is low. If there is only an 8-bit bus available on a board, the result may also be read on an 8-bit bus by using only DB7-DB0. In this case, two reads are necessary (see the timing diagram). The first, as before, leaving BYTE low and reading the eight least significant bits on DB7-DB0, then bringing BYTE high. When BYTE is high, the upper eight bits (D15-D8) appear on DB7-DB0. START OF A CONVERSION AND READING DATA By bringing the CONVST signal low, the input data are immediately placed in the hold mode (10ns), although CS must be low when CONVST goes low to initiate a conversion. The conversion follows with the next rising edge of CLOCK. If it is important to detect a hold command during a certain clock cycle, then the falling edge of the CONVST signal must occur at least 10ns before the rising edge of CLOCK (see Timing Diagram, tD1). The CONVST signal can remain low without initiating a new conversion. The CONVST signal must be high for at least 20ns (see Timing Diagram, tW4) before it is brought low again and CONVST must stay low for at least 20ns (see Timing Diagram, tW3). Once a CONVST signal goes low, further impulses of this signal are ignored until the conversion is finished or the device is reset. When the conversion is finished (after 16 clock cycles) the sampling switches close and sample the new value. The start of the next conversion must be delayed to allow the input capacitor of the ADS8323 to be fully charged. This delay time depends on the driving amplifier, but should be at least 400ns. To gain acquisition time, the falling edge of CONVST must take place just before the rising edge of CLOCK (see Timing Diagram, tD1). One conversion cycle requires 20 clock cycles. However, reading data during the conversion or on a falling hold edge may cause a loss in performance. Reading Data (RD, CS): In general, the data outputs are in 3-state. Both CS and RD must be low to enable these outputs. RD and CS must stay low together for at least 40ns (see Timing Diagram, tD7) before the output data is valid. RD must remain high for at least 20ns (see Timing Diagram, tW7) before bringing it back low for a subsequent read command. 16 clock-cycles after the start of a conversion (that is, the next rising edge of the clock after the falling edge of CONVST), the new data are latched into the output register and the reading process can start again. Refer to Table 1 for ideal output codes. CS being low tells the ADS8323 that the bus on the board is assigned to the ADS8323. If an ADC shares a bus with digital gates, there is a possibility that digital (high-frequency) noise could get coupled into the ADC. If the bus is just used by the ADS8323, CS can be hard-wired to ground. The output data should not be read 125ns prior to the falling edge of CONVST and 10ns after the falling edge. The ADS8323 output is in binary twos complement format (see Figure 22). Table 1. Ideal Input Voltages and Output Codes DESCRIPTION DIGITAL OUTPUT BINARY TWOS COMPLEMENT ANALOG VALUE Full-Scale Range 2 • VREF Least Significant Bit (LSB) 2 • VREF/65535 BINARY CODE HEX CODE +Full Scale +VREF – 1 LSB 0111 1111 1111 1111 7FFF Midscale 0V 0000 0000 0000 0000 0000 Midscale – 1 LSB 0V – 1 LSB 1111 1111 1111 1111 FFFF Zero –VREF 1000 0000 0000 0000 8000 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 15 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8323 circuitry. This consideration is particularly true if the CLOCK input is approaching the maximum throughput rate. As the ADS8323 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just before latching the output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, or nearby digital logic or high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. These errors can change if the external event changes in time with respect to the CLOCK input. 16 On average, the ADS8323 draws very little current from an external reference, as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1μF bypass capacitor is recommended from pin 31 directly to ground. The AGND and DGND pins should be connected to a clean ground point. In all cases, this point should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. As with the GND connections, VDD should be connected to a +5V power supply plane, or trace, that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8323 should be clean and well-bypassed. A 0.1μF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1μF to 10μF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. In some situations, additional bypassing may be required, such as a 100μF electrolytic capacitor, or even a Pi filter made up of inductors and capacitors all designed to essentially low-pass filter the +5V supply, removing the high-frequency noise. Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 ADS8323 www.ti.com SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 0111 1111 1111 1111 65535 0111 1111 1111 1110 65534 0111 1111 1111 1101 65533 0000 0000 0000 0001 32769 0000 0000 0000 0000 32768 1111 1111 1111 1111 32767 1000 0000 0000 0010 Step Digital Output Code Binary Twos Complement (BTC) 2 1000 0000 0000 0001 1 1000 0000 0000 0000 0 2.499962V VNFS = VCM - VREF = 0V 0.000038V 2.500038V VPFS = VCM + VREF = 5V VPFS Ð 1LSB = 4.999924V VBPZ = 2.5V 0.000076V 4.999848V Unipolar Analog Input Voltage 1LSB = 76mV 0.000152V VCM = 2.5V 16-BIT Bipolar Input, Binary Twos Complement Output: (BTC) Negative Full-Scale Code = VNFS = 8000h, Vcode = VCM - VREF Bipolar Zero Code = VBPZ = 0000h, Vcode = VCM Positive Full-Scale Code = VPFS = 7FFFh, Vcode = (VCM + VREF) - 1LSB VREF = 2.5V Figure 22. Ideal Conversion Characteristics (Condition: Single-Ended, VCM = IN– = 2.5V, VREF = 2.5V) Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 17 ADS8323 SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May, 2002) to Revision C Page • Updated document format to current standards ................................................................................................................... 1 • Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2 • Changed conversion time from 1.6μs (min) to 1.6μs (max) ................................................................................................. 3 • Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 3 • Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 7 18 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): ADS8323 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS8323Y/250 ACTIVE TQFP PBS 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8323Y/250G4 ACTIVE TQFP PBS 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8323Y/2K ACTIVE TQFP PBS 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8323Y/2KG4 ACTIVE TQFP PBS 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8323YB/250 ACTIVE TQFP PBS 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS8323YB/250G4 ACTIVE TQFP PBS 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8323Y/250 TQFP PBS 32 250 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 ADS8323Y/2K TQFP PBS 32 2000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 ADS8323YB/250 TQFP PBS 32 250 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8323Y/250 TQFP PBS ADS8323Y/2K TQFP PBS 32 250 367.0 367.0 38.0 32 2000 367.0 367.0 38.0 ADS8323YB/250 TQFP PBS 32 250 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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