® ADS ADS7845 784 5 TOUCH SCREEN CONTROLLER FEATURES DESCRIPTION ● 5-WIRE TOUCH SCREEN INTERFACE The ADS7845 is a 12-bit sampling analog-to-digital converter (ADC) with a synchronous serial interface and low on-resistance switches for driving touch screens. Typical power dissipation is 750µW at a 125kHz throughput rate and a +2.7V supply. The reference voltage (VREF) can be varied between 1V and +VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode which reduces typical power dissipation to under 0.5µW. The ADS7845 is guaranteed down to 2.7V operation. ● RATIOMETRIC CONVERSION ● SINGLE SUPPLY: 2V to 5V ● UP TO 125kHz CONVERSION RATE ● SERIAL INTERFACE ● PROGRAMMABLE 8- OR 12-BIT RESOLUTION ● AUXILIARY ANALOG INPUTS ● FULL POWER-DOWN CONTROL APPLICATIONS Low power, high speed, and on-board switches make the ADS7845 ideal for battery-operated systems such as personal digital assistants with resistive touch screens and other portable equipment. The ADS7845 is available in a 16-lead SSOP package and is guaranteed over the –40°C to +85°C temperature range. ● PERSONAL DIGITAL ASSISTANTS ● PORTABLE INSTRUMENTS ● POINT-OF-SALES TERMINALS ● PAGERS ● TOUCH-SCREEN MONITORS +VCC GND UR LR GND Driver +VCC SAR UL LL ADS7845 DOUT BUSY Comparator +VCC GND CDAC AUX IN Serial Data Interface and Control CS DCLK MUX WIPER DIN PENIRQ VREF International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1497A Printed in U.S.A. December, 1998 SPECIFICATIONS At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, fCLK = 16 • fSAMPLE = 2MHz, 12-bit mode, and digital inputs = GND or +VCC, unless otherwise noted. ADS7845E PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 12 ANALOG INPUT Full-Scale Input Span Absolute Input Range Positive Input - Negative Input Positive Input Negative Input 0 –0.2 –0.2 Capacitance Leakage Current Bits VREF +VCC +0.2 +0.2 25 0.1 SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Offset Error Gain Error Noise Power Supply Rejection Ratio SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Channel-to-Channel Isolation 11 ±2 ±6 ±4 30 70 12 REFERENCE INPUT Range Resistance Input Current Ω Ω +VCC 5 13 2.5 0.001 f SAMPLE = 12.5kHz CS = +VCC DIGITAL INPUT/OUTPUT Logic Family Logic Levels, Except PENIRQ VIH VIL VOH VOL PENIRQ VOL Data Format 7 7 1.0 CS = GND or +VCC Bits LSB(1) LSB LSB µVrms dB 500 30 100 100 125 VIN = 2.5Vp-p at 50kHz V V V pF µA Clk Cycles Clk Cycles kHz ns ns ps dB 3 SWITCH DRIVERS On-Resistance UL, UR LL, LR UNITS 40 3 V GΩ µA µA µA CMOS | IIH | ≤ +5µA | IIL | ≤ +5µA IOH = –250µA IOL = 250µA +VCC • 0.7 –0.3 +VCC • 0.8 +VCC +0.3 +0.8 TA = 0°C to +85°C, 100kΩ Pull-Up 0.4 V V V 0.8 V 5.5 650 3 V µA µA µA 1.8 mW +85 °C Straight Binary POWER SUPPLY REQUIREMENTS Specified Performance(2) +VCC Quiescent Current 2.7 280 220 f SAMPLE = 12.5kHz Shutdown Mode with DCLK = DIN = +VCC +VCC = +2.7V Power Dissipation TEMPERATURE RANGE Specified Performance –40 NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610µV. (2) ADS7845 will operate down to 2.0V. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7845 2 PIN CONFIGURATION PIN DESCRIPTION Top View SSOP PIN NAME DESCRIPTION 1 2 3 +VCC UL UR Power Supply, 2.0V to 5V. Upper Left Panel Driver (VCC ON/OFF) Upper Right Panel Driver (switch between VCC and GND) Lower Left Panel Driver (switch between GND and VCC) Lower Right Panel Driver (GND ON/OFF) Ground Panel Input Auxiliary Input Voltage Reference Input Power Supply, 2.0V to 5V. Pen Interrupt. Open anode output (requires 10kΩ to 100kΩ pull-up resistor externally). Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH. Busy Output. This output is high impedance when CS is HIGH. Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK. Chip Select Input. Controls conversion timing and enables the serial input/output register. External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. +VCC 1 16 DCLK UL 2 15 CS 4 LL UR 3 14 DIN LL 4 13 BUSY 5 6 7 8 9 10 11 LR GND WIPER AUXIN VREF +VCC PENIRQ 12 DOUT 13 BUSY 14 DIN 15 CS 16 DCLK ADS7845 LR 5 12 DOUT GND 6 11 PENIRQ WIPER 7 10 +VCC AUXIN 8 9 VREF ABSOLUTE MAXIMUM RATINGS(1) +VCC to GND ........................................................................ –0.3V to +6V Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V Digital Inputs to GND ............................................. –0.3V to +VCC + 0.3V Power Dissipation .......................................................................... 250mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C ELECTROSTATIC DISCHARGE SENSITIVITY NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ADS7845E " PACKAGE PACKAGE DRAWING NUMBER(1) SPECIFICATION TEMPERATURE RANGE ±2 16-Lead SSOP 322 –40°C to +85°C " " " " ORDERING NUMBER(2) TRANSPORT MEDIA ADS7845E ADS7845E/2K5 Rails Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ADS7845E/2K5” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® 3 ADS7845 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 400 140 350 120 Supply Current (nA) Supply Current (µA) SUPPLY CURRENT vs TEMPERATURE 300 250 200 100 80 60 40 150 20 100 –40 –20 0 20 40 60 80 –40 100 –20 0 SUPPLY CURRENT vs +VCC 40 80 100 MAXIMUM SAMPLE RATE vs +VCC 8-Bit Mode 350 Sample Rate (Hz) fCLOCK = 200kHz 300 VREF = +VCC 250 200 150 100k 12-Bit Mode 10k 100 VREF = +VCC 1k 50 1.5 2 2.5 3 3.5 4 4.5 5 1.5 2 2.5 3 3.5 4 4.5 5 +VCC (V) +VCC (V) CHANGE IN GAIN vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE 0.15 0.6 0.10 0.4 Delta from +25°C (LSB) Delta from +25°C (LSB) 60 1M 400 Supply Current (µA) 20 Temperature (°C) Temperature (°C) 0.05 0.00 –0.05 0.2 0.0 –0.2 –0.4 –0.10 –0.6 –0.15 –40 –20 0 20 40 60 80 –40 100 0 20 40 Temperature (°C) Temperature (°C) ® ADS7845 –20 4 60 80 100 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. REFERENCE CURRENT vs TEMPERATURE 18 12 16 Reference Current (µA) Reference Current (µA) REFERENCE CURRENT vs SAMPLE RATE 14 10 8 6 4 14 12 10 8 2 6 0 0 25 50 75 100 125 –40 0 20 40 60 80 Temperature (°C) SWITCH ON RESISTANCE vs +VCC (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) SWITCH ON RESISTANCE vs TEMPERATURE (X+, Y+: +VCC to Pin; X–, Y–: Pin to GND) 16 100 16 14 14 LL LR 12 RON (Ω) 10 8 LR LL 12 10 8 UR 6 UR UL UL 6 4 4 2 2 2 2.5 3 3.5 4 4.5 5 –40 0 –20 +VCC (V) 20 40 60 80 100 Temperature (°C) MAXIMUM SAMPLING RATE vs RIN 2 1.8 INL: R = 2kΩ INL: R = 500Ω DNL: R = 2kΩ DNL: R = 500Ω 1.6 1.4 LSB Error RON (Ω) –20 Sample Rate (kHz) 1.2 1 0.8 0.6 0.4 0.2 0 20 40 60 80 100 120 140 Sampling Rate (kHz) 160 180 200 ® 5 ADS7845 THEORY OF OPERATION differential input to the converter and a differential reference architecture, it is possible to negate the switch’s on-resistance error (should this be a source of error for the particular measurement). The ADS7845 is a classic Successive Approximation Register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6µs CMOS process. ANALOG INPUT Figure 2 shows a block diagram of the input multiplexer on the ADS7845, the differential input of the A/D converter, and the converter’s differential reference. Table I and Table II show the relationship between the A2, A1, A0, and SER/DFR control bits and the configuration of the ADS7845. The control bits are provided serially via the DIN pin—see the Digital Interface section of this data sheet for more details. The basic operation of the ADS7845 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.0V to 5.25V. The external reference can be any voltage between 1V and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS7845. When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (see Figure 2) is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate. The analog input to the converter is provided via the WIPER input. In the measurement mode, the lower right corner of the panel is connected to GND and the upper left corner is connected to VCC. When the lower left corner is connected to GND and the upper right corner is connected to VCC, a “Y” measurement is made. When the lower left corner is connected to VCC and the upper right corner is connected to GND, a “X” measurement is made. By maintaining a A2 A1 A0 DRV1 0 1 0 1 0 0 1 1 1 1 0 0 ON DRV2 AUXIN INTERRUPT –IN(1) X POSITION Y POSITION +REF(1) –REF(1) DOUT GND GND GND GND OFF ON OFF OFF ON OFF OFF OFF +VREF +VREF +VREF +VREF GND GND GND GND ON ON NOTE: (1) Internal node, for clarification only—not directly accessible by the user. TABLE I. Input Configuration—Single-Ended Reference Mode (SER/DFR HIGH). A2 A1 A0 DRV1 0 1 0 1 0 0 1 1 1 1 0 0 ON DRV2 AUXIN INTERRUPT –IN(1) X SWITCHES Y SWITCHES +REF(1) –REF(1) DOUT LR LR GND GND OFF ON OFF OFF ON OFF OFF OFF UL UL +VREF +VREF LR LR GND GND ON ON NOTE: (1) Internal node, for clarification only—not directly accessible by the user. TABLE II. Input Configuration—Differential Reference Mode (SER/DFR LOW). +2.7V to +5V 1µF + to 10µF (Optional) 0.1µF ADS7845 DCLK 16 Serial/Conversion Clock 1 +VCC 2 UL 3 UR 4 LL BUSY 13 Converter Status 5 LR DOUT 12 Serial Data Out 6 GND 7 WIPER +VCC 10 8 AUXIN VREF CS 15 DIN 14 PENIRQ 11 Chip Select Serial Data In Pen Interrupt WIPER Auxiliary Input 0.1µF FIGURE 1. Basic Operation of the ADS7845. ® ADS7845 6 100kΩ (optional) 9 External reference required with auxiliary input. Otherwise, NC in differential mode or VCC or external VREF in single-ended mode. +VCC PENIRQ VREF UR SER/DFR (Shown LOW) UL WIPER +IN +REF Drivers A/D CONVERTER AUXIN –IN –REF LL LR GND FIGURE 2. Simplified Diagram of ADS7845 Input and Panel Drivers. REFERENCE INPUT There is also a critical item regarding the reference when making measurements where the switch drivers are on. For this discussion, it’s useful to consider the basic operation of the ADS7845 as shown in Figure 1. This particular application shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made with the WIPER input to the A/D converter, turning on the UL and UR drivers to V CC, grounding LL and LR, and digitizing the voltage on the WIPER (see Figure 3 for a block diagram). The voltage difference between +REF and –REF (see Figure 2) sets the analog input range. The ADS7845 will operate with a reference in the range of 1V to +VCC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2 LSBs with a 2.5V reference, it will typically be 5 LSBs with a 1V reference. In each case, the actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a low-noise reference, and a low-noise input signal. +VCC GND UL UR VREF HI WIPER A/D Converter INLOW The voltage into the VREF input is not buffered and directly drives the capacitor digital-to-analog converter (CDAC) portion of the ADS7845. Typically, the input current is 13µA with VREF = 2.5V and fSAMPLE = 125kHz. This value will vary by a few microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. VREF LO LL LR GND GND +VCC GND FIGURE 3. Simplified Diagram of Single-Ended Reference (SER/DFR HIGH). ® 7 ADS7845 processor and the converter consists of 8 clock cycles. One complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the DCLK input. Under the situation outlined so far, it would not be possible to achieve a zero volt input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. The first 8 clock cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer, switches, and reference inputs appropriately, the converter enters the acquisition (sample) mode and, if needed, the internal switches are turned on. After three more clock cycles, the control byte is complete and the converter enters the conversion mode. At this point, the input sample/hold goes into the hold mode and the internal switches may turn off. The next 12 clock cycles accomplish the actual analog-to-digital conversion. If the conversion is ratiometric (SER/DFR LOW), the internal switches are on during the conversion. A 13th clock cycle is needed for the last bit of the conversion result. Three more clock cycles are needed to complete the last byte (DOUT will be LOW). These will be ignored by the converter. This situation can be remedied as shown in Figure 4. By setting the SER/DFR bit LOW, the +REF and –REF inputs are connected directly to Y+ and Y–. This makes the analogto-digital conversion ratiometric. The result of the conversion is always a percentage of the external resistance, regardless of how it changes in relation to the on-resistance of the internal switches. NOTE: There is an important consideration regarding power dissipation when using the ratiometric mode of operation. See the Power Dissipation section for more details. GND +VCC Control Byte UL Also shown in Figure 5 is the placement and order of the control bits within the control byte. Tables III and IV give detailed information about these bits. The first bit, the ‘S’ bit, must always be HIGH and indicates the start of the control byte. The ADS7845 will ignore inputs on the DIN pin until the start bit is detected. The next three bits (A2 - A0) select the active panel drivers (see Tables I and II and Figure 2). The MODE bit determines the number of bits for each conversion, either 12 bits (LOW) or 8 bits (HIGH). UR VREF HI +VCC WIPER A/D Converter INLO VREF LO LL LR The SER/DFR bit controls the reference mode: either singleended (HIGH) or differential (LOW). (The differential mode is also referred to as the ratiometric conversion mode.) In GND GND +VCC GND FIGURE 4. Simplified Diagram of Differential Reference (SER/DFR LOW). BIT 7 (MSB) BIT 6 BIT 5 BIT 4 S A2 A1 A0 BIT 2 MODE SER/DFR BIT 1 BIT 0 (LSB) PD1 PD0 TABLE III. Order of the Control Bits in the Control Byte. As a final note about the differential reference mode, it must be used with +VCC as the source of the +REF voltage and cannot be used with VREF. It is possible to use a high precision reference on VREF and single-ended reference mode for measurements which do not need to be ratiometric. Or, in some cases, it could be possible to power the converter directly from a precision reference. Most references can provide enough power for the ADS7845, but they might not be able to supply enough current for the external load (such as a resistive touch screen). BIT 7 NAME Figure 5 shows the typical operation of the ADS7845’s digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface. Each communication between the DESCRIPTION S Start Bit. Control byte starts with first HIGH bit on DIN. A new control byte can start every 15th clock cycle in 12-bit conversion mode or every 11th clock cycle in 8-bit conversion mode. 6-4 A2 - A0 Channel Select Bits. Along with the SER/DFR bit, these bits control the setting of the multiplexer input, switches, and reference inputs, as detailed in Tables I and II. 3 MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls the number of bits for the following conversion: 12 bits (LOW) or 8 bits (HIGH). 2 SER/DFR Single-Ended/Differential Reference Select Bit. Along with bits A2 - A0, this bit controls the setting of the multiplexer input, switches, and reference inputs, as detailed in Tables I and II. PD1 - PD0 Power-Down Mode Select Bits. See Table V for details. DIGITAL INTERFACE 1-0 TABLE IV. Descriptions of the Control Bits within the Control Byte. ® ADS7845 BIT 3 8 single-ended mode, the converter’s reference voltage is always the difference between the VREF and GND pins. In differential mode, the reference voltage is the difference between the currently enabled switches. See Tables I and II and Figures 2 through 4 for more information. The last two bits (PD1 - PD0) select the power- down mode as shown in Table V. If both inputs are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid. There are two power-down modes: one where PENIRQ is disabled and one where it is enabled. PD1 PD0 PENIRQ DESCRIPTION 0 0 Enabled Power-down between conversions. When each conversion is finished, the converter enters a LOW power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid. The LR– switch is on while in power-down. 0 1 Disabled Same as mode 00, except PENIRQ is disabled. The LR– switch is off while in power-down mode. 1 0 Disabled Reserved for future use. 1 1 Disabled No power down between conversions, device is always powered. TABLE V. Power-Down Selection. CS tACQ DCLK DIN 1 S 8 A2 A1 8 1 1 8 A0 MODE SER/ DFR PD1 PD0 (START) Idle Acquire Conversion Idle BUSY DOUT 11 10 9 8 7 6 5 4 3 2 (MSB) DRIVERS 1 AND 2(1) (SER/DFR HIGH) DRIVERS 1 AND 2(1, 2) (SER/DFR LOW) OFF 1 0 Zero Filled... (LSB) ON OFF OFF ON OFF NOTES: (1) For Y Position, Driver 1 is ON and Driver 2 is OFF. For X Position, Driver 1 is OFF and Driver 2 is ON. LR will turn on when power-down mode is entered and PD1, PD0 = 00B. (2) Drivers will remain on if power-down mode is 11B (no power down) until selected input channel, reference mode, or power-down mode is changed, or CS is HIGH. FIGURE 5. Conversion Timing, 24 Clocks per Conversion, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port. CS DCLK 1 DIN 8 1 8 S 1 8 1 S CONTROL BITS CONTROL BITS BUSY DOUT 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 FIGURE 6. Conversion Timing, 16 Clocks per Conversion, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port. ® 9 ADS7845 16 Clocks per Conversion Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs). This effectively increases the maximum conversion rate of the converter beyond the values given in the Specification table, which assume 16 clock cycles per conversion. The control bits for conversion n+1 can be overlapped with conversion ‘n’ to allow for a conversion every 16 clock cycles, as shown in Figure 6. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter. This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the input sample/hold may droop enough to affect the conversion result. Note that the ADS7845 is fully powered while other serial communications are taking place during a conversion. SYMBOL DESCRIPTION MIN tACQ Acquisition Time 1.5 TYP MAX UNITS tDS DIN Valid Prior to DCLK Rising 100 ns tDH DIN Hold After DCLK HIGH 10 ns µs tDO DCLK Falling to DOUT Valid 200 ns tDV CS Falling to DOUT Enabled 200 ns tTR CS Rising to DOUT Disabled Digital Timing tCSS CS Falling to First DCLK Rising Figure 7 and Table VI provide detailed timing for the digital interface of the ADS7845. tCSH CS Rising to DCLK Ignored 0 ns tCH DCLK HIGH 200 ns tCL DCLK LOW 200 15 Clocks per Conversion tBD DCLK Falling to BUSY Rising 200 ns tBDV CS Falling to BUSY Enabled 200 ns tBTR CS Rising to BUSY Disabled 200 ns Figure 8 provides the fastest way to clock the ADS7845. This method will not work with the serial interface of most microcontrollers and digital signal processors as they are generally not capable of providing 15 clock cycles per serial transfer. However, this method could be used with Field 200 ns 100 ns ns TABLE VI. Timing Specifications (+VCC = +2.7V and Above, TA = –40°C to +85°C, CLOAD = 50pF). CS tCSS tCL tCH tBD tBD tCSH tD0 DCLK tDS tDH DIN PD0 tBDV tBTR BUSY tDV tTR DOUT 11 10 FIGURE 7. Detailed Timing Diagram. CS DCLK 15 1 DIN S A2 A1 A0 MODE SGL/ DIF PD1 PD0 1 S 15 A2 A1 A0 MODE SGL/ DIF PD1 PD0 1 S A2 5 4 A1 A0 BUSY DOUT 11 10 9 8 7 6 5 4 FIGURE 8. Maximum Conversion Rate, 15 Clocks per Conversion. ® ADS7845 10 3 2 1 0 11 10 9 8 7 6 3 2 Data Format Figure 10 shows the difference between reducing the DCLK frequency (“scaling” DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversions per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active). The ADS7845 output data is in Straight Binary format as shown in Figure 9. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. FS = Full-Scale Voltage = VREF(1) 1 LSB = VREF(1)/4096 1 LSB 1000 11...111 fCLK = 16 • fSAMPLE 11...101 Supply Current (µA) Output Code 11...110 00...010 00...001 100 fCLK = 2MHz 10 00...000 TA = 25°C +VCC = +2.7V 0V FS – 1 LSB 1 1k Input Voltage(2) (V) 10k 100k 1M fSAMPLE (Hz) NOTES: (1) Reference voltage at converter: +REF–(–REF). See Figure 2. (2) Input voltage at converter, after multiplexer: +IN–(–IN). See Figure 2 FIGURE 10. Supply Current vs Directly Scaling the Frequency of DCLK with Sample Rate or Keeping DCLK at the Maximum Possible Frequency. FIGURE 9. Ideal Input Voltages and Output Codes. 8-Bit Conversion Another important consideration for power dissipation is the reference mode of the converter. In the single-ended reference mode, the converter’s internal switches are on only when the analog input voltage is being acquired (see Figure 5). Thus, the external device, such as a resistive touch screen, is only powered during the acquisition period. In the differential reference mode, the external device must be powered throughout the acquisition and conversion periods (see Figure 5). If the conversion rate is high, this could substantially increase power dissipation. The ADS7845 provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. This could be used in conjunction with serial interfaces that provide 12bit transfers or two conversions could be accomplished with three 8-bit transfers. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actually occur at a faster clock rate. This is because the internal settling time of the ADS7845 is not as critical— settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate. LAYOUT The following layout suggestions should provide the most optimum performance from the ADS7845. However, many portable applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable devices have fairly “clean” power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter’s power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully. POWER DISSIPATION There are two major power modes for the ADS7845: full power (PD1 - PD0 = 11B) and auto power-down (PD1 - PD0 = 00B). When operating at full speed and 16-clocks per conversion (as shown in Figure 6), the ADS7845 spends most of its time acquiring or converting. There is little time for auto powerdown, assuming that this mode is active. Therefore, the difference between full power mode and auto power-down is negligible. If the conversion rate is decreased by simply slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion but conversions are simply done less often, the difference between the two modes is dramatic. For optimum performance, care should be taken with the physical layout of the ADS7845 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an ‘n-bit’ SAR converter, there are n ‘windows’ in which ® 11 ADS7845 PENIRQ Output large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input. The pen interrupt output function is detailed in Figure 11. By connecting a pull-up resistor to VCC (typically 100kΩ), the PENIRQ output is HIGH. While in the power-down mode, with PD0 = PD1 = 0, the lower-right panel corner is connected to GND and the PENIRQ output is connected to the WIPER input. When the panel is touched, the PENIRQ output goes LOW, due to the current path through the panel to GND, initiating an interrupt to the processor. During the measurement cycles for X and Y position, the PENIRQ output diode will be internally connected to GND and the WIPER disconnected from the PENIRQ diode to eliminate any leakage current from the pull-up resistor to flow through the WIPER, thus causing no errors. With this in mind, power to the ADS7845 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1µF to 10µF capacitor may also be needed if the impedance of the connection between +VCC and the power supply is high. The reference should be similarly bypassed with a 0.1µF capacitor. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation. The ADS7845 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion). In addition, when the DIN has selected A2 = 1, A1 = 1, A0 = 0, and the ADS7845 is commanded into the powerdown mode (PD0 and PD1 = 0) and CS is LOW (when CS is HI, the DOUT line is high impedance), the DOUT will be LOW (all “0”s) during no touch and HI (all “1”s) when the panel is touched. This feature eliminates the need for an additional port to detect panel touch. Since all panels have end resistance, all “0”s and all “1”s are an unused set of codes. The ADS7845 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power supply entry or battery connection point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. OFF UL UR +VCC 100kΩ PENIRQ WIPER LL In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections will be a source of error, much like the on-resistance of the internal switches. Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations. LR OFF ON UR, LL Driver FIGURE 11. PENIRQ Functional Block Diagram. ® ADS7845 OFF 12