ADS7864 ADS 786 4 500kHz, 12-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● ● The ADS7864 is a dual 12-bit, 500kHz Analog-toDigital (A/D) converter with 6 fully differential input channels grouped into three pairs for high speed simultaneous signal acquisition. Inputs to the sample-andhold amplifiers are fully differential and are maintained differential to the input of the A/D converter. This provides excellent common-mode rejection of 80dB at 50kHz which is important in high noise environments. The ADS7864 offers a parallel interface and control inputs to minimize software overhead. The output data for each channel is available as a 16-bit word (address and data). The ADS7864 is offered in a TQFP-48 package and is fully specified over the –40°C to +85°C operating range. 6 SIMULTANEOUS SAMPLING CHANNELS FULLY DIFFERENTIAL INPUTS 2µs TOTAL THROUGHPUT PER CHANNEL GUARANTEED NO MISSING CODES PARALLEL INTERFACE 1MHz EFFECTIVE SAMPLING RATE LOW POWER: 50mW 6X FIFO APPLICATIONS ● MOTOR CONTROL ● MULTI-AXIS POSITIONING SYSTEMS ● 3-PHASE POWER CONTROL HOLDA CH A0+ CH A0– HOLDB SAR S/H Amp CH B0+ COMP CH B0– S/H Amp HOLDC Interface A2 CDAC A1 CH C1+ CH C1– S/H Amp A0 Conversion and Control MUX BYTE CLOCK REFIN CS RD Internal 2.5V Reference REFOUT BUSY RESET FIFO Registers CH A1+ CH A1– Channel/ Data Output COMP S/H Amp CDAC CH B1+ CH B1– 16 S/H Amp CH C1+ CH C1– S/H Amp MUX SAR International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 http://www.burr-brown.com/ http://www.ti.com/ ® Copyright © 2000, Texas Instruments Incorporated SBAS141 PDS-1581A 1 Printed in U.S.A. September, 2000 ADS7864 SPECIFICATIONS All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. ADS7864Y PARAMETER CONDITIONS MIN TYP RESOLUTION ADS7864YB MAX MIN TYP 12 ANALOG INPUT Input Voltage Range-Bipolar Absolute Input Range Input Capacitance Input Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Integral Linearity Match Differential Linearity Bipolar Offset Error Bipolar Offset Error Match Positive Gain Error Positive Gain Error Match Negative Gain Error Negative Gain Error Match Common-Mode Rejection Ratio VCENTER = +2.5V +IN –IN –VREF –0.3 –0.3 Referenced to REFIN Referenced to REFIN ±0.15 Referenced to REFIN ±0.15 At DC VIN = ±1.25Vp-p at 50kHz 84 80 120 0.3 POWER SUPPLY REQUIREMENTS Power Supply Voltage, +VA, +VD Quiescent Current, +VA, +VD Power Dissipation ✻ ±4 3 ±0.75 3 ±0.75 3 2.475 1.2 ±0.1 ✻ ✻ ✻ ✻ Bits ✻ V V V pF µA ±1 ±3 ✻ ±0.5 ✻ ±0.5 ✻ ✻ Bits LSB LSB LSB LSB LSB % of FSR LSB % of FSR LSB dB dB µVrms LSB 3.5 100 50 40 ✻ ✻ ✻ ✻ µs µs kHz ns ps ps MHz –75 71 78 –76 ✻ ✻ ✻ ✻ dB dB dB dB ✻ ✻ ✻ 2.5 10 50 2 0.005 80 2.5 2.525 ✻ 2.6 100 ✻ +VD + 0.3 0.8 ✻ ✻ ✻ 0.4 0.2 8 Binary Two’s Complement ✻ 4.75 ✻ 5 ✻ ✻ ✻ V ppm/°C µVp-p mA mV/µA dB V µA pF ✻ CMOS 3.0 –0.3 3.5 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 5 IIH = +5µA IIL = +5µA IOH = –500µA IOL = –500µA ±0.5 ✻ ±0.4 ±0.5 ±0.1 2 500 VOLTAGE REFERENCE Internal Reference Voltage Internal Drift Internal Noise Internal Source Current Internal Load Rejection Internal PSRR External Reference Voltage Range Input Current Input Capacitance DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL External Clock Data Format ±2 1.75 0.25 VIN = ±2.5Vp-p at 100kHz VIN = ±2.5Vp-p at 100kHz VIN = ±2.5Vp-p at 100kHz VIN = ±2.5Vp-p at 50kHz ✻ ✻ ±0.75 0.5 ±0.6 ±0.75 –0.9 UNITS ✻ ✻ 12 SAMPLING DYNAMICS Conversion Time per A/D Acquisition Time Throughput Rate Aperture Delay Aperture Delay Matching Aperture Jitter Small-Signal Bandwidth ✻ 15 ±1 CLK = GND Noise Power Supply Rejection Ratio DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range Channel-to-Channel Isolation +VREF +VA + 0.3 +VA + 0.3 MAX 5.25 10 50 ✻ ✻ ✻ ✻ V V V V MHz ✻ ✻ ✻ V mA mW ✻ ✻ ✻ Specifications same as ADS7864Y. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7864 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+VD + 0.3V) REFIN ............................. –0.3V to (+VD + 0.3V) Digital Inputs to DGND .......................................... –0.3V to (+VD + 0.3V) Ground Voltage Differences: AGND, DGND ................................... ±0.3V +VD to AGND ......................... –0.3V to +6V Power Dissipation .......................................................................... 325mW Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT ADS7864Y " ADS7864YB " MINIMUM RELATIVE ACCURACY (LSB) MAXIMUM GAIN ERROR (%) SPECIFICATION TEMPERATURE RANGE ±2 " ±1 " ±0.75 " ±0.5 " –40°C to +85°C " –40°C to +85°C " PACKAGE PACKAGE DRAWING NUMBER ORDERING NUMBER (1) TQFP-48 " TQFP-48 " 355 " 355 " ADS7864Y/250 ADS7864Y/2K ADS7864YB/250 ADS7864YB/2K TRANSPORT MEDIA Tape Tape Tape Tape and and and and Reel Reel Reel Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “ADS7864Y/2K” will get a single 2000-piece Tape and Reel. 42 41 CH A0– CH B0+ CH B0– CH C0+ CH C0– CH C1– CH C1+ 40 39 38 37 CH A1– 43 CH A1+ 44 CH B1– 45 CH B1+ 46 +VA 36 AGND 35 DB15 REFIN 34 DB14 REFOUT 33 5 DB13 RESET 32 6 DB12 A0 31 1 +VA 2 AGND 3 4 0.1µF 0.1µF + 10µF +5V Analog Power Supply Global Reset ADS7864Y 7 DB11 A1 30 8 DB10 A2 29 DB6 HOLDC 25 CS 12 RD 26 CLOCK HOLDB +VD DB7 DGND 11 BUSY 27 DB0 28 HOLDA DB1 BYTE DB8 DB2 DB9 DB3 9 10 DB4 13 14 15 16 17 18 19 20 21 22 23 24 Address Select Sample and Hold Inputs +5V Digital Power Supply Read Input Chip Select Data Ouput Clock Input 0.1µF BUSY Output 10µF + 47 DB5 +5V Analog Power Supply 48 CH A0+ BASIC OPERATION + 10µF DGND AGND ® 3 ADS7864 PIN CONFIGURATION CH A0+ CH A0– CH B0+ CH B0– CH C0+ CH C0– CH C1– CH C1+ CH B1– CH B1+ CH A1– CH A1+ Top View 48 47 46 45 44 43 42 41 40 39 38 37 +VA 1 36 +VA AGND 2 35 AGND DB15 3 34 REFIN DB14 4 33 REFOUT DB13 5 32 RESET DB12 6 31 A0 ADS7864 DB11 7 30 A1 DB10 8 29 A2 DB9 9 28 BYTE 13 14 15 16 17 18 19 20 21 22 23 24 DB0 BUSY DGND +VD CLOCK RD CS 25 HOLDC DB1 DB6 12 DB2 26 HOLDB DB3 DB7 11 DB4 27 HOLDA DB5 DB8 10 PIN DESCRIPTIONS DESCRIPTION PIN NAME DESCRIPTION Analog Power Supply. Normally +5V. 25 HOLDC Places Channels C0 and C1 in hold mode. AGND Analog Ground 26 HOLDB Places Channels B0 and B1 in hold mode. DB15 Data Valid Output: “1” for data valid; “0” for invalid data. 27 HOLDA 28 BYTE PIN NAME 1 +VA 2 3 Places Channels A0 and A1 in hold mode. 2 x 8 Output Capability. Active HIGH 4 DB14 Channel Address Output Pin (see channel truth table) 29 A2 A2 Address/Mode Select Pin (see Address/Mode Truth table). 5 DB13 Channel Address Output Pin (see channel truth table) 30 A1 A1 Address/Mode Select Pin (see Address/Mode Truth Table). 6 DB12 Channel Address Output Pin (see channel truth table) 31 A0 A0 Address/Mode Select Pin (see Address/Mode Truth Table). 7 DB11 Data Bit 11 - MSB 8 DB10 Data Bit 10 9 DB9 Data Bit 9 10 DB8 Data Bit 8 11 DB7 Data Bit 7 12 DB6 Data Bit 6 13 DB5 Data Bit 5 14 DB4 Data Bit 4 15 DB3 Data Bit 3 16 DB2 Data Bit 2 17 DB1 Data Bit 1 18 DB0 Data Bit 0 - LSB 19 BUSY Low when a conversion is in progress. 20 DGND Digital Ground 21 +VD 22 CLOCK Digital Power Supply, +5VDC An external clock must be applied to the CLOCK input. 23 RD RD Input. Enables the parallel output when used in conjunction with chip select. 24 CS Chip Select ® ADS7864 4 32 RESET 33 REFOUT Reset Pin 34 REFIN 35 AGND 36 +VA 37 CH A1+ 38 CH A1– Inverting Input Channel A1 39 CH B1+ Noninverting Input Channel B1 40 CH B1– Inverting Input Channel B1 41 CH C1+ Noninverting Input Channel C1 42 CH C1– Inverting Input Channel C1 43 CH C0– Inverting Input Channel C0 44 CH C0+ Noninverting Input Channel C0 Reference Out Reference In Analog Ground Analog Power Supply. Normally +5V. Noninverting Input Channel A1 45 CH B0– Inverting Input Channel B0 46 CH B0+ Noninverting Input Channel B0 47 CH A0– Inverting Input Channel A0 48 CH A0+ Noninverting Input Channel A0 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 199.9kHz, –0.2dB) 0 0 –20 –20 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 99.9kHz, –0.2dB) –40 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 62.5 125 187.5 250 0 62.5 125 Frequency (kHz) SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY 75 1.0 SNR Delta from +25°C (dB) SNR and SINAD (dB) 250 CHANGE IN SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 70 SINAD 65 60 55 0.6 0.2 SNR –0.2 SINAD –0.6 50 1k 10k 100k –1.0 –40 1M 0 20 40 60 Temperature (°C) CHANGE IN SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE POSITIVE GAIN MATCH vs TEMPERATURE (Maximum Deviation for All Six Channels) 1.0 80 1.80 THD 0.5 0.0 SFDR –0.5 –1.0 –40 –20 Input Frequency (Hz) Change in Positive Gain Match (LSB) THD and SFDR Delta from +25°C (dB) 187.5 Frequency (kHz) –20 0 20 40 60 1.70 1.60 1.50 1.40 1.30 1.20 –40 80 Temperature (°C) –20 0 20 40 60 80 Temperature (°C) ® 5 ADS7864 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. REFERENCE VOLTAGE vs TEMPERATURE 1.50 2.510 1.40 2.506 Reference (V) Change in Negative Gain Match (LSB) NEGATIVE GAIN MATCH vs TEMPERATURE (Maximum Deviation for All Six Channels) 1.30 1.20 1.10 2.502 2.498 2.494 1.00 –40 –20 0 20 40 60 2.490 –40 80 –20 0 Temperature (°C) 1.0 1.20 Bipolar Match (LSB) Bipolar Zero (LSB) 1.30 CH1 CH0 0.6 0.4 –40 –20 0 20 40 60 80 60 1.10 1.00 0.90 –40 80 –20 0 20 40 60 80 Temperature (°C) Temperature (°C) DIFFERENTIAL LINEARITY ERROR vs CODE INTEGRAL LINEARITY ERROR vs CODE 1 2.0 Typical of All Six Channels Typical of All Six Channels 0.75 1.5 0.5 1.0 0.25 0.5 ILE (LSB) DLE (LSB) 40 BIPOLAR ZERO MATCH vs TEMPERATURE BIPOLAR ZERO vs TEMPERATURE 1.2 0.8 20 Temperature (°C) 0 –0.25 0 –0.5 –0.5 –1.0 –0.75 –1.5 –1 800 000 –2.0 800 7FF Hex BTC Code ® ADS7864 000 Hex BTC Code 6 7FF TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted. INTEGRAL LINEARITY ERROR MATCH vs TEMPERATURE Channel A0/Channel C1 (Different Converter, Different Channels) INTEGRAL LINEARITY ERROR vs TEMPERATURE 2.0 –0.02 1.6 1.2 –0.03 Positive ILE ILE Match (LSB) 0.8 ILE (LSB) –0.04 –0.05 0.4 0 –0.4 Negative ILE –0.8 –0.06 –1.2 –0.07 –1.6 –0.08 –40 –20 0 20 40 60 –2.0 –40 80 40 60 80 1.0 0.8 0.8 0.6 Positive DLE 0.6 0.4 0.4 0.2 ILE (LSB) DLE (LSB) 20 INTEGRAL LINEARITY ERROR MATCH vs CODE Channel A0/Channel B0 (Same Converter, Different Channels) DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0 –0.2 –0.8 –40 0.2 0 –0.2 –0.4 Negative DLE –0.6 –0.6 –0.8 –20 0 20 40 60 –1.0 800 80 Temperature (°C) 000 7FF Hex BTC Code INTEGRAL LINEARITY ERROR MATCH vs CODE Channel A0/Channel B1 (Different Converter, Different Channels) CHANNEL SEPARATION 1.0 –65 0.75 –70 0.5 –75 0.25 –80 dB ILE (LSB) 0 Temperature (°C) Temperature (°C) –0.4 –20 0 –85 –0.25 –0.5 –90 –0.75 –95 –1.0 800 –100 000 7FF 1k Hex BTC Code 10k 100k fIN (Hz) ® 7 ADS7864 INTRODUCTION REFERENCE Under normal operation, the REFOUT pin (pin 2) should be directly connected to the REFIN pin (pin 1) to provide an internal +2.5V reference to the ADS7864. The ADS7864 can operate, however, with an external reference in the range of 1.2V to 2.6V for a corresponding full-scale range of 2.4V to 5.2V. The ADS7864 is a high speed, low power, dual 12-bit A/D converter that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains dual 2µs successive approximation ADCs, six differential sample-and-hold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins and a high speed parallel interface. There are six analog inputs that are grouped into three channels (A, B and C). Each A/D converter has three inputs (A0/A1, B0/B1 and C0/ C1) that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. Each pair of channels has a hold signal (HOLDA, HOLDB, HOLDC) to allow simultaneous sampling on all 6 channels. The part accepts an analog input voltage in the range of –VREF to +VREF, centered around the internal +2.5V reference. The part will also accept bipolar input ranges when a level shift circuit is used at the front end (see Figure 7). The internal reference of the ADS7864 is double-buffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to pin 33 (the internal reference can typically source 2mA of current—load capacitance should not exceed 100pF). If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of both CDACs during conversion. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS7864: single-ended or differential (see Figures 1 and 2). When the input is single-ended, the –IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode +VREF) and the (common-mode –VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 3). A conversion is initiated on the ADS7864 by bringing the HOLDX pin LOW for a minimum of 15ns. HOLDX LOW places both sample-and-hold amplifiers of the X channels in the hold state simultaneously and the conversion process is started on both channels. The BUSY output will then go LOW and remain LOW for the duration of the conversion cycle. The data can be read from the parallel output bus following the conversion by bringing both RD and CS LOW. When the input is differential, the amplitude of the input is the difference between the +IN and –IN input, or: (+IN) – (–IN). The peak-to-peak amplitude of each input is ±1/2VREF around this common voltage. However, since the inputs are 180° out of phase, the peak-to-peak amplitude of the differential voltage is +VREF to –VREF. The value of VREF also determines the range of the voltage that may be common to both inputs (see Figure 4). Conversion time for the ADS7864 is 1.75µs when an 8MHz external clock is used. The corresponding acquisition time is 0.25µs. To achieve maximum output rate (500kHz), the read function can be performed during at the start of the next conversion. NOTE: This mode of operation is described in more detail in the Timing and Control section of this data sheet. SAMPLE-AND-HOLD SECTION The sample-and-hold amplifiers on the ADS7864 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the sample-and-hold is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the ADC even when the ADC is operated at its maximum throughput rate of 500kHz. The typical small-signal bandwidth of the sampleand-hold amplifiers is 40MHz. –VREF to +VREF peak-to-peak ADS7864 Common Voltage Single-Ended Input VREF peak-to-peak Typical aperture delay time or the time it takes for the ADS7864 to switch from the sample to the hold mode following the negative edge of HOLDX signal is 5ns. The average delta of repeated aperture delay values is typically 50ps (also known as aperture jitter). These specifications reflect the ability of the ADS7864 to capture AC input signals accurately at the exact same moment in time. Common Voltage ADS7864 VREF peak-to-peak Differential Input FIGURE 1. Methods of Driving the ADS7864 Single-Ended or Differential. ® ADS7864 8 +IN CM +VREF +VREF CM Voltage –IN = CM Voltage –VREF t CM –VREF CM +1/2VREF Single-Ended Inputs +IN +VREF CM Voltage –VREF CM –1/2VREF –IN t Differential Inputs NOTES: Common-Mode Voltage (Differential Mode) = (IN+) + (IN–) , Common-Mode Voltage (Single-Ended Mode) = IN–. 2 The maximum differential voltage between +IN and –IN of the ADS7864 is VREF. See Figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs. FIGURE 2. Using the ADS7864 in the Single-Ended and Differential Input Modes. 5 5 VCC = 5V 4.7 VCC = 5V 4.1 4 4 3 Common Voltage Range (V) Common Voltage Range (V) 4.05 2.7 Single-Ended Input 2.3 2 1 0.9 0 Differential Input 2 0.90 1 0.3 0 –1 1.0 3 –1 1.2 1.5 2.0 2.5 2.6 3.0 1.0 VREF (V) 1.2 1.5 2.0 2.5 2.6 3.0 VREF (V) FIGURE 3. Single-Ended Input: Common-Mode Voltage Range vs VREF. FIGURE 4. Differential Input: Common-Mode Voltage Range vs VREF. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Otherwise, this may result in offset error, which will change with both temperature and input voltage. capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (15pF) to a 12-bit settling level within 2 clock cycles. When the converter goes into the hold mode, the input impedance is greater than 1GΩ. The input current on the analog inputs depend on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS7864 charges the internal capacitor array during the sampling period. After this Care must be taken regarding the absolute analog input voltage. The +IN and –IN inputs should always remain within the range of GND – 300mV to VDD + 300mV. ® 9 ADS7864 TRANSITION NOISE Figure 5 shows a histogram plot for the ADS7864 following 8,000 conversions of a DC input. The DC input was set at output code 2046. All but one of the conversions had an output code result of 2046 (one of the conversions resulted in an output of 2047). The histogram reveals the excellent noise performance of the ADS7864. R1 4kΩ OPA340 20kΩ Bipolar Input +IN –IN ADS7864 R2 BIPOLAR INPUTS The differential inputs of the ADS7864 were designed to accept bipolar inputs (–VREF and +VREF) around the internal reference voltage (2.5V), which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring a single amplifier and four external resistors, the ADS7864 can be configured to except bipolar inputs. The conventional ±2.5V, ±5V, and ±10V input ranges can be interfaced to the ADS7864 using the resistor values shown in Figure 7. REFOUT (pin 33) 2.5V R1 R2 ±10V ±5V ±2.5V 1kΩ 2kΩ 4kΩ 5kΩ 10kΩ 20kΩ FIGURE 7. Level Shift Circuit for Bipolar Input Ranges. THEORY OF OPERATION The ADS7864 contains two 12-bit A/D converters that operate simultaneously. The three hold signals (HOLDA, HOLDB, HOLDC) select the input MUX and initiate the conversion. A simultaneous hold on all six channels can occur with all three hold signals strobed together. The converted values are saved in 6 registers. For each read operation the ADS7864 outputs 16 bits of information (12 Data, 3 Channel Address and Data Valid). The Address/Mode signals (A0, A1, A2) select how the data is read from the ADS7864. These Address/Mode signals can define a selection of a single channel, a cycle mode that cycles through all channels or a FIFO mode that sequences the data determined by the order of the Hold signals. The FIFO mode will allow the 6 registers to be used by a single channel pair and therefore three locations for CH X0 and three locations for CH X1 can be acquired before they are read from the part. TIMING AND CONTROL The ADS7864 uses an external clock (CLOCK, pin 22) which controls the conversion rate of the CDAC. With an 8MHz external clock, the A/D sampling rate is 500kHz which corresponds to a 2µs maximum throughput time. 8000 7000 Number of Conversions BIPOLAR INPUT 6000 5000 4000 3000 2000 1000 EXPLANATION OF CLOCK, RESET AND BUSY PINS CLOCK—An external clock has to be provided for the ADS7864. The maximum clock frequency is 8MHz. The minimum clock cycle is 125ns (Figure 8, t 5 ), and the clock has to remain HIGH (Figure 8, t 6 ) or LOW (Figure 8, t 7) for at least 40ns. 0 2044 2045 2046 2047 2048 Code (decimal) FIGURE 5. Histogram of 8,000 Conversions of a DC Input. 1.4V RESET—Bringing reset LOW will reset the ADS7864. It will clear all the output registers, stop any actual conversions and will close the sampling switches. Reset has to stay LOW for at least 20ns (Figure 8, t8 ). The reset should be back HIGH for at least 20ns (Figure 8, t9 ), before starting the next conversion (negative hold edge). 3kΩ DATA Test Point 100pF CLOAD VOH DATA BUSY—Busy goes LOW when the internal A/D converters start a new conversion. It stays LOW as long as the conversion is in progress (Figure 9, 13 clock-cycles, t10 ) and rises again, after the data is latched to the output register. With busy going high, the new data can be read. It takes at least 16 clock cycles (Figure 9, t11) to complete conversion. VOL tR tF Voltage Waveforms for DATA Rise and Fall Times tR, and tF. FIGURE 6. Test Circuits for Timing Specifications. ® ADS7864 10 START OF A CONVERSION By bringing one or all of the HOLDX signals low, the input data of the corresponding channel X is immediately placed in the hold mode (5ns). The conversion of this channel X follows as soon as the AD-converter is available for the particular channel. If other channels are already in the hold mode but not converted, then the conversion of channel X is put in the queue until the previous conversion has been completed. If more than one channel goes into hold mode within one clock cycle, then channel A will be converted first if HOLDA is one of the triggered hold signals. Next channel B will be converted and at last channel C. If it is important to detect a hold command during a certain clock-cycle, then the falling edge of the hold signal has to occur at least 10ns before the falling edge of clock. (Figure 8, t1). The hold signal can remain low without initiating a new conversion. The hold signal has to be high for at least 15ns (Figure 8, t2 ) before it is brought low again and hold has to stay low for at least 20ns (Figure 8, t3). t6 CLOCK In the example of Figure 8, the signal HOLDB goes low first and channel B0 and B1 will be converted first. The falling edges of HOLDA and HOLDC occur within the same clock cycle. Therefore, the channels A0 and A1 will be converted as soon as the channels B0 and B1 are finished (plus acquisition time). When the A-channels are finished, the C-channels will be converted. The second HOLDA signal is ignored, as the A-channels are not converted at this point in time. Once a particular hold signal goes low, further impulses of this hold signal are ignored until the conversion is finished or the part is reset. When the conversion is finished (BUSY signal goes high) the sampling switches will close and sample the selected channel. The start of the next conversion must be delayed to allow the input capacitor of the ADS7864 to be fully charged. This delay time depends on the driving amplifier, but should be at least 175ns (Figure 9, t 4 ). The ADS7864 can also convert one channel continuously, as it is shown in Figure 9 with channel B. Therefore, HOLDA and HOLDC are kept high all the time. To gain acquisition TIMING SPECIFICATIONS t1 t7 t5 t3 HOLDA HOLDB t9 t2 HOLDC RESET t8 FIGURE 8. Start of the Conversion. SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 HOLD (A, B, C) before falling edge of clock 10 ns t2 HOLD HIGH time to be recognized again 15 ns t3 HOLD LOW time 20 ns t4 Input capacitor charge time 175 ns t5 Clock period 125 ns t6 Clock HIGH time 40 ns t7 Clock LOW time 40 ns t8 Reset pulse width 20 ns t9 First hold after reset 20 t10 Conversion time t11 Successive conversion time (16 • t5) 2 µs t12 Address setup before RD 10 ns t13 CS before end of RD 30 ns t14 RD HIGH time 30 ns ns 12.5 • t5 ns t11 BUSY t10 t4 CLOCK HOLDB CS RD A0 FIGURE 9. Timing of One Conversion Cycle. ® 11 ADS7864 time, the falling edge of HOLDB takes place just before the falling edge of clock. One conversion requires 16 clock cycles. Here, data is read after the next conversion is initiated by HOLDB. To read data from channel B, A1 is set high and A2 is low. As A0 is low during the first reading (A2 A1 A0 = 010) data B0 is put to the output. Before the second RD, A0 switches high (A2 A1 A0 = 011) so data from channel B1 is read. DATA CHANNEL DB14 DB13 DB12 A0 0 0 0 A1 0 0 1 B0 0 1 0 B1 0 1 1 C0 1 0 0 C1 1 0 1 TABLE I. Channel Truth Table. READING DATA (RD, CS)—In general, the channel/data outputs are in tristate. Both, CS and RD have to be LOW to enable these outputs. RD and CS have to stay LOW together for at least 30ns (Figure 10, t13 ) before the output data is valid. RD has to remain high for at least 30ns (Figure 10, t14) before bringing it back LOW for a subsequent read command. 12.5 clock-cycles after the start of a conversion (BUSY going LOW), the new data is latched into its output register. If a read process is initiated around 12.5 clock cycles after BUSY went LOW, RD and CS should stay LOW for at least 50ns to get the new data stored to its register and switched to the output. BYTE—If there is only an 8-bit bus available on a board then Byte can be set HIGH (see Figures 11 and 12). In this case, the lower eight bits can be read at the output pins DB7 to DB0 at the first RD signal and the higher bits after the second RD signal. GETTING DATA The ADS7864 has three different output modes that are selected with A2, A1 and A0. With (A2 A1 A0) = 000 to 101 a particular channel can directly be addressed (see Table II and Figure 9). The channel address should be set at least 10ns (Figure 10, t12) before the falling edge of RD and should not change as long as RD is low. CS being LOW tells the ADS7864 that the bus on the board is assigned to the ADS7864. If an A/D converter shares a bus with digital gates, there is a possibility, that digital (high frequency) noise gets coupled into the A/D converter. If the bus is just used by the ADS7864, CS can be hardwired to ground. Reading data at the falling edge of one of the hold signals might cause distortion of hold value. OUTPUT CODE (DB15…DB0) The ADS7864 has a 16 bit output word. DB15 is 1 if the output contains valid data. This is important for the FIFO mode. Valid Data can be read until DB15 switches to 0. DB14, DB13 and DB12 store channel information as indicated in Table I (Channel Truth Table). The 12 bit output data is stored from DB11 (MSB) to DB0 (LSB). CHANNEL SELECTED/ MODE A2 A1 A0 A0 0 0 0 A1 0 0 1 B0 0 1 0 B1 0 1 1 C0 1 0 0 C1 Cycle Mode FIFO Mode 1 1 1 0 1 1 1 0 1 TABLE II. Address/Mode Truth Table. BUSY CLOCK HOLDB t1 t4 t13 CS t14 RD t12 A0 FIGURE 10. Timing for Reading Data. ® ADS7864 12 With (A2 A1 A0) = 110 the interface is running in a cycle mode (see Figures 11 and 12). Here, data from channel A0 is read on the first RD signal, then A1 on the second, followed by B0, B1, C0 and finally C1 before reading A0 again. Data from channel A0 is brought to the output first after a reset-signal or after powering the part up. and is converted more frequently (e.g., to get a history of a particular channel) then there are 3 output registers per channel available to store data. If a read process is just going on (RD signal low) and new data has to be stored, then the ADS7864 will wait until the read process is finished (RD signal going high) before the new data gets latched into its output register. The third mode is a FIFO mode that is addressed with (A2 A1 A0 = 111). Data of the channel that is converted first will be read first. So, if a particular channel is most interesting HOLDA HOLDC BUSY CS RD BYTE FIGURE 11. Reading Data in Cycling Mode. CS RD BYTE A0 A0 A1 A1 B0 B0 LOW HIGH LOW HIGH LOW HIGH B1 C0 C1 A0 FIGURE 12. Reading Data in Cycling Mode. ® 13 ADS7864 At time tA (Figure 13) the ADS7864 resets. With the reset signal all conversions and scheduled conversions are cancelled. The data in the output registers are also cleared. With a reset a running conversion gets interrupted and all channels go into the sample mode again. The 16 bit output word has following structure: Valid Data 3-Bit Channel Information 12-Bit Data Word Bit 15 shows if the FIFO is empty (low) or if it contains channel information (high). Bit 12 to 14 contain the Channel for the 12 bit data word (Bit 0 to 11). If the data is from channel A0, then bits 14 to 12 are 000. The Channel bit pattern is outlined in Table I (Channel Truth Table). At time tB a HOLDB signal occurs. With the next falling clock edge (tC) the ADS7864 puts channel B into the loop to be converted next. As the reset signal occurred at tA, the conversion of channel B will be started with the next rising edge of the clock after tC. New data is always written into the next available register. At t0 (see Figure 14), the reset deletes all the existing data. At t1 the new data of the channels A0 and A1 are put into registers 0 and 1. On t2 the read process of channel A0 data is finished. Therefore this data is dumped and A1 data is shifted to register 0. At t3 new data is available, this time from channel B0 and B1. This data is written into the next available registers (register 1 and 2). The new data of channel C0 and C1 at t4 is put on top (registers 3 and 4). Within the next clock cycle (tC to tF), HOLDC (tD ) and HOLDA (tE ) occur. If more than one hold signals get active within one clock cycle, channel A will be converted first. So as soon as the conversion of channel B is done, the conversion of channel A will be initiated. After this second conversion, channel C will be converted. RESET CLOCK HOLDA HOLDB HOLDC tA tB tC t D t E tF FIGURE 13. Example of Hold Signals. RESET Conversion Channel B Conversion Channel A BUSY Conversion Channel C RD reg. 5 empty empty empty empty empty reg. 4 empty empty empty empty ch C1 reg. 2 empty empty empty empty ch C0 reg. 3 empty empty empty ch B1 ch B1 reg. 1 empty ch A1 empty ch B0 ch B0 reg. 0 empty ch A0 ch A1 ch A1 ch A1 t0 t1 t2 FIGURE 14. Functionality Diagram of FIFO Registers. ® ADS7864 14 t3 t4 LAYOUT to low-pass filter a noisy supply. On average, the ADS7864 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A bypass capacitor must not be used when using the internal reference (tie pin 33 directly to pin 34). For optimum performance, care should be taken with the physical layout of the ADS7864 circuitry. This is particularly true if the CLOCK input is approaching the maximum throughput rate. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Their error can change if the external event changes in time with respect to the CLOCK input. The AGND and DGND pins should be connected to a clean ground point. In all cases, this should be the ‘analog’ ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. APPLICATIONS An applications section will be added featuring the ADS7864 interfacing to popular DSP processors. The updated data sheet will be available in the near future on the Burr-Brown web site (www.burr-brown.com). With this in mind, power to the ADS7864 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor may be used ® 15 ADS7864 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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