OPA373, OPA2373 OPA374 OPA2374, OPA4374 SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 6.5MHz, 585µA, Rail-to-Rail I/O CMOS Operational Amplifier FEATURES D D D D D D D D DESCRIPTION LOW OFFSET: 5mV (max) LOW IB: 10pA (max) HIGH BANDWIDTH: 6.5MHz RAIL-TO-RAIL INPUT AND OUTPUT SINGLE SUPPLY: +2.3V to +5.5V SHUTDOWN: OPAx373 SPECIFIED UP TO +125°C MicroSIZE PACKAGES: SOT23-5, SOT23-6, and SOT23-8 The OPA373 and OPA374 families of operational amplifiers are low power and low cost with excellent bandwidth (6.5MHz) and slew rate (5V/µs). The input range extends 200mV beyond the rails and the output range is within 25mV of the rails. Their speed/power ratio and small size make them ideal for portable and battery-powered applications. The OPA373 family includes a shutdown mode. Under logic control, the amplifiers can be switched from normal operation to a standby current that is less than 1µA. APPLICATIONS D D D D PORTABLE EQUIPMENT BATTERY-POWERED DEVICES ACTIVE FILTERS DRIVING A/D CONVERTERS The OPA373 and OPA374 families of operational amplifiers are specified for single or dual power supplies of +2.7V to +5.5V, with operation from +2.3V to +5.5V. All models are specified for −40°C to +125°C. 1 V− 2 +IN A75 Out 3 OPA2373 OPA374 OPA373 6 V+ 5 Enable 4 −IN Out 1 V− 2 +IN 5 OUT A V+ 1 10 V+ −IN A 2 −IN 4 3 +IN A 9 OUT B 8 −IN B A 3 B SOT23−6(1) V− 4 7 +IN B Enable A 5 6 Enable B SOT23−5 OPA373 MSOP−10 NC(2) 1 8 Enable −IN 2 7 V+ +IN 3 6 OUT OUT A 1 V− 4 5 NC(2) −IN A 2 +IN A OPA4374 OPA2374 OUT A 1 14 OUT D −IN A 2 13 −IN D +IN A 3 3 12 +IN D V− 4 V+ 4 11 V− +IN B 5 10 +IN C −IN B 6 9 −IN C OUT B 7 8 OUT C D A A B 8 V+ 7 OUT B 6 −IN B 5 +IN B SO−8 OPA374 NC(2) 1 8 NC(2) −IN 2 7 V+ +IN 3 6 OUT V− 4 5 NC(2) B C SO−8, SOT23−8 SO−14, TSSOP−14 SO−8 (1) Pin 1 of the SOT23-6 is determined by orienting the package marking as shown. (2) NC indicates no internal connection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2003-2004, Texas Instruments Incorporated ! ! www.ti.com "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING Shutdown OPA373 ″ OPA373 ″ OPA2373 ″ SOT23-6 ″ SO-8 ″ MSOP-10 ″ DBV ″ D ″ DGS ″ −40°C to +125°C ″ −40°C to +125°C ″ −40°C to +125°C ″ A75 ″ OPA373A ″ AYO ″ ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA373AIDBVT Tape and Reel, 250 OPA373AIDBVR Tape and Reel, 3000 OPA373AID Rails, 100 OPA373AIDR Tape and Reel, 2500 OPA2373AIDGST Tape and Reel, 250 OPA2373AIDGSR Tape and Reel, 2500 Non-Shutdown OPA374 SOT23-5 DBV −40°C to +125°C A76 OPA374AIDBVT Tape and Reel, 250 ″ ″ ″ ″ ″ OPA374AIDBVR Tape and Reel, 3000 OPA374 SO-8 D −40°C to +125°C OPA274A OPA374AID Rails, 100 ″ ″ ″ ″ ″ OPA374AIDR Tape and Reel, 2500 OPA2374 SOT23-8 DCN −40°C to +125°C ATP OPA2374AIDCNT Tape and Reel, 250 ″ ″ ″ ″ ″ OPA2374AIDCNR Tape and Reel, 3000 OPA2374 SO-8 D −40°C to +125°C OPA2374A OPA2374AID Rails, 100 ″ ″ ″ ″ ″ OPA2374AIDR Tape and Reel, 2500 OPA4374 SO-14 D −40°C to +125°C OPA4374A OPA4374AID Rails, 58 ″ ″ ″ ″ ″ OPA4374AIDR Tape and Reel, 2500 OPA4374 TSSOP-14 PW −40°C to +125°C OPA4374A OPA4374AIPWT Tape and Reel, 250 ″ ″ ″ ″ ″ OPA4374AIPWR Tape and Reel, 2500 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Signal Input Terminals, Voltage(2) . . . . . . . . . −0.5V to (V+) + 0.5V Current(2) . . . . . . . . . . . . . . . . . . . ±10mA (3) Output Short-Circuit . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current-limited to 10mA or less. (3) Short-circuit to ground, one amplifier per package. 2 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V Boldface limits apply over the specified temperature range, TA = −40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. OPA373, OPA2373, OPA374, OPA2374, OPA4374 PARAMETER OFFSET VOLTAGE Input Offset Voltage over Temperature Drift vs Power Supply over Temperature Channel Separation, DC f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio over Temperature CONDITIONS VOS dVOS/dT PSRR VS = 5V OPEN-LOOP GAIN Open-Loop Voltage Gain over Temperature VCM CMRR (V−) − 0.2V < VCM < (V+) − 2V (V−) − 0.2V < VCM < (V+) − 2V VS = 5.5V, (V−) − 0.2V < VCM < (V+) + 0.2V VS = 5.5V, (V−) − 0.2V < VCM < (V+) + 0.2V (V−) − 0.2 80 70 66 60 ENABLE/SHUTDOWN tOFF tON VL (shutdown) VH (amplifier is active) Input Bias Current of Enable Pin IQSD (per amplifier) 1 5 6.5 mV mV µV/°C µV/V µV/V µV/V dB 100 150 (V+) + 0.2 V dB dB dB dB ±10 ±10 pA pA 90 1013 3 1013 6 Ω pF Ω pF 10 15 4 µVPP nV/√Hz fA/√Hz 110 dB dB dB dB VCM < (V+) − 2V en in AOL OUTPUT Voltage Output Swing from Rail over Temperature FREQUENCY RESPONSE Gain-Bandwidth Product Slew Rate Settling Time, 0.1% 0.01% Overload Recovery Time Total Harmonic Distortion + Noise UNIT ±0.5 ±0.5 IB IOS over Temperature over Temperature Short-Circuit Current Capacitive Load Drive Open-Loop Output Impedance MAX 3 25 VS = 2.7V to 5.5V, VCM < (V+) − 2V VS = 2.7V to 5.5V, VCM < (V+) − 2V INPUT IMPEDANCE Differential Common-Mode NOISE Input Voltage Noise, f = 0.1Hz to 10Hz Input Voltage Noise Density, f = 10kHz Input Current Noise Density, f = 10kHz TYP 0.4 128 over Temperature INPUT BIAS CURRENT Input Bias Current Input Offset Current MIN VS = 5V, RL = 100kΩ, 0.025V < VO < 4.975V VS = 5V, RL = 100kΩ, 0.025V < VO < 4.975V VS = 5V, RL = 5kΩ, 0.125V < VO < 4.875V VS = 5V, RL = 5kΩ, 0.125V < VO < 4.875V RL = 100kΩ RL = 100kΩ RL = 5kΩ RL = 5kΩ ISC CLOAD f = 1MHz, IO = 0 94 80 94 80 106 18 25 25 100 125 125 See Typical Characteristics See Typical Characteristics 220 mV mV mV mV 6.5 5 1 1.5 0.3 0.0013 MHz V/µs µs µs µs % 3 12 µs µs V V µA µA Ω CL = 100pF GBW SR tS THD+N G = +1 VS = 5V, 2V Step, G = +1 VS = 5V, 2V Step, G = +1 VIN • Gain > VS VS = 5V, VO = 3VPP, G = +1, f = 1kHz V− (V−) + 0.8 V+ (V−) + 2 0.2 < 0.5 1 3 "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (continued) Boldface limits apply over the specified temperature range, TA = −40°C to +125°C. At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. OPA373, OPA2373, OPA374, OPA2374, OPA4374 PARAMETER POWER SUPPLY Specified Voltage Range Operating Voltage Range Quiescent Current (per amplifier) over Temperature TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance SOT23-5, SOT23-6, SOT23-8 MSOP-10, SO-8 SO-14, TSSOP-14 4 CONDITIONS VS IQ MIN TYP 2.7 2.3 to 5.5 585 IO = 0 −40 −55 −65 MAX UNIT 5.5 V V µA µA 750 800 +125 +150 +150 qJA +200 +150 +100 °C °C °C °C/W °C/W °C/W °C/W "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. POWER−SUPPLY AND COMMON−MODE REJECTION RATIO vs FREQUENCY 120 100 0 100 Gain 80 −30 60 −60 40 −90 Phase PSRR and CMRR (dB) 30 Phase Margin (_) Open−Loop Gain (dB) OPEN−LOOP GAIN AND PHASE vs FREQUENCY 120 CMRR 80 40 20 −120 0 −150 20 −180 10M 0 −20 10 100 1k 10k 100k 1M PSRR 60 100 1k 10k Frequency (Hz) 10M 0.100 Total Harmonic Distortion+Noise (%) 1000 Voltage Noise (nV/√Hz) 1M TOTAL HARMONIC DISTORTION+NOISE vs FREQUENCY INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 100 RL = 5kΩ G = 10V/V 0.010 G = 1V/V 0.001 10 10 100 1k 10k 10 100k 100 1k 10k 100k Frequency (Hz) Frequency (Hz) OPEN−LOOP GAIN AND POWER−SUPPLY REJECTION RATIO vs TEMPERATURE COMMON−MODE REJECTION RATIO vs TEMPERATURE 120 130 VS = 5.5V RL = 100kΩ 110 120 VCM = −0.2V to 3.5V 100 CMRR (dB) AOL, PSRR (dB) 100k Frequency (Hz) 110 RL = 5kΩ 100 PSRR 90 80 VCM = −0.2V to 5.7V 70 60 90 50 80 40 −50 −25 0 25 50 75 Temperature (_ C) 100 125 150 −50 −25 0 25 50 75 100 125 150 Temperature (_C) 5 "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. QUIESCENT CURRENT vs SUPPLY VOLTAGE QUIESCENT CURRENT vs TEMPERATURE 800 800 VOUT = 1/2[(V+) − (V−)] Quiescent Current (µA) Quiescent Current (µA) 700 600 500 400 300 700 600 500 400 −50 −25 300 0 25 50 75 100 125 150 2.0 3.0 4.5 5.0 5.5 CONTINUOUS SHORT−CIRCUIT CURRENT vs POWER−SUPPLY VOLTAGE 12 +ISC Short−Circuit Current (mA) +ISC 12 10 8 −ISC 6 4 2 0 10 8 −ISC 6 4 2 0 −50 −25 0 25 50 75 100 125 2.0 2.5 3.0 Temperature (_ C) 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 3 1k 2 Output Voltage (V) 10k 100 10 1 1 0 −1 −55_ C 25_C 150_C −2 −3 0.1 −50 −25 0 25 50 Temperature (_ C) 5.5 Power−Supply Voltage (V) INPUT BIAS CURRENT vs TEMPERATURE Input Bias Current (pA) 4.0 SHORT−CIRCUIT CURRENT vs TEMPERATURE 14 6 3.5 Supply Voltage (V) 16 Short−Circuit Current (mA) 2.5 Temperature (_C) 75 100 125 0 2 4 6 8 10 12 Output Current (mA) 14 16 18 20 "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. OFFSET VOLTAGE PRODUCTION DISTRIBUTION MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 6 VS = 5.5V VS = 5V 4 3 Population Output Voltage (VPP ) 5 VS = 2.5V 2 1 0 10k 100k 1M −5 10M −4 −3 −2 −1 0 1 2 3 4 5 5.5 Offset Voltage (mV) Frequency (Hz) OFFSET VOLTAGE DRIFT MAGNITUDE PRODUCTION DISTRIBUTION SMALL−SIGNAL STEP RESPONSE CL = 100pF Population 50mV/div Typical production distribution of packaged units. 1 2 3 4 5 6 7 8 200ns/div 9 10 11 12 13 14 15 16 Offset Voltage Drift (µV/_C) LARGE −SIGNAL STEP RESPONSE SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE 50 Refer to the Capacitive Load and Stability section for tips on improving performance. CL = 100pF 40 1V/div Small−Signal Overshoot (%) 60 G = +1V/V 30 20 G = ±10V/V RFB = 10kΩ 10 0 10 100 1k 10k 400ns/div Load Capacitance (pF) 7 "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, RL = 10kΩ connected to VS/2, and VOUT = VS/2, unless otherwise noted. CHANNEL SEPARATION vs FREQUENCY SETTLING TIME vs CLOSED−LOOP GAIN 140 Channel Separation (dB) Settling Time (µs) 100 10 0.01% 0.1% 1 G = +1V/V, All Channels RL = 5kΩ 120 100 80 60 40 20 0.1 0 1 10 Closed−Loop Gain (V/V) 8 100 10 100 1K 10K 100K Frequency (Hz) 1M 10M 100M "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 APPLICATIONS The input common-mode voltage range includes both rails, allowing the OPA373 and OPA374 series op amps to be used in virtually any single-supply application up to a supply voltage of +5.5V. 1.5 Offset Voltage (mV) The OPA373 and OPA374 series op amps are unity-gain stable and suitable for a wide range of general-purpose applications. Rail-to-rail input and output make them ideal for driving sampling Analog-to-Digital Converters (ADCs). Excellent AC performance makes them well suited for audio applications. The class AB output stage is capable of driving 100kΩ loads connected to any point between V+ and ground. 2.0 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 − 0.5 0 V− V+ 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common−Mode Voltage (V) Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications. Figure 1. Behavior of Typical Transition Region at Room Temperature Power-supply pins should be bypassed with 0.01µF ceramic capacitors. RAIL-TO-RAIL INPUT OPERATING VOLTAGE The OPA373 and OPA374 op amps are specified and tested over a power-supply range of +2.7V to +5.5V (±1.35V to ±2.75V). However, the supply voltage may range from +2.3V to +5.5V (±1.15V to ±2.75V). Supply voltages higher than 7.0V (absolute maximum) can permanently damage the amplifier. Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section of this data sheet. The input common-mode range extends from (V−) − 0.2V to (V+) + 0.2V. For normal operation, inputs should be limited to this range. The absolute maximum input voltage is 500mV beyond the supplies. Inputs greater than the input common-mode range but less than the maximum input voltage, while not valid, will not cause any damage to the op amp. Unlike some other op amps, if input current is limited, the inputs may go beyond the supplies without phase inversion, as shown in Figure 2. G = +1V/V, VS = 5V VIN The input common-mode voltage range of the OPA373 and OPA374 series extends 200mV beyond the supply rails. This is achieved with a complementary input stage—an N-channel input differential pair in parallel with a P-channel differential pair. The N-channel pair is active for input voltages close to the positive rail, typically (V+) − 1.65V to 200mV above the positive supply, while the P-channel pair is on for inputs from 200mV below the negative supply to approximately (V+) − 1.65V. There is a 500mV transition region, typically (V+) − 1.9V to (V+) − 1.4V, in which both pairs are on. This 500mV transition region, shown in Figure 1, can vary ±300mV with process variation. Thus, the transition region (both stages on) can range from (V+) − 2.2V to (V+) − 1.7V on the low end, up to (V+) − 1.6V to (V+) − 1.1V on the high end. Within the 500mV transition region PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation outside this region. 5V VOUT 1V/div COMMON-MODE VOLTAGE RANGE 0V 1µs/div Figure 2. OPA373: No Phase Inversion with Inputs Greater Than the Power-Supply Voltage Normally, input bias current is approximately 500fA; however, input voltages exceeding the power supplies by more than 500mV can cause excessive current to flow in or out of the input pins. Momentary voltages greater than 500mV beyond the power supply can be tolerated if the current on the input pins is limited to 10mA. This is easily accomplished with an input resistor; see Figure 3. (Many input signals are inherently current-limited to less than 10mA, therefore, a limiting resistor is not required.) 9 "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 V+ IOVERLOAD 10mA max R OPA373 VOUT capacitor, CFB, can be inserted in the feedback, as shown in Figure 5. This significantly reduces overshoot by compensating the effect of capacitance, CIN, which includes the amplifier input capacitance and PC board parasitic capacitance. VIN V+ RS 10Ωto 20Ω Figure 3. Input Current Protection for Voltages Exceeding the Supply Voltage VOUT OPA373 VIN RL CL RAIL-TO-RAIL OUTPUT A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For light resistive loads ( > 100kΩ), the output voltage can typically swing to within 18mV from the supply rails. With moderate resistive loads (5kΩ to 50kΩ), the output can typically swing to within 100mV from the supply rails and maintain high open-loop gain. See the Typical Characteristics curve, Output Voltage Swing vs Output Current, for more information. Figure 4. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive CFB RF CAPACITIVE LOAD AND STABILITY One method of improving capacitive load drive in the unity-gain configuration is to insert a small (10Ω to 20Ω) resistor, RS, in series with the output, as shown in Figure 4. This significantly reduces ringing while maintaining DC performance for purely capacitive loads. When there is a resistive load in parallel with the capacitive load, RS must be placed within the feedback loop as shown to allow the feedback loop to compensate for the voltage divider created by RS and RL. RI VIN VOUT OPA373 CIN CL Figure 5. Improving Capacitive Load Drive For example, when driving a 100pF load in unity-gain inverter configuration, adding a 6pF capacitor in parallel with the 10kΩ feedback resistor decreases overshoot from 57% to 12%, as shown in Figure 6. 60 G = −1V/V RFB = 10kΩ 50 Overshoot (%) OPA373 series op amps can drive a wide range of capacitive loads. However, under certain conditions, all op amps may become unstable. Op amp configuration, gain, and load value are just a few of the factors to consider when determining stability. An op amp in unity-gain configuration is the most susceptible to the effects of capacitive load. The capacitive load reacts with the op amp output resistance, along with any additional load resistance, to create a pole in the small-signal response that degrades the phase margin. The OPA373 series op amps perform well in unity-gain configuration, with a pure capacitive load up to approximately 250pF. Increased gains allow the amplifier to drive more capacitance. See the Typical Characteristics curve, Small-Signal Overshoot vs Capacitive Load, for further details. V+ 40 30 20 10 In unity-gain inverter configuration, phase margin can be reduced by the reaction between the capacitance at the op amp input and the gain setting resistors, thus degrading capacitive load drive. Best performance is achieved by using small valued resistors. However, when large valued resistors cannot be avoided, a small (4pF to 6pF) 10 CFB = 6pF 0 10 100 1k 10k Load Capacitance (pF) Figure 6. Improving Capacitive Load Drive "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 DRIVING ADCs Figure 8 shows the OPA373 driving the ADS7816 in a speech band-pass filtered data acquisition system. This small, low-cost solution provides the necessary amplification and signal conditioning to interface directly with an electret microphone. This circuit will operate with VS = 2.7V to 5V. The OPA373 and OPA374 series op amps are optimized for driving medium-speed sampling ADCs. The OPA373 and OPA374 op amps buffer the ADC input capacitance and resulting charge injection, while providing signal gain. The OPA373 is shown driving the ADS7816 in a basic noninverting configuration, as shown in Figure 7. The ADS7816 is a 12-bit, MicroPower sampling converter in the MSOP-8 package. When used with the low-power, miniature packages of the OPA373, the combination is ideal for space-limited, low-power applications. In this configuration, an RC network at the ADC input can be used to provide anti-aliasing filtering. The OPA373 is shown in the inverting configuration described in Figure 9. In this configuration, filtering may be accomplished with the capacitor across the feedback resistor. ENABLE/SHUTDOWN OPA373 and OPA374 series op amps typically require 585µA quiescent current. The enable/shutdown feature of the OPA373 allows the op amp to be shut off in order to reduce this current to less than 1µA. +5V 0.1µF 0.1µF 1 VREF 8 V+ 500Ω 7 DCLOCK +In OPA373 2 VIN ADS7816 12−Bit ADC −In 3300pF 6 DOUT CS/SHDN 3 Serial Interface 5 GND 4 VIN = 0V to 5V for 0V to 5V output. fSAMPLE = 100kHz NOTE: ADC Input = 0 to VREF RC network filters high frequency noise. Figure 7. The OPA373 in Noninverting Configuration Driving the ADS7816 V+ = +2.7V to +5V Passband 300Hz to 3kHz R9 510kΩ R1 1.5kΩ R2 1MΩ R4 20kΩ C3 33pF C1 1000pF Electret Microphone (1) R3 1MΩ 1/2 OPA2373 R7 51kΩ R8 150kΩ VREF 1 8 V+ 7 C2 1000pF R6 100kΩ 1/2 OPA2373 +IN ADS7816 6 12−Bit ADC 5 2 −IN DCLOCK D OUT CS/SHDN Serial Interface 3 4 GND NOTE: (1) Electret microphone powered by R 1. R5 20kΩ G = 100 Figure 8. The OPA2373 as a Speech Bypass Filtered Data Acquisition System 11 "#"$ %"#" "#& %"#&$ &"#& www.ti.com SBOS279D − SEPTEMBER 2003 − REVISED DECEMBER 2004 +5V 330pF 0.1µF 5kΩ 0.1µF 5kΩ VIN 1 VREF 8 V+ 500kΩ OPA373 VS 2 DCLOCK 7 +IN 6 ADS7816 DOUT 12− Bit ADC 2 5 −IN CS/SHDN 3300pF 3 GND 4 Serial Interface NOTE: ADC Input = 0 to VREF Figure 9. The OPA373 in Inverting Configuration Driving the ADS7816 C3 330pF R1 11.7kΩ 1/2 R2 2.72kΩ R3 21.4kΩ OPA373 1/2 OPA373 C1 680pF C2 330pF NOTE: FilterPro is a low-pass filter design program available for download at no cost from TI’s web site (www.ti.com). The program can be used to determine component values for other cutoff frequencies or filter types. Figure 10. Three-Pole Sallen-Key Butterworth Low-Pass Filter 12 PACKAGE OPTION ADDENDUM www.ti.com 16-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA2373AIDGSR ACTIVE MSOP DGS 10 3000 None CU NIPDAU Level-3-235C-168 HR OPA2373AIDGST ACTIVE MSOP DGS 10 250 None CU NIPDAU Level-3-235C-168 HR Lead/Ball Finish MSL Peak Temp (3) OPA2374AID ACTIVE SOIC D 8 100 None CU SNPB Level-1-240C-UNLIM OPA2374AIDCNR ACTIVE SOT23 DCN 8 3000 None CU SNPB Level-3-220C-168 HR OPA2374AIDCNT ACTIVE SOT23 DCN 8 250 None CU SNPB Level-3-220C-168 HR OPA2374AIDR ACTIVE SOIC D 8 2500 None CU SNPB Level-1-240C-UNLIM OPA373AID ACTIVE SOIC D 8 100 None CU SNPB Level-1-240C-UNLIM OPA373AIDBVR ACTIVE SOT-23 DBV 6 3000 None CU NIPDAU Level-3-250C-168 HR OPA373AIDBVT ACTIVE SOT-23 DBV 6 250 None CU NIPDAU Level-3-250C-168 HR OPA373AIDR ACTIVE SOIC D 8 2500 None CU SNPB Level-1-240C-UNLIM OPA374AID ACTIVE SOIC D 8 100 None CU SNPB Level-1-220C-UNLIM OPA374AIDBVR ACTIVE SOT-23 DBV 5 3000 None CU NIPDAU Level-3-250C-168 HR OPA374AIDBVT ACTIVE SOT-23 DBV 5 250 None CU NIPDAU Level-3-250C-168 HR OPA374AIDR ACTIVE SOIC D 8 2500 None CU SNPB Level-1-220C-UNLIM OPA4374AID ACTIVE SOIC D 14 58 None CU SNPB Level-1-220C-UNLIM OPA4374AIDR ACTIVE SOIC D 14 2500 None CU SNPB Level-1-220C-UNLIM OPA4374AIPWR ACTIVE TSSOP PW 14 2500 None CU SNPB Level-1-220C-UNLIM OPA4374AIPWT ACTIVE TSSOP PW 14 250 None CU SNPB Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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