BB OPA671AP

®
OPA671
OPA
671
Wide Bandwidth, Fast Settling
Difet ® OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
● HIGH GAIN-BANDWIDTH: 35MHz
The OPA671 is a FET-input monolithic operational
amplifier featuring wide bandwidth and fast settling
time. Fabricated using Burr-Brown’s Difet, complementary bipolar process, it provides an excellent combination of high speed, accuracy, and high output
current.
● LOW INPUT NOISE: 10nV/√Hz
● HIGH SLEW RATE: 100V/µs
● FAST SETTLING: 240ns to 0.01%
● FET INPUT: IB = 50pA max
● HIGH OUTPUT CURRENT: 50mA
● WIDE SUPPLY RANGE: VS = ±4.5 to ±18V
APPLICATIONS
The OPA671 is versatile, operating from ±4.5V to
±18V power supplies. It can deliver ±10V signals into
a 200Ω load at slew rates of 100V/µs. OPA671’s Difet
input provides input bias current thousands of times
lower than bipolar-input wideband op amps.
The OPA671 is internally compensated to be unity-gain
stable, allowing use in the widest range of applications.
● HIGH-SPEED DATA ACQUISITION
● OPTOELECTRONICS
● TRANSIMPEDANCE AMPLIFIER
The OPA671 is available in an 8-pin plastic DIP, rated
for the industrial temperature range.
● LINE DRIVER
● CCD BUFFER AMPLIFIER
V+
7
Trim
Trim
1
5
+In
–In
3
2
VO
6
4
V–
Difet® Burr-Brown Corporation
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1991 Burr-Brown Corporation
PDS-1120D
Printed in U.S.A. October, 1993
SPECIFICATIONS
At TA = +25°C, VS = ±15V, unless otherwise noted.
OPA671AP
PARAMETER
CONDITION
OFFSET VOLTAGE
Input Offset Voltage
Average Drift
Power Supply Rejection
INPUT BIAS CURRENT(1)
Input Bias Current
Input Offset Current
VS = ±4.5 to ±16.5V
MIN
TYP
MAX
UNITS
±5
72
±0.5
±10
94
mV
µV/°C
dB
5
2
50
pA
pA
VCM = 0V
VCM = 0V
NOISE
Input Voltage Noise
Noise Density, f = 100Hz
f = 1kHz
f = 10kHz
f = 100kHz
Voltage Noise, BW = 10Hz to 1MHz
Input Bias Current Noise
Current Noise Density, f = 10Hz to 1MHz
INPUT VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
±12
74
VCM = ±10V
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time
0.01%
0.1%
1%
Total Harmonic Distortion
OUTPUT
Voltage Output
Current Output
Short Circuit Current
Output Resistance, Open-Loop
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
TEMPERATURE RANGE
Specification
Operating
Storage
Thermal Resistance, θJA
VO = ±10V, RL = 1kΩ
VO = ±10V, RL = 200Ω
74
G = –1, 10V Step
G = –1, 10V Step
G = –1, 10V Step
G = –1, 10V Step
G = 1, f = 100kHz
VO = 3V, RL = 200Ω
±10.5
RL = 200Ω
VO = ±10V
DC
±4.5
VS = ±15V
24
15
12
10
60
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
2
fA/√Hz
±13
92
V
dB
1012 || 4.5
1012 || 6
Ω || pF
Ω || pF
80
78
dB
dB
35
107
240
150
85
0.0006
MHz
V/µs
ns
ns
ns
%
±11.5
50
–90/+105
20
V
mA
mA
Ω
±15
±14.8
–25
–40
–40
Junction to Ambient
±18
±17
+85
+100
+125
100
V
V
mA
°C
°C
°C
°C/W
NOTE: (1) Tested without warm-up at TJ = TA = 25°C.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
OPA671
2
ELECTROSTATIC
DISCHARGE SENSITIVITY
PIN CONFIGURATION
Top View
DIP
VOS Trim
1
8
NC
–In
2
7
V+
+In
3
6
VO
V–
4
5
VOS Trim
An integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published
specifications.
NC = No Internal Connection
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDERING INFORMATION
Power Supply Voltage ........................................................................ ±18V
Input Voltage ............................................................. (V+) +1V to (V–) –1V
Operating Temperature ................................................... –40°C to +100°C
Storage Temperature ...................................................... –40°C to +125°C
Output Short-Circuit to Ground ............................................................ 15s
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
OPA671AP
8-Pin Plastic DIP
006
TEMPERATURE
RANGE
–25°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
OPA671
TYPICAL PERFORMANCE CURVES
TA = +25°C, VS = ±15V unless otherwise noted.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
INPUT VOLTAGE NOISE SPECTRAL DENSITY
90
1k
0
–45
Phase
Phase (°)
Gain (dB)
60
–90
50
40
Gain
30
–135
20
–180
10
Voltage Noise (nV/ Hz)
80
70
0
–10
10
0
1k
100k
10k
1M
10M
1
100M
10k
1k
100k
1M
Frequency (Hz)
GAIN-BANDWIDTH PRODUCT AND
SLEW RATE vs TEMPERATURE
POWER SUPPLY REJECTION AND
COMMON-MODE REJECTION vs TEMPERATURE
Slew Rate (V/µs)
110
40
SR
105
35
GBW
100
PSR
90
CMR
100
30
10M
110
PSR & CMR (dB)
115
80
25
–25
25
0
50
75
–25
100
Temperature (°C)
0
25
50
75
100
Temperature (°C)
OPEN-LOOP GAIN vs LOAD RESISTANCE
OPEN-LOOP GAIN vs TEMPERATURE
90
Open-Loop Gain (dB)
90
Open-Loop Gain (dB)
100
10
Frequency (Hz)
45
Gain-Bandwidth Product (MHz)
100
80
RL = 200Ω
70
80
70
60
50
60
–25
0
25
50
75
20
100
®
OPA671
100
200
Load Resistance (Ω)
Temperature (°C)
4
1k
2k
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VS = ±15V unless otherwise noted.
SHORT-CIRCUIT CURRENT
vs TEMPERATURE
POWER SUPPLY CURRENT vs TEMPERATURE
120
Short-Circuit Current (mA)
Power Supply Current (mA)
16.0
15.5
15.0
14.5
110
ISC+
100
90
ISC –
80
70
14.0
60
–25
25
0
75
50
100
–25
75
50
Temperature (°C)
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs JUNCTION TEMPERATURE
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
1000
100
0.001
100
THD + N (%)
Input Bias And Offset Current (pA)
25
0
Temperature (°C)
IB
10
G=1
0.0004
G = 10
IOS
1
RL = 200Ω
0
–25
0.0001
0
25
75
50
100
10
125
Junction Temperature (°C)
100
1k
10k
100k
Frequency (Hz)
MAX OUTPUT VOLTAGE SWING vs FREQUENCY
Max Output Voltage Swing (Vp-p)
30
20
10
0
100k
1M
10M
100M
Frequency (Hz)
®
5
OPA671
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VS = ±15V unless otherwise noted.
G = +1 LARGE SIGNAL RESPONSE
G = +1 SMALL SIGNAL RESPONSE
G = –1 LARGE SIGNAL RESPONSE
G = –1 SMALL SIGNAL RESPONSE
®
OPA671
6
CIRCUIT LAYOUT
(a)
With any high-speed, wide-bandwidth circuitry, careful circuit
layout will ensure best performance. Make short, direct circuit
interconnections and avoid stray wiring capacitance—especially at the inverting input pin. A component-side ground plane
will help ensure low ground impedance. Do not place the
ground plane under or near the inputs and feedback network.
The power supply connections should be bypassed with good
high-frequency capacitors positioned close to the op amp pins.
In most cases, both a 1µF solid tantalum capacitor and a 0.1µF
ceramic capacitor are required on each supply. The OPA671
can deliver peak load currents up to 100mA. Even if steadystate load currents are lower, signal transients may demand
large current transients from the power supplies. It is the power
supply bypass capacitors which must supply these current
transients. Larger bypass capacitors such as 4.7µF solid tantalum capacitors may improve dynamic performance in some
applications.
47kΩ
VO
VI
G=1
(b)
1kΩ
CL
100pF
250pF
1kΩ
CC
CL
100pF
RC
10pF 20Ω
1000pF 47pF 20Ω
CC
RC
VO
VI
CL
G = –1
1kΩ
(c)
1kΩ
330Ω
RC
VO
100pF
VI
OFFSET ADJUSTMENT
CL ≤ 100pF
G = –1
See application bulletin AB-028 for
details on circuits for driving capacitive loads.
Many applications require no external offset voltage adjustment. Figure 1 shows an optional circuit for trimming the offset
voltage. Do not use this offset voltage adjustment to correct for
offsets produced in other circuitry since this can introduce large
offset voltage temperature drift.
FIGURE 2. Compensation Circuits for Capacitive Loads.
assure that the maximum junction temperature is not exceeded.
The OPA671 may be operated at reduced power supply voltage
to minimize power dissipation.
V+
10kΩ
FIGURE 1. Optional Offset Voltage Trim Circuit.
OUTPUT CURRENT LIMIT
Output current is limited by internal circuitry to approximately
90mA at 25°C. The short-circuit limit current decreases with
increasing junction temperature as shown in the typical curves.
The current limit will protect the device from inadvertent shortcircuits to ground. The internal power dissipation under this
condition, however, is quite high so short-circuits should be
avoided.
CAPACITIVE LOADS
INPUT BIAS CURRENT
The OPA671 is internally compensated to be unity-gain stable
with minimal capacitive load. The combination of low closedloop gain and capacitive load will decrease the phase margin
and may lead to gain peaking or oscillations. Load capacitance
reacts with the op amp’s open-loop output resistance to form an
additional pole in the feedback loop. With wideband op amps,
load capacitance as low as 50pF can introduce enough phase
shift to degrade dynamic performance. Figure 2 shows circuits
which preserve phase margin with capacitive load. Request
Application Bulletin AB-028 for details on various compensation circuits and analysis techniques.
The OPA671 is fabricated with Burr-Brown’s dielectrically
isolated Difet process, giving it extremely low input bias
current. As with other FET-input amplifiers, input bias current
approximately doubles with every 10°C increase in junction
temperature. Input bias current can be minimized by soldering
the device to the circuit board to provided best heat dissipation.
Reduced power supply voltage will also minimize input bias
current by reducing internal power dissipation.
5kΩ to 50kΩ
Potentiometer
(10kΩ preferred)
7
2
3
1
5
OPA671
6
4
V–
DEMONSTRATION BOARD
The OPA671 may be evaluated using a high frequency PC
board developed for the OPA65x op amp family. This board
may be ordered from your local Burr-Brown distribution as part
# DEM-OPA65xP. It comes partially assembled but does not
include the amplifier. Since this board was intended for ±5V
amplifier, verify that any electrolytic capacitors loaded on the
board can support the higher supply voltages possible with the
OPA671.
POWER DISSIPATION
High output current can cause large internal power dissipation
in the OPA671. Copper leadframe construction improves heat
dissipation compared to conventional plastic packages. To
achieve best heat dissipation, solder the device directly to the
circuit board and use wide circuit board traces close to the
device pins. Limit the ambient temperature, load and signal to
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7
OPA671