OPA621 ® Wideband Precision OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● LOW NOISE: 2.3nV/√Hz ● LOW DIFFERENTIAL GAIN/PHASE ERROR ● HIGH OUTPUT CURRENT: 150mA ● LOW NOISE PREAMPLIFIER ● LOW NOISE DIFFERENTIAL AMPLIFIER ● HIGH-RESOLUTION VIDEO ● FAST SETTLING: 25ns (0.01%) ● GAIN-BANDWIDTH: 500MHz ● STABLE IN GAINS: ≥ 2V/V ● LINE DRIVER ● HIGH-SPEED SIGNAL PROCESSING ● ADC/DAC BUFFER ● LOW OFFSET VOLTAGE: ±100µV ● SLEW RATE: 500V/µs ● ULTRASOUND ● PULSE/RF AMPLIFIERS ● 8-PIN DIP, SOIC PACKAGES ● ACTIVE FILTERS DESCRIPTION The OPA621 is a precision wideband monolithic operational amplifier featuring very fast settling time, low differential gain and phase error, and high output current drive capability. The OPA621 is stable in gains of ±2V/V or higher. This amplifier has a very low offset, fully symmetrical differential input due to its “classical” operational amplifier circuit architecture. Unlike “current-feedback” amplifier designs, the OPA621 may be used in all op amp applications requiring high speed and precision. Low noise and distortion, wide bandwidth, and high linearity make this amplifier suitable for RF and video applications. Short circuit protection is provided by an internal current-limiting circuit. The OPA621 is available in DIP and SO-8 packages. +VCC 7 Non-Inverting Input Inverting Input 3 2 Output Stage 6 Output Current Mirror 4 –VCC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1989 Burr-Brown Corporation PDS-939F Printed in U.S.A. June, 1997 SPECIFICATIONS ELECTRICAL At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. OPA621KP, KU PARAMETER CONDITIONS INPUT NOISE Voltage: fO = 100Hz fO = 1kHz fO = 10kHz fO = 100kHz fO = 1MHz to 100MHz fB = 100Hz to 10MHz Current: fO = 10kHz to 100MHz OFFSET VOLTAGE(1) Input Offset Voltage Average Drift Supply Rejection MIN TYP MAX UNITS RS = 0Ω 10 5.5 3.3 2.5 2.3 8.0 2.3 VCM = 0VDC TA = TMIN to TMAX ±VCC = 4.5V to 5.5V ±200 ±12 60 ±1mV µV µV/°C dB 50 nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz µV, rms pA/√Hz BIAS CURRENT Input Bias Current VCM = 0VDC 18 30 µA OFFSET CURRENT Input Offset Current VCM = 0VDC 0.2 2 µA Open-Loop 15 || 1 1 || 1 kΩ || pF MΩ || pF INPUT IMPEDANCE Differential Common-Mode INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Closed-Loop Bandwidth (–3dB) Gain-Bandwidth Product Differential Gain Differential Phase Harmonic Distortion Full Power Bandwidth Slew Rate Overshoot Settling Time: 0.1% 0.01% Phase Margin Rise Time RATED OUTPUT Voltage Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Derated Performance Current, Quiescent TEMPERATURE RANGE Specification: KP, KU Operating: KP, KU θJA KP KU VIN = ±2.5VDC, VO = 0VDC ±3.0 65 ±3.5 75 V dB RL = 100Ω RL = 50Ω 50 48 60 58 dB dB 500 100 50 500 0.05 0.05 MHz MHz MHz MHz % Degrees Gain = +2V/V Gain = +5V/V Gain = +10V/V Gain ≥ +10V/V 3.58MHz, G = +2V/V 3.58MHz, G = +2V/V G = +2V/V, f = 10MHz, VO = 2Vp-p f = 10MHz, Second Harmonic Third Harmonic VO = 5Vp-p, Gain = +2V/V VO = 2Vp-p, Gain = +2V/V 2V Step, Gain = –2V/V 2V Step, Gain = –2V/V 2V Step, Gain = –2V/V 22 55 350 Gain = +2V/V Gain = +2V/V, 10% to 90% VO = 100mVp-p; Small Signal VO = 6Vp-p; Large Signal ±3.0 ±2.5 RL = 100Ω RL = 50Ω 1MHz, Gain = +2V/V Gain = +2V/V Continuous ±VCC ±VCC IO = 0mA –50 –70 ns ns ±3.5 ±3.0 0.015 15 ±150 V V Ω pF mA 5 26 Ambient Temperature –40 –40 6.0 28 +85 +85 100 125 2 dBc(3) dBc MHz MHz V/µs % ns ns Degrees 1.8 8 4.0 ® OPA621 –62 –80 32 80 500 15 15 25 50 VDC VDC mA °C °C °C/W °C/W SPECIFICATIONS (CONT) ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At VCC = ±5VDC, RL = 100Ω, and TA = TMIN to TMAX, unless otherwise noted. OPA621KP, KU PARAMETER TEMPERATURE RANGE Specification: KP, KU OFFSET VOLTAGE(1) Average Drift Supply Rejection CONDITIONS MIN Ambient Temperature –40 Full Temperature Range ±VCC = 4.5V to 5.5V 45 TYP MAX UNITS +85 °C ±12 60 µV/°C dB BIAS CURRENT Input Bias Current Full Temperature, VCM = 0VDC 18 40 µA OFFSET CURRENT Input Offset Current Full Temperature, VCM = 0VDC 0.2 5 µA INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN LOOP GAIN, DC Open-Loop Voltage Gain RATED OUTPUT Voltage Output POWER SUPPLY Current, Quiescent ±2.5 60 ±3.0 75 V dB RL = 100Ω RL = 50Ω 46 44 60 58 dB dB RL = 100Ω RL = 50Ω ±3.0 ±2.5 ±3.5 ±3.0 V V VIN = ±2.5VDC, VO = 0VDC IO = 0mA 26 30 mA NOTES: (1) Offset Voltage specifications are also guaranteed with units fully warmed up. (2) Parameter is guaranteed by characterization. (3) dBc = dB referred to carrier-input signal. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA621 PIN CONFIGURATION Top View DIP/SO-8 No Internal Connection 1 8 No Internal Connection Inverting Input 2 7 Positive Supply (+VCC ) Non-Inverting Input 3 6 Output Negative Supply (–VCC ) 4 5 No Internal Connection ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS OPA621 ( ) ( Supply ............................................................................................. ±7VDC Internal Power Dissipation(1) .......................... See Applications Information Differential Input Voltage ............................................................. Total VCC Input Voltage Range .................................... See Applications Information Storage Temperature Range KP, KU: ............................ –40°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C (soldering, SO-8 3s) ........................................ +260°C Output Short Circuit to Ground (+25°C) .................. Continuous to Ground Junction Temperature (TJ ) ............................................................ +175°C ) Basic Model Number Performance Grade Code K = –40°C to +85°C Package Code P = 8-pin Plastic DIP U = 8-pin Plastic SO-8 NOTE: (1) Packages must be derated based on specified θ JA. Maximum TJ must be observed. PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) OPA621KP OPA621KU 8-Pin Plastic DIP 8-Pin SO-8 006 182 ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® OPA621 4 TYPICAL PERFORMANCE CURVES Phase Shift (°) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. +10 AOL 80 0 +8 60 –45 +6 –90 Phase Gain 20 Phase Margin ≈ 50° 0 10k 100k 1M 10M 100M +2 –180 0 –90 –135 PM ≈ 50° –2 –180 1M 10M 100M Frequency (Hz) Frequency (Hz) A V = +5V/V CLOSED-LOOP SMALL-SIGNAL BANDWIDTH A V = +10V/V CLOSED-LOOP SMALL-SIGNAL BANDWIDTH +16 Gain –45 Open-Loop Phase 1G +18 AOL +22 0 +20 –45 Open-Loop Phase +10 AOL Gain Gain (dB) f –3dB ≈ 100MHz 1G +24 0 +14 +12 f –3dB ≈ 500MHz +4 –135 Phase Shift (°) 1k 0 Phase Shift (°) 40 Gain (dB) Gain –20 f –3dB ≈ 50MHz +18 –45 +16 –90 –90 Open-Loop Phase +8 PM ≈ 70° +6 1M 10M 100M –135 +14 –180 +12 –135 PM ≈ 80° –180 1M 1G 10M 100M 1G Frequency (Hz) Frequency (Hz) A V = +2V/V CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING A V = +5V/V CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING 8 8 R L = 50Ω RL = 50Ω 6 Output Voltage (Vp-p) Output Voltage (Vp-p) Gain (dB) A V = +2V/V CLOSED-LOOP SMALL-SIGNAL BANDWIDTH Phase Shift (°) Open-Loop Voltage Gain (dB) OPEN-LOOP FREQUENCY RESPONSE 4 2 0 6 4 2 0 1k 10k 100k 1M 10M 100M 1G 1k Frequency (Hz) 10k 100k 1M 10M 100M 1G Frequency (Hz) ® 5 OPA621 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE A V = +10V/V CLOSED-LOOP BANDWIDTH vs OUTPUT VOLTAGE SWING 100 8 RS = 1kΩ Voltage Noise (nV/√Hz) Output Voltage (Vp-p) RL = 50Ω 6 4 2 RS = 500Ω 10 RS = 100 Ω RS = 0 Ω 1 0.1 0 1k 10k 100k 1M 10M 100M 100 1G 1k 10k 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE INPUT CURRENT NOISE SPECTRAL DENSITY 3.1 3.1 100 10 1 0.1 2.8 Current Noise 2.5 2.5 Voltage Noise 2.2 2.2 1.9 100 1k 10k 100k 1M 10M 100M –75 –50 –25 0 +25 +50 +75 +100 Frequency (Hz) Ambient Temperature (°C) INPUT OFFSET VOLTAGE WARM-UP DRIFT INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK 1.9 +125 +1500 Offset Voltage Change (µV) +200 Offset Voltage Change (µV) 2.8 +100 0 –100 +750 TA = 25°C to 70°C Air Environment 25°C 0 –750 –1500 –200 1 0 2 3 4 5 –1 6 ® OPA621 0 +1 +2 +3 Time From Thermal Shock (min) Time From Power Turn-On (min) 6 +4 +5 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) fO = 100kHz TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. BIAS AND OFFSET CURRENT vs TEMPERATURE 0.8 24 23 0.6 21 0.4 13 0.2 Bias Current (µA) Bias Current 18 0.8 18 0.4 15 0.2 Offset Current Offset Current 8 –3 –2 –1 0 +1 +2 +3 –75 +4 –50 –25 +25 +50 +75 0 +100 +125 Ambient Temperature (°C) COMMON-MODE REJECTION vs FREQUENCY POWER SUPPLY REJECTION vs FREQUENCY 80 60 VO = 0VDC 40 20 0 80 60 + PSR 40 20 – PSR 0 –20 –20 1k 10k 100k 1M 10M 100M 1k 1G 10k 100k 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE SUPPLY CURRENT vs TEMPERATURE 80 32 75 29 Supply Current (mA) Common-Mode Rejection (dB) 0 Common-Mode Voltage (V) Power Supply Rejection (dB) Common-Mode Rejection (dB) 12 0 –4 0.6 Bias Current Offset Current (µA) 28 Offset Current (µA) Bias Current (µA) BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE VO = 0VDC 70 65 60 26 23 20 –5 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 –75 Common-Mode Voltage (V) –50 –25 0 +25 +50 +75 +100 +125 Ambient Temperature (°C) ® 7 OPA621 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. SMALL-SIGNAL TRANSIENT RESPONSE LARGE-SIGNAL TRANSIENT RESPONSE +3 Output Voltage (V) Output Voltage (mV) +50 G = +2V/V 0 RL = 50Ω CL = 15pF G = +2V/V 0 RL = 50Ω CL = 15pF –50 –3 0 25 0 50 100 Time (ns) SETTLING TIME vs OUTPUT VOLTAGE CHANGE SETTLING TIME vs CLOSED-LOOP GAIN 160 100 VO = 2V Step 140 80 120 60 Settling Time (ns) Settling Time (ns) 200 Time (ns) 0.01% 40 G = –2V/V 100 80 0.01% 60 40 20 20 0.1% 0.1% 0 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 0 –10 2 Closed-Loop Amplifier Gain (V/V) A OL , PSR, AND CMR vs TEMPERATURE 70 6 8 FREQUENCY CHARACTERISTICS vs TEMPERATURE 2.0 1.5 CMR Relative Value A OL , PSR, CMR (dB) 80 4 Output Voltage Change (V) PSR 60 A OL 50 Settling Time 1.0 Slew Rate Gain-Bandwidth 0.5 40 0 –75 –50 –25 0 +25 +50 +75 +100 +125 –75 Temperature (°C) –25 0 +25 +50 Temperature (°C) ® OPA621 –50 8 +75 +100 +125 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL = 100Ω, and TA = +25°C, unless otherwise noted. NTSC DIFFERENTIAL GAIN vs CLOSED-LOOP GAIN NTSC DIFFERENTIAL PHASE vs CLOSED-LOOP GAIN 0.5 1.0 f = 3.58MHz RL = 75Ω (Two Back-Terminated Outputs) 0.3 Differential Phase (Degrees) Differential Gain (%) 0.4 f = 3.58MHz RL = 75Ω (Two Back-Terminated Outputs) VO = 0V to 2.1V VO = 0V to 1.4V 0.2 VO = 0V to 0.7V 0.1 0 0.8 0.6 VO = 0V to 2.1V VO = 0V to 1.4V 0.4 VO = 0V to 0.7V 0.2 0 1 2 4 3 5 7 6 9 8 10 1 2 Closed-Loop Amplifier Gain (V/V) 4 5 6 8 7 9 10 Closed-Loop Amplifier Gain (V/V) LARGE-SIGNAL HARMONIC DISTORTION vs FREQUENCY SMALL-SIGNAL HARMONIC DISTORTION vs FREQUENCY –30 –40 G = +2V/V VO = 0.5Vp-p RL = 50Ω –50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 3 –60 –70 2f –80 G = +2V/V VO = 2Vp-p RL = 50Ω –40 –50 –60 2f –70 3f 3f below noise floor –90 100k 1M 10M –80 100k 100M 10M 100M Frequency (Hz) 1MHz HARMONIC DISTORTION vs POWER OUTPUT 10MHz HARMONIC DISTORTION vs POWER OUTPUT –30 –40 G = +2V/V RL = 50 Ω f C = 1MHz –50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 1M Frequency (Hz) –60 –70 2f –80 3f below noise floor –90 0.125Vp-p 0.25Vp-p 0.5Vp-p 1Vp-p G = +2V/V RL = 50 Ω f C = 10MHz –40 –50 –60 2f –70 3f –80 2Vp-p 0.125Vp-p –100 0.25Vp-p 0.5Vp-p 1Vp-p 2Vp-p –90 –20 –15 –10 –5 0 +5 +10 +15 –20 Power Output (dBm) –15 –10 –5 0 +5 +10 +15 Power Output (dBm) ® 9 OPA621 APPLICATIONS INFORMATION Grounding is the most important application consideration for the OPA621, as it is with all high-frequency circuits. Oscillations at frequencies of 500MHz and above can easily occur if good grounding techniques are not used. A heavy ground plane (2oz copper recommended) should connect all unused areas on the component side. Good ground planes can reduce stray signal pickup, provide a low resistance, low inductance common return path for signal and power, and can conduct heat from active circuit package pins into ambient air by convection. DISCUSSION OF PERFORMANCE The OPA621 provides a level of speed and precision not previously attainable in monolithic form. Unlike current feedback amplifiers, the OPA621’s design uses a “Classical” operational amplifier architecture and can therefore be used in all traditional operational amplifier applications. While it is true that current feedback amplifiers can provide wider bandwidth at higher gains, they offer many disadvantages. The asymmetrical input characteristics of current feedback amplifiers (i.e. one input is a low impedance) prevents them from being used in a variety of applications. In addition, unbalanced inputs make input bias current errors difficult to correct. Bias current cancellation through matching of inverting and non-inverting input resistors is impossible because the input bias currents are uncorrelated. Current noise is also asymmetrical and is usually significantly higher on the inverting input. Perhaps most important, settling time to 0.01% is often extremely poor due to internal design tradeoffs. Many current feedback designs exhibit settling times to 0.01% in excess of 10 microseconds even though 0.1% settling times are reasonable. Such amplifiers are completely inadequate for fast settling 12-bit applications. Supply bypassing is extremely critical and must always be used, especially when driving high current loads. Both power supply leads should be bypassed to ground as close as possible to the amplifier pins. Tantalum capacitors (1µF to 10µF) with very short leads are recommended. A parallel 0.1µF ceramic should be added at the supply pins. Surface mount bypass capacitors will produce excellent results due to their low lead inductance. Additionally, suppression filters can be used to isolate noisy supply lines. Properly bypassed and modulation-free power supply lines allow full amplifier output and optimum settling time performance. Points to Remember The OPA621’s “Classical” operational amplifier architecture employs true differential and fully symmetrical inputs to eliminate these troublesome problems. All traditional circuit configurations and op amp theory apply to the OPA621. The use of low-drift thin-film resistors allows internal operating currents to be laser-trimmed at wafer-level to optimize AC performance such as bandwidth and settling time, as well as DC parameters such as input offset voltage and drift. The result is a wideband, high-frequency monolithic operational amplifier with a gainbandwidth product of 500MHz, a 0.01% settling time of 25ns, and an input offset voltage of 200µV. 1) Don’t use point-to-point wiring as the increase in wiring inductance will be detrimental to AC performance. However, if it must be used, very short, direct signal paths are required. The input signal ground return, the load ground return, and the power supply common should all be connected to the same physical point to eliminate ground loops, which can cause unwanted feedback. WIRING PRECAUTIONS 3) Whenever possible, solder the OPA621 directly into the PC board without using a socket. Sockets add parasitic capacitance and inductance, which can seriously degrade AC performance or produce oscillations. If sockets must be used, consider using zero-profile solderless sockets such as Augat part number 8134-HC-5P2. Alternately, Teflon® standoffs located close to the amplifier’s pins can be used to mount feedback components. 2) Good component selection is essential. Capacitors used in critical locations should be a low inductance type with a high quality dielectric material. Likewise, diodes used in critical locations should be Schottky barrier types, such as HP50822835 for fast recovery and minimum charge storage. Ordinary diodes will not be suitable in RF circuits. Maximizing the OPA621’s capability requires some wiring precautions and high-frequency layout techniques. Oscillation, ringing, poor bandwidth and settling, gain peaking, and instability are typical problems plaguing all high-speed amplifiers when they are improperly used. In general, all printed circuit board conductors should be wide to provide low resistance, low impedance signal paths. They should also be as short as possible. The entire physical circuit should be as small as practical. Stray capacitances should be minimized, especially at high impedance nodes, such as the amplifier’s input terminals. Stray signal coupling from the output or power supplies to the inputs should be minimized. All circuit element leads should be no longer than 1/4 inch (6mm) to minimize lead inductance, and low values of resistance should be used. This will minimize time constants formed with the circuit capacitances and will eliminate stray, parasitic circuits. 4) Resistors used in feedback networks should have values of a few hundred ohms for best performance. Shunt capacitance problems limit the acceptable resistance range to about 1kΩ on the high end and to a value that is within the amplifier’s output drive limits on the low end. Metal film and carbon resistors will be satisfactory, but wirewound resistors (even “non-inductive” types) are absolutely unacceptable in high-frequency circuits. 5) Surface mount components (chip resistors, capacitors, etc.) have low lead inductance and are therefore strongly Teflon® E. I. Du Pont de Nemours & Co. ® OPA621 10 INPUT PROTECTION Static damage has been well recognized for MOSFET devices, but any semiconductor device deserves protection from this potentially damaging source. The OPA621 incorporates on-chip ESD protection diodes as shown in Figure 2. This eliminates the need for the user to add external protection diodes, which can add capacitance and degrade AC performance. recommended. Circuits using all surface mount components with the OPA621AU (SO-8 package) will offer the best AC performance. The parasitic package inductance and capacitance for the SO-8 is lower than the both the Cerdip and 8-lead Plastic DIP. 6) Avoid overloading the output. Remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its load. Lowest distortion is achieved with high impedance loads. 7) Don’t forget that these amplifiers use ±5V supplies. Although they will operate perfectly well with +5V and –5.2V, use of ±15V supplies will destroy the part. +VCC 8) Standard commercial test equipment has not been designed to test devices in the OPA621’s speed range. Benchtop op amp testers and ATE systems will require a special test head to successfully test these amplifiers. External Pin FIGURE 2. Internal ESD Protection. All pins on the OPA621 are internally protected from ESD by means of a pair of back-to-back reverse-biased diodes to either power supply as shown. These diodes will begin to conduct when the input voltage exceeds either power supply by about 0.7V. This situation can occur with loss of the amplifier’s power supplies while a signal source is still present. The diodes can typically withstand a continuous current of 30mA without destruction. To insure long term reliability, however, diode current should be externally limited to 10mA or so whenever possible. The internal protection diodes are designed to withstand 2.5kV (using Human Body Model) and will provide adequate ESD protection for most normal handling procedures. However, static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, static protection is strongly recommended when handling the OPA621. 10) Plug-in prototype boards and wire-wrap boards will not be satisfactory. A clean layout using RF techniques is essential; there are no shortcuts. OFFSET VOLTAGE ADJUSTMENT The OPA621’s input offset voltage is laser-trimmed and will require no further adjustment for most applications. However, if additional adjustment is needed, the circuit in Figure 1 can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier’s inverting input terminal. Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce input bias current errors to the amplifier’s offset current, which is typically only 0.2µA. 20kΩ OUTPUT DRIVE CAPABILITY The OPA621’s design uses large output devices and has been optimized to drive 50Ω and 75Ω resistive loads. The device can easily drive 6Vp-p into a 50Ω load. This highoutput drive capability makes the OPA621 an ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded. R2 RTrim 47kΩ OPA621 –VCC R1 Internal Circuitry –VCC 9) Terminate transmission line loads. Unterminated lines, such as coaxial cable, can appear to the amplifier to be a capacitive or inductive load. By terminating a transmission line with its characteristic impedance, the amplifier’s load then appears purely resistive. +VCC ESD Protection diodes internally connected to all pins. Internal current-limiting circuitry limits output current to about 150mA at 25°C. This prevents destruction from accidental shorts to common and eliminates the need for external current-limiting circuitry. Although the device can withstand momentary shorts to either power supply, it is not recommended. *R 3 = R1 || R2 VIN or Ground Output Trim Range ≅ +V CC ( R 2 ) to –V CC ( R2 ) RTrim RTrim Many demanding high-speed applications such as ADC/ DAC buffers require op amps with low wideband output impedance. For example, low output impedance is essential * R3 is optional and can be used to cancel offset errors due to input bias currents. FIGURE 1. Offset Voltage Trim. ® 11 OPA621 When the output is shorted to ground PDL = 5V x 150mA = 750mW. Thus, PD = 280mW + 750mW = 1W. Note that the short-circuit condition represents the maximum amount of internal power dissipation that can be generated. Thus, the “Maximum Power Dissipation” curve starts at 1W and is derated based on a 175°C maximum junction temperature and the junction-to-ambient thermal resistance, θJA, of each package. The variation of short-circuit current with temperature is shown in Figure 5. when driving the signal-dependent capacitances at the inputs of flash A/D converters. As shown in Figure 3, the OPA621 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. 1 250 G = +10V/V Short-Circuit Current (mA) Small-Signal Output Impedance (Ω ) 10 G = +5V/V 0.1 G = +2V/V 0.01 100 1k 100k 10k 1M 10M 100M Frequency (Hz) FIGURE 3. Small-Signal Output Impedance vs Frequency. +ISC 200 150 – ISC 100 50 –75 THERMAL CONSIDERATIONS 0 +25 +50 +75 +100 +125 FIGURE 5. Short-Circuit Current vs Temperature. CAPACITIVE LOADS The OPA621’s output stage has been optimized to drive resistive loads as low as 50Ω. Capacitive loads, however, will decrease the amplifier’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than 15pF should be buffered by connecting a small resistance, usually 5Ω to 25Ω, in series with the output as shown in Figure 6. This is particularly important when driving high capacitance loads such as flash A/D converters. 1.2 Internal Power Dissipation (W) –25 Ambient Temperature (°C) The OPA621 does not require a heat sink for operation in most environments. The use of a heat sink, however, will reduce the internal thermal rise and will result in cooler, more reliable operation. At extreme temperatures and under full load conditions a heat sink is necessary. See “Maximum Power Dissipation” curve, Figure 4. Plastic, SO-8 Packages 1.0 –50 0.8 In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance. 0.6 0.4 0.2 0 0 +25 +50 +75 +100 +125 +150 Ambient Temperature (°C) (RS typically 5Ω to 25Ω ) FIGURE 4. Maximum Power Dissipation. The internal power dissipation is given by the equation PD = PDQ + PDL, where PDQ is the quiescent power dissipation and PDL is the power dissipation in the output stage due to the load. (For ±VCC = ±5V, PDQ = 10V x 28mA = 280mW, max). For the case where the amplifier is driving a grounded load (RL) with a DC voltage (±VOUT) the maximum value of PDL occurs at ±VOUT = ±VCC/2, and is equal to PDL, max = (±VCC)2/4RL. Note that it is the voltage across the output transistor, and not the load, that determines the power dissipated in the output stage. RS OPA621 RL FIGURE 6. Driving Capacitive Loads. ® OPA621 12 CL error band of ±200µV centered around the final value of 2V. COMPENSATION The OPA621 is stable in inverting gains of ≥–2V/V and in non-inverting gains ≥+2V/V. Phase margin for both configurations is approximately 50°. Inverting and non-inverting gains of unity should be avoided. The minimum stable gains of +2V/V and –2V/V are the most demanding circuit configurations for loop stability and oscillations are most likely to occur in these gains. If possible, use the device in a noise gain greater than three to improve phase margin and reduce the susceptibility to oscillation. (Note that, from a stability standpoint, an inverting gain of –2V/V is equivalent to a noise gain of 3.) Gain and phase response for other gains are shown in the Typical Performance Curves. Settling time, specified in an inverting gain of two, occurs in only 25ns to 0.01% for a 2V step, making the OPA621 one of the fastest settling monolithic amplifiers commercially available. Settling time increases with closed-loop gain and output voltage change as described in the Typical Performance Curves. Preserving settling time requires critical attention to the details as mentioned under “Wiring Precautions.” The amplifier also recovers quickly from input overloads. Overload recovery time to linear operation from a 50% overload is typically only 30ns. In practice, settling time measurements on the OPA621 prove to be very difficult to perform. Accurate measurement is next to impossible in all but the very best equipped labs. Among other things, a fast flat-top generator and high speed oscilloscope are needed. Unfortunately, fast flat-top generators, which settle to 0.01% in sufficient time, are scarce and expensive. Fast oscilloscopes, however, are more commonly available. For best results a sampling oscilloscope is recommended. Sampling scopes typically have bandwidths that are greater than 1GHz and very low capacitance inputs. They also exhibit faster settling times in response to signals that would tend to overload a real-time oscilloscope. The high-frequency response of the OPA621 in a good layout is flat with frequency for higher-gain circuits. However, low-gain circuits and configurations where large feedback resistances are used, can produce high-frequency gain peaking. This peaking can be minimized by connecting a small capacitor in parallel with the feedback resistor. This capacitor compensates for the closed-loop, high frequency, transfer function zero that results from the time constant formed by the input capacitance of the amplifier (typically 2pF after PC board mounting), and the input and feedback resistors. The selected compensation capacitor may be a trimmer, a fixed capacitor, or a planned PC board capacitance. The capacitance value is strongly dependent on circuit layout and closed-loop gain. Using small resistor values will preserve the phase margin and avoid peaking by keeping the break frequency of this zero sufficiently high. When high closed-loop gains are required, a three-resistor attenuator (tee network) is recommended to avoid using large value resistors with large time constants. Figure 7 shows the test circuit used to measure settling time for the OPA621. This approach uses a 16-bit sampling oscilloscope to monitor the input and output pulses. These waveforms are captured by the sampling scope, averaged, and then subtracted from each other in software to produce the error signal. This technique eliminates the need for the traditional “false-summing junction,” which adds extra parasitic capacitance. Note that instead of an additional flattop generator, this technique uses the scope’s built-in calibration source as the input signal. SETTLING TIME DIFFERENTIAL GAIN AND PHASE Differential Gain (DG) and Differential Phase (DP) are among the more important specifications for video applications. DG is defined as the percent change in closed-loop gain over a specified change in output voltage level. DP is Settling time is defined as the total time required, from the input signal step, for the output to settle to within the specified error band around the final value. This error band is expressed as a percentage of the value of the output transition, a 2V step. Thus, settling time to 0.01% requires an 1pF to 4pF (Adjust for Optimum Settling) 0 to +2V, f = 1.25MHz 100Ω 200Ω VIN +5VDC 0 to –2V VOUT OPA621 NOTE: Test fixture built using all surface-mount components. Ground plane used on component side and entire fixture enclosed in metal case. Both power supplies bypassed with 10µF Tantalum || 0.01µF ceramic capacitors. It is directly connected (without cable) to TIME CAL trigger source on Sampling Scope (Data Precision's Data 6100 with Model 640-1 plug-in). Input monitored with Active Probe (Channel 1). 200Ω –5VDC To Active Probe (Channel 2) on sampling scope. FIGURE 7. Settling Time Test Circuit. ® 13 OPA621 defined as the change in degrees of the closed-loop phase over the same output voltage change. Both DG and DP are specified at the NTSC sub-carrier frequency of 3.58MHz. DG and DP increase with closed-loop gain and output voltage transition as shown in the Typical Performance Curves. All measurements were performed using a Tektronix model VM700 Video Measurement Set. 60 RL = 400Ω Intercept Point (+dBm) 55 DISTORTION The OPA621’s Harmonic Distortion characteristics into a 50Ω load are shown vs frequency and power output in the Typical Performance Curves. Distortion can be further improved by increasing the load resistance as illustrated in Figure 8. Remember to include the contribution of the feedback resistance when calculating the effective load resistance seen by the amplifier. 50 45 RL = 100 Ω 40 35 RL = 50 Ω 30 250Ω 250Ω 25 POUT – + 20 15 RL G = +2V/V 10 0 10 20 30 40 50 60 70 80 90 100 Frequency (MHz) FIGURE 9. Two-Tone Third-Order Intermodulation Intercept vs Frequency. For this case OPI3P = 47dBm, PO = 4dBm, and the thirdorder IMD = 2(47 – 4) = 86dB below either 4dBm tone. The OPA621’s low IMD makes the device an excellent choice for a variety of RF signal processing applications. 10MHz HARMONIC DISTORTION vs LOAD RESISTANCE –40 Harmonic Distortion (dBc) VO = 2Vp-p –50 NOISE FIGURE The OPA621’s voltage and current noise spectral densities are specified in the Typical Performance Curves. For RF applications, however, Noise Figure (NF) is often the preferred noise specification since it allows system noise performance to be more easily calculated. The OPA621’s Noise Figure vs Source Resistance is shown in Figure 10. –60 2f G = +2V/V –70 G = +5V/V –80 3f –90 0 100 200 300 400 500 SPICE MODELS Load Resistance (Ω) Computer simulation using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model using MicroSim Corporation’s PSpice is available for the OPA621. This simulation model is available through the Burr-Brown web site at www.burr-brown.com or by calling the BurrBrown Applications Department. FIGURE 8. 10MHz Harmonic Distortion vs Load Resistance. Two-tone, third-order intermodulation distortion (IM) is an important parameter for many RF amplifier applications. Figure 9 shows the OPA621’s two-tone, third-order IM intercept vs frequency. For these measurements, tones were spaced 1MHz apart. This curve is particularly useful for determining the magnitude of the third-order IM products as a function of frequency, load resistance, and gain. For example, assume that the application requires the OPA621 to operate in a gain of +2V/V and drive 2Vp-p (4dBm for each tone) into 50Ω at a frequency of 10MHz. Referring to Figure 9 we find that the intercept point is +47dBm. The magnitude of the third-order IM products can now be easily calculated from the expression: NOISE FIGURE vs SOURCE RESISTANCE 25 NF (dB) 20 Third IMD = 2(OPI3P – PO) where OPI3P = third-order output intercept, dBm PO = output level/tone, dBm/tone Third IMD = third-order intermodulation ratio below each output tone, dB NFdB = 10log 1 + en2 + (inRS)2 4kTRS 15 10 5 0 10 100 1k 10k Source Resistance (Ω ) FIGURE 10. Noise Figure vs Source Resistance. ® OPA621 14 100k RELIABILITY DATA Extensive reliability testing has been performed on the OPA621. Accelerated life testing (2000 hours) at maximum operating temperature was used to calculate MTTF at an ambient temperature of 25°C. These test results yield MTTF of: DIP = 5.02E+7 Hours, and SO-8 = 2.94E+7 Hours. Additional tests such as PCT have also been performed. Reliability reports are available upon request for each of the package options offered. R3 R1 ENVIRONMENTAL (Q) SCREENING 15.8kΩ R5 158Ω 1000pF R2 158Ω FIGURE 12. High-Q 1MHz Bandpass Filter +5V (–) D D *J1 *J2 S S 2N5911 METHOD Burn-In Test 7 2 Temperature = 125°C, 24 hrs Temperature Cycling VOUT OPA621 C1 1000pF Burr-Brown QC4118 Stabilization Bake C2 fC = 1MHz BW = 20kHz at –3dB Q = 50 (+) Internal Visual 2kΩ R4 2kΩ VIN The inherent reliability of a semiconductor device is controlled by the design, materials and fabrication of the device—it cannot be improved by testing. However, the use of environmental screening can eliminate the majority of those units which would fail early in their lifetimes (infant mortality) through the application of carefully selected accelerated stress levels. Burr-Brown “Q-Screening” provides environmental screening to our standard industrial products, thus enhancing reliability. The screening illustrated in the following table is performed to selected levels similar to those of MIL-STD-883. SCREEN OPA621 3 Temperature = –55°C to 125°C, 10 cycles OPA621 6 VOUT 4 Temperature = 125°C, 160 hrs minimum Hermetic Seal Fine: He leak rate < 1 X 10 atm cc/s Gross: per Fluorocarbon bubble test Electrical Tests As described in specifications tables. External Visual Burr-Brown QC5150 *R1 2kΩ *R2 2kΩ –5V Minimum Stable Gain : ≥ ±2V/V IB : 1pA eN : 6nV/√Hz at 1MHz Gain-Bandwidth : 500MHz Feedback from pin 6 to the (–) Slew Rate : 500 V/µs FET input required for stability. Settling Time : 18ns to 0.1% * Select J1, J2 and R1, R2 to set input stage current for optimum performance. NOTE: Q-Screening is available on SG package only. DEMONSTRATION BOARDS Demonstration boards are available to speed protyping. The 8-pin DIP packaged parts may be evaluated using the DEMOPA65XP board while the SO-8 packaged part may be evaluated using the DEM-OPA65XU board. Both of these boards come partially assembled from your local distributor (the external resistors or the amplifier is not included). FIGURE 13. Low Noise, Wideband FET Input Op Amp. APPLICATIONS 249Ω 249Ω OPA621 RF 249Ω 249Ω 249Ω OPA621 Differential Input OPA621 249Ω SingleEnded Output 249Ω RG 499Ω 249Ω RF 249Ω 249 Ω OPA621 FIGURE 14. Differential Input Buffer Amplifier (G = –2V/V). FIGURE 11. Unity Gain Difference Amplifier. ® 15 OPA621 390Ω 390Ω 75Ω Transmission Line 75Ω VOUT OPA621 Video Input 75Ω 75Ω 75Ω VOUT 75Ω Bandwidth, —3dB = 500MHz 75Ω VOUT High output current drive capability (6Vp-p into 50Ω) allows three back-terminated 75Ω transmission lines to be simultaneously driven. 75Ω FIGURE 15. Video Distribution Amplifier. ® OPA621 16