® PCM3000 PCM3001 PCM 49% 300 1E FPO PCM 300 0E For most current data sheet and other product information, visit www.burr-brown.com Stereo Audio CODEC 18-BITS, SERIAL INTERFACE TM FEATURES DESCRIPTION ● MONOLITHIC 18-BIT ∆Σ ADC AND DAC The PCM3000/3001 is a low cost single chip stereo audio CODEC (analog-to-digital and digital-to-analog converter) with single-ended analog voltage input and output. ● 16- OR 18-BIT INPUT/OUTPUT DATA ● STEREO ADC: Single-ended Voltage Input 64X Oversampling High Performance: –88dB THD+N 94dB SNR 94dB Dynamic Range Digital High-Pass Filter Both ADCs and DACs employ delta-sigma modulation with 64X oversampling. The ADCs include a digital decimation filter and the DACs include an 8X oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection and soft mute to form a complete subsystem. The PCM3000/3001 operates with leftjustified, right-justified, I2S or DSP data formats. ● STEREO DAC: Single-ended Voltage Output Analog Low Pass Filter 64X Oversampling High Performance: –90dB THD+N 98dB SNR 97dB Dynamic Range PCM3000 can be programmed with a 3-wire serial interface for special features and data formats. PCM3001 can be pin-programmed for data formats. Fabricated on a highly advanced CMOS process, the PCM3000/3001 is suitable for a wide variety of costsensitive consumer applications where good performance is required. Applications include sampling keyboards, digital mixers, mini-disc recorders, hard-disk recorders, karaoke systems, DSP-based car stereo, DAT recorders, and video conferencing. ● SPECIAL FEATURES (PCM3000): Digital De-emphasis Digital Attenuation (256 Steps) Soft Mute Analog Loop Back ● SAMPLE RATE: Up to 48kHz ● SYSTEM CLOCK: 256fS, 384fS, 512fS ● SINGLE +5V POWER SUPPLY ● SMALL PACKAGE: SSOP-28 Lch In Analog Front-End Rch In Lch Out Rch Out Low Pass Filter and Output Buffer Delta-Sigma Modulator Multi-Level Delta-Sigma Modulator Digital Decimation Filter Digital Interpolation Filter Digital Out Serial Interface and Mode Control Digital In Mode Control System Clock International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1996 Burr-Brown Corporation PDS-1342E 1 Printed in U.S.A., January, 2000 PCM3000/3001 SPECIFICATIONS All specifications at +25°C, V DD = VCC = +5V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted. PCM3000E/3001E PARAMETER CONDITIONS MIN DIGITAL INPUT/OUTPUT Input Logic Input Logic Level: VIH(1) VIL(1) Input Logic Current: IIN(2) Input Logic Current: IIN(3) Input Logic Level: VIH(4) VIL(4) Input Logic Current: IIN(4) Output Logic Output Logic Level: VOH(5) VOL(5) Output Logic Level: VOH(6) VOL(6) CLOCK FREQUENCY Sampling Frequency (fS) System Clock Frequency TYP MAX 2.0 0.8 ±1 –120 0.64 • VDD 0.28 • VDD ±40 IOUT IOUT IOUT IOUT = = = = –1.6mA +3.2mA –3.2mA +3.2mA 4.5 0.5 48 12.2880 18.4320 24.5760 kHz MHz MHz MHz 4.5 44.1 11.2896 16.9344 22.5792 VDC VDC µA µA VDC VDC µA VDC VDC VDC VDC 0.5 32(7) 8.1920 12.2880 16.3840 256fS 384fS 512fS UNITS ADC CHARACTERISTICS RESOLUTION 18 DC ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift DYNAMIC PERFORMANCE(9) THD+N: VIN = –0.5dB VIN = –60dB Dynamic Range Signal-to-Noise Ratio Channel Separation ±1.0 ±2.0 ±20 ±1.7 ±20 ±5.0 ±5.0 % of FSR % of FSR ppm of FSR/°C %of FSR ppm of FSR/°C –88 –31 94 94 92 –80 dB dB dB dB dB 0.454fS 17.4/fS Hz Hz dB dB sec 0.019fS mHz 0dB (Full Scale) 2.9 2.1 15 Vp-p V kΩ CEXT = 470pF 170 kHz High-Pass Filter Off(8) High-Pass Filter Off(8) f= f= f = 1kHz, f = 1kHz, 1kHz 1kHz A-Weighted A-Weighted DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time (Latency) ANTI-ALIASING FILTER –3dB Frequency 90 90 88 0.583fS ±0.05 –65 DIGITAL HIGH PASS FILTER RESPONSE –3dB Frequency ANALOG INPUT Voltage Range Center Voltage Input Impedance Bits NOTES: (1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB. (2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN, CLKIO (Schmitt Trigger Input). (3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt Trigger Input, 70kΩ Internal Pull-Up Resistor). (4) Pin 20: XTI. (5) Pins 19, 22: DOUT,CLKIO. (6) Pin 21: XTO. (7) Refer to Application Bulletin AB-148 for information relating to operation at lower sampling frequencies. (8) High Pass Filter disabled (PCM3000 only) to measure DC offset. (9) fIN = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (10) With no load on XTO and CLKIO. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM3000/3001 2 SPECIFICATIONS (cont.) All specifications at +25°C, V DD = VCC = 5V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted. PCM3000E/3001E PARAMETER CONDITIONS MIN TYP MAX UNITS DAC CHARACTERISTICS RESOLUTION 18 Bits DC ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift ±1.0 ±1.0 ±20 ±1.0 ±20 ±5.0 ±5.0 % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C DYNAMIC PERFORMANCE(9) THD+N: VOUT = 0dB (Full Scale) VOUT = –60dB Dynamic Range Signal-to-Noise Ratio (Idle Channel) Channel Separation –90 –34 97 98 95 –80 dB dB dB dB dB 0.445fS Hz Hz dB dB sec EIAJ A-Weighted EIAJ A-Weighted 90 92 90 DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time 0.555f S ±0.17 –35 11.1/fS ANALOG OUTPUT Voltage Range Center Voltage Load Impedance ANALOG LOW PASS FILTER Frequency Response AC Load Vp-p VDC kΩ –0.16 dB 5 f = 20kHz POWER SUPPLY REQUIREMENTS Voltage Range: VCC VDD Supply Current: +ICC, +IDD(10) Power Dissipation 0.62 • VCC 0.5 • VCC 4.5 4.5 VCC = VDD = 5V VCC = VDD = 5V TEMPERATURE RANGE Operation Storage –25 –55 5 5 32 160 5.5 5.5 50 250 VDC VDC mA mW +85 +125 °C °C PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER PCM3000E " PCM3001E " SSOP-28 " SSOP-28 " 324 " 324 " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA –25°C to +85°C " –25°C to +85°C " PCM3000E " PCM3001E " PCM3000E PCM3000E/2K PCM3001E PCM3001E/2K Rails Tape and Reel Rails Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM3000E/2K” will get a single 2000-piece Tape and Reel. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage +VDD, +VCC1, +VCC2 ...................................................................... +6.5V Supply Voltage Differences ............................................................... ±0.1V GND Voltage Differences .................................................................. ±0.1V Digital Input Voltage ...................................................... –0.3 to VDD + 0.3V Analog Input Voltage ......................................... –0.3 to VCC1, VCC2 + 0.3V Power Dissipation .......................................................................... 300mW Input Current ................................................................................... ±10mA Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C (reflow, 10s) ..................................................... +235°C Thermal Resistance, θJA .............................................................. 100°C/W This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® 3 PCM3000/3001 PIN CONFIGURATION—PCM3000 Top View PIN CONFIGURATION—PCM3001 SSOP 1 VINL 2 Top View RSTB 28 1 VINL RSTB 28 VCC1 ML 27 2 VCC1 FMT0 27 3 AGND1 MD 26 3 AGND1 FMT1 26 4 VREFL MC 25 4 VREFL FMT2 25 5 VREFR DGND 24 5 VREFR DGND 24 6 VINR VDD 23 6 VINR 7 CINPR CLKIO 22 7 CINPR CLKIO 22 8 CINNR XTO 21 8 CINNR XTO 21 9 CINNL XTI 20 9 CINNL XTI 20 10 CINPL DOUT 19 10 CINPL DOUT 19 11 VCOM DIN 18 11 VCOM DIN 18 12 VOUTR BCKIN 17 12 VOUTR BCKIN 17 13 AGND2 LRCIN 16 13 AGND2 LRCIN 16 14 VCC2 VOUTL 15 14 VCC2 VOUTL 15 PIN ASSIGNMENTS PCM3000/3001 PIN NAME I/O DESCRIPTION VINL IN ADC Analog Input, Lch 2 VCC1 — ADC Analog Power Supply 3 AGND1 — ADC Analog Ground 4 VREFL — ADC Input Reference, Lch 5 VREFR — ADC Input Reference, Rch 6 VINR IN ADC Analog Input, Rch 1 SSOP 7 CINPR — ADC Anti-alias Filter Capacitor (+), Rch 8 C INNR — ADC Anti-alias Filter Capacitor (–), Rch ADC Anti-alias Filter Capacitor (–), Lch 9 CINNL — 10 CINPL — ADC Anti-alias Filter Capacitor (+), Lch 11 VCOM — DAC Output Common 12 VOUTR OUT 13 AGND2 — DAC Analog Ground DAC Analog Power Supply DAC Analog Output, Rch 14 VCC2 — 15 VOUTL OUT 16 LRCIN IN Sample Rate Clock Input (fS)(2) 17 BCKIN IN Bit Clock Input(2) 18 DIN IN Data Input(2) 19 DOUT OUT Data Output 20 XTI IN 21 XTO OUT 22 CLKIO I/O DAC Analog Output, Lch Oscillator Input Oscillator Output Buffered Output of Oscillator or External Clock Input(2) 23 VDD — Digital Power Supply 24 DGND — Digital Ground 25 MC/FMT2 IN Serial Control Bit Clock (PCM3000)/Data Format Control 2 (PCM3001)(1, 2) 26 MD/FMT1 IN Serial Control Data (PCM3000)/Data Format Control 1 (PCM3001)(1, 2) 27 ML/FMT0 IN Serial Control Strobe Pulse/Data Format Control 0 (PCM3001)(1, 2) 28 RSTB IN Reset(1, 2) NOTES: (1) With 70kΩ typical internal pull-up resistor. (2) Schmitt trigger input. ® PCM3000/3001 4 VDD 23 TYPICAL PERFORMANCE CURVES ADC SECTION At TA = +25°C, VCC = VDD = +5V, fIN = 1.0kHz, fS = 44.1kHz, 18-bit data, V IN = 2.9Vp-p, and SYSCLK = 384fS, unless otherwise noted. THD+N vs TEMPERATURE THD+N vs POWER SUPPLY 0.01 4.0 0.01 4.0 2.0 0dB 0.004 0.002 –25 1.0 THD+N at 0dB (%) 0.006 0 0 25 50 75 85 0.008 3.0 0.006 2.0 0dB 0.004 1.0 0.002 THD+N at –60dB (%) –60dB 3.0 THD+N at –60dB (%) THD+N at 0dB (%) –60dB 0.008 0 100 4.5 4.75 5.0 Temperature (°C) 5.25 5.5 VCC (V) THD+N vs SYSTEM CLOCK and SAMPLING FREQUENCY 0.01 SNR and DYNAMIC RANGE vs POWER SUPPLY 4.0 98 98 3.0 96 96 48kHz 0.004 1.0 Dynamic Range 94 94 SNR 92 92 Dynamic Range (dB) 2.0 48kHz SNR (dB) 0.006 THD+N at –60dB (%) –60dB 0dB 44.1kHz 0.002 90 0 384fS 90 4.5 512fS 4.75 5.0 5.25 5.50 VCC (V) System Clock THD+N vs OUTPUT DATA RESOLUTION 0.01 4.0 –60dB 0.008 3.0 0.006 2.0 0.004 1.0 THD+N at –60dB (%) 256fS THD+N at 0dB (%) THD+N at 0dB (%) 44.1kHz 0.008 0dB 0.002 0 16-Bit 18-Bit Resolution ® 5 PCM3000/3001 TYPICAL PERFORMANCE CURVES DAC SECTION At TA = +25°C, VCC = VDD = +5V, fIN = 1.0kHz, fS = 44.1kHz, 18-bit data, and SYSCLK = 384fS, unless otherwise noted. 4.0 0.008 3.0 0.008 3.0 0.006 2.0 0.004 1.0 THD+N at 0dB (%) –60dB THD+N at –60dB (%) 0.01 –60dB 0.006 2.0 0.004 1.0 0dB 0.002 –25 0dB 0.002 0 0 25 50 75 85 0 4.5 100 4.75 5.0 5.25 5.5 Temperature (°C) VCC (V) SNR and DYNAMIC RANGE vs POWER SUPPLY THD+N vs SYSTEM CLOCK and SAMPLING FREQUENCY 100 100 0.01 4.0 98 0.008 3.0 96 SNR 94 94 48kHz 0.006 2.0 –60dB 48kHz 44.1kHz 0.004 1.0 0dB 44.1kHz 92 92 4.5 4.75 5.0 5.25 0.002 5.50 0 384fS 256fS VCC (V) System Clock 4.0 0.008 3.0 –60dB 0.006 2.0 0.004 1.0 0dB 0.002 0 16-Bit 18-Bit Resolution ® PCM3000/3001 6 THD+N at –60dB (%) THD+N at 0dB (%) THD+N vs INPUT DATA RESOLUTION 0.01 512fS THD+N at –60dB (%) 96 THD+N at 0dB (%) 98 Dynamic Range (dB) Dynamic Range SNR (dB) THD+N at 0dB (%) 4.0 THD+N at –60dB (%) THD+N vs POWER SUPPLY THD+N vs TEMPERATURE 0.01 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, and SYSCLK = 384fS, unless otherwise noted. ADC DIGITAL FILTER OVERALL CHARACTERISTICS STOPBAND ATTENUATION CHARACTERISTICS 0 0 –20 Amplitude (dB) Amplitude (dB) –50 –100 –40 –60 –150 –80 –200 –100 0 8 16 24 32 0 0.25 Normalized Frequency (x fS Hz) PASSBAND RIPPLE CHARACTERISTICS 0.75 1.00 HIGH PASS FILTER RESPONSE 0.2 0.2 0.0 0.0 –0.2 –0.2 Amplitude (dB) Amplitude (dB) 0.50 Normalized Frequency (x fS Hz) –0.4 –0.6 –0.8 –0.4 –0.6 –0.8 –1.0 –1.0 0 0.125 0.250 0.375 0.500 0 1 Normalized Frequency (x fS Hz) 2 3 4 Normalized Frequency (x fS /1000 Hz) ANTI-ALIASING FILTER ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE (CEXT = 470pF, 1000pF) 0.2 ANTI-ALIASING FILTER OVERALL FREQUENCY RESPONSE (CEXT = 470pF, 1000pF) 0 470pF 470pF –10 –0.2 Amplitude (dB) Amplitude (dB) 0.0 –0.4 1000pF –0.6 –20 –30 1000pF –40 –0.8 –50 –1.0 0 10 100 1k 10k 0 100k 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) ® 7 PCM3000/3001 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, and SYSCLK = 384fS, unless otherwise noted. DAC DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC PASSBAND RIPPLE CHARACTERISTIC 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –100 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS –1 4.0815fS 0 0.1134fS Frequency (Hz) 5k 10k 15k 20k 25k 0 3628 7256 15k 20k 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 25k 0 4999.8375 Frequency (Hz) 10k 15k 14999.5125 19999.35 DE-EMPHASIS ERROR (48kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 5k 9999.675 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 0 14512 DE-EMPHASIS ERROR (44.1kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 10k 10884 Frequency (Hz) 0 –2 –4 –6 –8 –10 –12 5k 0.4535fS 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 0.3402fS DE-EMPHASIS ERROR (3kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (3kHz) 0 –2 –4 –6 –8 –10 –12 0 0.2268fS Frequency (Hz) 20k 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 25k 5442 10884 Frequency (Hz) 16326 21768 Frequency (Hz) ANALOG OUTPUT FILTER INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0 dB dB 0.5 0 –0.5 –1.0 20 100 1k Frequency (Hz) 10k 10 24k 100 1k 10k 100k Frequency (Hz) ® PCM3000/3001 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 8 1M 10M BLOCK DIAGRAM CINPL CINNL (+) Analog Front-End Circuit VINL Decimation and High Pass Filter Delta-Sigma Modulator (–) LRCIN BCKIN VREFL Serial Data Interface ADC Reference VREFR DIN (–) Analog Front-End Circuit VINR Decimation and High Pass Filter Delta-Sigma Modulator (+) DOUT CINNR Loop Control CINPR Analog Low-Pass Filter VOUTL Multi-Level Delta-Sigma Modulator ML (FMT0)(1) Interpolation Filter 8X Oversampling Mode Control Interface DAC VCOM Analog Low-Pass Filter VOUTR Multi-Level Delta-Sigma Modulator MC (FMT2)(1) MD (FMT1)(1) Interpolation Filter 8X Oversampling Reset Power Supply AGND2 VCC2 AGND1 VCC1 RSTB Clock/OSC Manager DGND CLKIO VDD XTO XTI NOTE: (1) FMT0, FMT1, FMT2 are for PCM3001 only. 470pF CINPL 10 2.2µF + 1 VINL 1kΩ 4.7µF CINNL 15kΩ 1kΩ 4 9 (+) (–) Delta-Sigma Modulator VREFL + VREF FIGURE 1. Analog Front-End (Single-Channel). ® 9 PCM3000/3001 PCM AUDIO INTERFACE The three-wire digital audio interface for PCM3000/3001 is on LRCIN (Pin 16), BCKIN (Pin 17), DIN (Pin 18), and DOUT (Pin 19). The PCM3000/3001 can operate with seven different data formats. For the PCM3000, these formats are selected through PROGRAM REGISTER 3 in the software mode. For PCM3001, data formats are selected by pin-strapping the three format pins. Figures 2, 3 and 4 illustrate audio data input/output format and timing. PCM3000/3001 can accept 32, 48, or 64 bit clocks (BCKIN) in one clock of LRCIN. Only formats 0, 2, and 6 can be selected when 32 bit clocks/LRCIN are applied. FORMAT 0: FMT[2:0] = “000” DAC: 16-Bit, MSB-First, Right-Justified L–ch LRCIN R–ch BCKIN 16 DIN 1 2 3 14 15 16 MSB 1 LSB 2 3 14 15 16 MSB LSB ADC: 16-Bit, MSB-First, Left-Justified LRCIN L–ch R–ch BCKIN 1 DOUT 2 3 14 15 16 MSB 1 LSB 2 3 14 15 16 MSB 1 LSB FORMAT 1: FMT[2:0] = “001” DAC: 18-Bit, MSB-First, Right-Justified L–ch LRCIN R–ch BCKIN 18 DIN 1 2 3 16 17 18 MSB 1 LSB 2 3 16 17 18 MSB LSB ADC: 18-Bit, MSB-First, Left-Justified LRCIN L–ch R–ch BCKIN DOUT 1 2 16 17 18 3 1 LSB MSB 2 3 1 16 17 18 LSB MSB FORMAT 2: FMT[2:0] = “010” DAC: 16-Bit, MSB-First, Right-Justified L–ch LRCIN R–ch BCIN 16 DIN 2 1 3 MSB 14 15 16 1 LSB 2 3 MSB 14 15 16 LSB ADC: 16-Bit, MSB-First, Right-Justified LRCIN L–ch R–ch BCIN 16 DOUT 1 2 3 MSB 14 15 16 LSB FIGURE 2. Audio Data Input/Output Format. ® PCM3000/3001 10 1 2 MSB 3 14 15 16 LSB FORMAT 3: FMT[2:0] = "011" DAC: 18-Bit, MSB-First, Right-Justified LRCIN R-ch L-ch BCKIN DIN 18 2 1 3 16 17 18 1 LSB MSB 2 3 16 17 18 MSB LSB ADC: 18-Bit, MSB-First, Right-Justified LRCIN R-ch L-ch BCKIN DOUT 18 1 2 3 16 17 18 MSB 1 LSB 2 3 16 17 18 MSB LSB FORMAT 4: FMT[2:0] = "100 " DAC: 18-Bit, MSB-First, Left-Justified LRCIN R-ch L-ch BCKIN 1 DIN 2 3 16 17 18 MSB 1 2 3 16 17 18 MSB LSB 1 LSB ADC: 18-Bit, MSB-First, Left-Justified LRCIN R-ch L-ch BCKIN DOUT 1 2 16 17 18 3 1 LSB 2 3 1 16 17 18 LSB MSB FORMAT 5: FMT[2:0] = "101" DAC: 18-Bit, MSB-First, I2S L_ch LRCIN R-ch BCKIN 1 DIN 2 3 16 17 18 MSB ADC: 18-Bit, MSB-First, 1 2 3 16 17 18 MSB LSB LSB I2S L-ch LRCIN R-ch BCKIN 1 DOUT 2 3 16 17 18 1 LSB MSB 2 3 16 17 18 MSB LSB FORMAT 6: FMT[2:0] = "110" DAC: 16-Bit, MSB-First, DSP-Frame L-ch LRCIN R-ch BCKIN DIN 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 LSB MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 LSB MSB ADC: 16-Bit, MSB-First, DSP-Frame L-ch LRCIN R-ch BCKIN DOUT 16 1 2 3 4 5 6 7 8 MSB 9 10 11 12 13 14 15 16 LSB 1 2 MSB 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 LSB FIGURE 3. Audio Data Input/Output Format. ® 11 PCM3000/3001 tLRP 1.4V LRCIN tBL tBCH tLB tBCL 1.4V BCKIN tBCY tDIS tDIH 1.4V DIN tLDO tBDO DOUT 0.5 x VDD BCKIN Pulse Cycle Time tBCY 300ns (min) BCKIN Pulse Width High t BCH 120ns (min) BCKIN Pulse Width Low tBCL 120ns (min) BCKIN Rising Edge to LRCIN Edge tBL 40ns (min) LRCIN Edge to BCKIN Rising Edge tLB 40ns (min) LRCIN Pulse Width tLRP tBCY (min) DIN Set-up Time tDIS 40ns (min) DIN Hold Time t DIH 40ns (min) DOUT Delay Time to BCKIN Falling Edge tBDO 40ns (max) DOUT Delay Time to LRCIN Edge tLDO 40ns (max) Rising Time of All Signals tRISE 20ns (max) Falling Time of All Signals tFALL 20ns (max) FIGURE 4. Audio Data Input/Output Timing. SYSTEM CLOCK 256fS, 384fS, or 512fS. When a 384fS or 512fS system clock is used, the clock is divided into 256fS automatically. The 256fS clock is used to operate the digital filters and the modulators. The system clock for the PCM3000/3001 must be either 256fS, 384fS or 512fS, where fS is the audio sampling frequency. The system clock can be either a crystal oscillator placed between XTI (Pin 20) and XTO (Pin 21), or an external clock input. If an external clock is used, the clock is provided to either XTI or CLKIO (Pin 22), and XTO is open. The PCM3000/3001 has an XTI clock detection circuit which senses if an XTI clock is operating. When the external clock is delivered to XTI, CLKIO is a buffered output of XTI. When XTI is connected to ground, the external clock must be tied to CLKIO. For best performance, the “External Clock Input 2” circuit in Figure 5 is recommended. Table I lists the relationship of typical sampling frequencies and system clock frequencies, and Figures 5 and 6 illustrate the typical system clock connections and external system clock timing. SAMPLING RATE FREQUENCY (kHz) 32 The PCM3000/3001 also has a system clock detection circuit which automatically senses if the system clock is operating at 256fS 384fS 512fS 8.1920 12.2880 16.3840 44.1 11.2896 16.9340 22.5792 48 12.2880 18.4320 24.5760 TABLE I. System Clock Frequencies. ® PCM3000/3001 SYSTEM CLOCK FREQUENCY (MHz) 12 CLKIO 256fS Internal System Clock Clock Divider C1 X’tal XTI R C2 XTO C1 = C2 = 10 to 33pF PCM3000/3001 CRYSTAL RESONATOR CONNECTION (X’tal must be fundamental made, parallel resonant) CLKIO External Clock (TTL I/F) CLKIO 256fS Internal System Clock 256fS Internal System Clock Clock Divider External Clock (CMOS I/F) Clock Divider XTI XTI R R XTO XTO PCM3000/3001 PCM3000/3001 EXTERNAL CLOCK INPUT 1: (XTO is open) EXTERNAL CLOCK INPUT 2: (XTO is open) FIGURE 5. System Clock Connections. tCLKIH tCLKIL XTI CLKIO 3.2V 2.0V 1.4V 0.8V XTI or CLKIO System Clock Pulse Width High tCLKIH 12ns (min) System Clock Pulse Width Low tCLKIL 12ns (min) FIGURE 6. External System Clock Timing. ® 13 PCM3000/3001 EXTERNAL RESET The PCM3000 and PCM3001 include a reset input, RSTB (pin 28). As shown in Figure 8, the external reset signal must drive RSTB low for a minimum of 40 nanoseconds while system clock is active in order to initiate the reset sequence. Initialization starts on the rising edge of RSTB, and requires 1024 system clock cycles for completion. Figure 10 shows the state of the DAC and ADC outputs during and after the reset sequence. POWER-ON RESET Both the PCM3000 and PCM3001 have internal power-on reset circuitry. Power-on reset occurs when system clock (XTI or CLKIO) is active and VDD > 4.0V. For the PCM3001, the system clock must complete a minimum of 3 complete cycles prior to VDD > 4.0V to ensure proper reset operation. The initialization sequence requires 1024 system cycles for completion, as shown in Figure 7. Figure 10 shows the state of the DAC and ADC outputs during and after the reset sequence. 4.4V 4.0V 3.6V VDD Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock (XTI or CLKIO) FIGURE 7. Internal Power-On Reset Timing. tRST = 40ns minimum RSTB tRST Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock (XTI or CLKIO) FIGURE 8. External Forced Reset Timing. ML MC MD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 FIGURE 9. Control Data Input Format. ® PCM3000/3001 14 to LRCIN. Internal operation of the ADC will also stop with 1/fS, and the digital output codes will be set to bipolar zero until re-synchronization occurs. If LRCIN is synchronized with 5 or less bit clocks to the system clock, operation will be normal. SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM PCM3000/3001 operates with LRCIN synchronized to the system clock. The CODEC does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization. If the synchronization between the system clock and LRCIN changes more than 6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC will stop within 1/fS, and the analog output will be forced to bipolar zero (VCC/2) until the system clock is re-synchronized Figure 11 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero (<1/fS seconds), the outputs are not defined and some noise may occur. During the transitions between normal data and undefined states, the output has discontinuities, which will cause output noise. Reset Removal or Power-Down(1) OFF Internal Reset Reset 32/fS VCOM DAC VOUT (= 1/2 x VCC2) 4096/fS ADC DOUT Zero (2) NOTES: (1) Power-Down is for PCM3000 only. (2) The HPF transient response (exponentially attenuationed signal with 200ms time constant) appears intially. FIGURE 10. DAC Output and ADC Output for Reset and Power-Down. State of Synchronization Synchronous Asynchronous Synchronous within 1/fS 22.2/fS Undefined Data DAC VOUT VCOM (= 1/2 x VCC2) Undefined Data Normal 32/fS Undefined Data ADC DOUT Normal Normal ZERO Normal(1) NOTE: (1) The HPF transient response (exponentially attenuationed signal with 200ms time constant) appears initally. FIGURE 11. DAC Output and ADC Output When Synchronization is Lost. ® 15 PCM3000/3001 OPERATIONAL CONTROL (Pin 27). Table II indicates selectable functions, and Figures 9 and 12 illustrate control data input format and timing. The PCM3001 only allows for control of data format. PCM3000 can be controlled in a software mode with a threewire serial interface on MC (Pin 25), MD (Pin 26), and ML FUNCTION ADC/DAC DEFAULT (PCM3000) Audio Data Format (7 Selectable Formats) ADC/DAC LRCIN Polarity Loop Back Control Left Channel Attenuation Right Channel Attenuation Attenuation Control Infinite Zero Detection DAC Output Control Soft Mute Control De-emphasis (OFF, 32kHz, 44.1kHz, 48kHz) Power Down Control High Pass Filter Operation ADC/DAC ADC/DAC DAC DAC DAC DAC DAC DAC DAC ADC ADC DAC: 16-bit, MSB-first, Right-Justified ADC: 16-bit, MSB-first, Left-Justified Left/Right = High/Low OFF 0dB 0dB Left Channel and Right Channel = Individual Control OFF Output Enabled OFF OFF OFF ON TABLE II. Selectable Functions. tMHH tMLH tMLS 1.4V ML tMCH tMCL tMLL 1.4V MC tMCY LSB MD tMDS 1.4V tMDH MC Pulse Cycle Time MC Pulse Width LOW MC Pulse Width HIGH MD Setup Time MD Hold Time ML Low Level Time ML High Level Time ML Setup Time ML Hold Time tMCY tMCL tMCH tMDS tMDH tMLL tMLH tMLS tMLH 100ns (min) 40ns (min) 40ns (min) 40ns (min) 40ns (min) 40ns + 1SYSCLK (min) 40ns + 1SYSCLK (min) 40ns (min) 40ns (min) SYSCLK: 1/256fS or 1/384fS or 1/512fS FIGURE 12. Control Data Input Timing. MAPPING OF PROGRAM REGISTERS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 REGISTER 2 res res res res res A1 A0 PDWN BYPS res ATC IZD OUT DM1 DM0 MUT REGISTER 3 res res res res res A1 A0 res res res LOP FMT2 FMT1 FMT0 LRP res ® PCM3000/3001 16 PROGRAM REGISTER (PCM3000) AL (7:0): Bit 7 :0 AL7 and AL0 are MSB and LSB, respectively. The attenuation level (ATT) is given by: The software mode allows the user to control special functions. PCM3000’s special functions are controlled using four program registers which are 16 bits long. There are four distinct registers, with bits 9 and 10 determining which register is in use. Table III describes the functions of the four registers. REGISTER NAME BIT NAME Register 0 A (1:0) res LDL AL (7:0) Register Address “00” Reserved, should be set to “0” DAC Attenuation Data Load Control for Lch Attenuation Data for Lch A (1:0) res LDR AR (7:0) Register Address “01” Reserved, should be set to “0” DAC Attenuation Data Load Control for Rch DAC Attenuation for Rch A (1:0) res PDWN BYPS ATC IZD OUT DEM (1:0) MUT Register Address “10” Reserved, should be set to “0” ADC Power Down Control ADC High-Pass Filter Operation Control DAC Attenuation Data Mode Control DAC Infinite Zero Detection Circuit Control DAC Output Enable Control DAC De-emphasis Control Lch and Rch Soft Mute Control A (1:0) res LOP FMT (2:0) LRP Register Address “11” Reserved, should be set to “0” ADC/DAC Analog Loop-back Control ADC/DAC Audio Data Format Selection ADC/DAC Polarity of LR-clock Selection Register 1 Register 2 Register 3 ATT = 20 x log10 (ATT data/256) (dB) DESCRIPTION res: LDR: res: 0 A1 A0 0 1 Register 1 Bit 15 : 11 Reserved Bit 8 DAC Attenuation Data Load Control for Right Channel AR (7:0): Bit 7 : 0 Register 0 Bit 11 : 15 Reserved DAC Attenuation Data for Right Channel AR7 and AR0 are MSB and LSB respectively. See REGISTER 0 for the attenuation formula. These bits are reserved and should be set to “0”. LDL: –∞dB (Mute) –48.16dB : –0.07dB 0dB (default) This bit is used to simultaneously set analog outputs of the left and right channels. The output level is controlled by AR (7:0) attenuation data when this bit is set to “1”. When set to “0”, the new attenuation data will be stored into a register, and the output level will remain at the previous attenuation level. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously controlled. These bits define the address for REGISTER 0: 0 00h 01h : FEh FFh These bits are reserved and should be set to “0” Register Address A0 ATTENUATION LEVEL These bits define the address for REGISTER 1: PROGRAM REGISTER 0 A1 AL (7:0) PROGRAM REGISTER 1 A (1:0): Register Address TABLE III. Functions of the Registers. A (1:0): Bit 10, 9 DAC Attenuation Data for Left Channel Bit 8 DAC Attenuation Data Load Control for Left Channel PROGRAM REGISTER 2 A (1:0): Bit 10, 9 This bit is used to simultaneously set analog outputs of the left and right channels. The output level is controlled by AL (7:0) attenuation data when this bit is set to “1”. When set to “0”, the new attenuation data will be stored into a register, and the output level will remain at the previous attenuation level. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously controlled. Register Address These bits define the address for REGISTER 2: res: A1 A0 1 0 Register 2 Bit 15:11, 6 Reserved These bits are reserved and should be set to “0”. PDWN: Bit 8 ADC Power-Down Control This bit places the ADC section in a power-down mode, forcing the output data to all zeroes. This has no effect on the DAC section. PDWN 0 Power Down Mode Disabled (default) 1 Power Down Mode Enabled ® 17 PCM3000/3001 BYPS: Bit 7 ADC High-Pass Filter Bypass Control PROGRAM REGISTER 3 A (1:0): Bit 10, 9 This bit determines enables or disables the highpass filter for the ADC. These bits define the address for REGISTER 3: BYPS ATC: 0 High-Pass Filter Enabled (default) 1 High-Pass Filter Disabled (bypassed) Bit 5 res: DAC Attenuation Channel Control 1 1 Register 3 Bit 15:11, 8:6, 0 Reserved Audio Data Format Select These bits determine the input and output audio data formats. (default: FMT [2:0] = 000H) FMT2 FMT1 FMT0 DAC Data Format ADC Data Format 0 Individual Channel Attenuation Data Control (default) 1 Common Channel Attenuation Data Control 0 0 0 16-bit, MSB-first, Right-justified 16-bit, MSB-first, Left-justified DAC Infinite Zero Detection Circuit Control 0 0 1 18-bit, MSB-first, Right-justified 18-bit, MSB-first, Left-justified 0 1 0 16-bit, MSB-first, Right-justified 16-bit, MSB-first, Right-justified 0 1 1 18-bit, MSB-first, Right-justified 18-bit, MSB-first, Right-justified 1 0 0 16-/18-bit, MSB-first, Left-justified 18-bit, MSB-first, Left-justified 1 0 1 16-/18-bit, MSB-first, I2S 18-bit, MSB-first, I2S 1 1 0 16-bit, MSB-first, DSP-frame 16-bit, MSB-first, DSP-frame 1 1 1 Reserved Reserved Bit 4 This bit enables the Infinite Zero Detection Circuit in PCM3000. When enabled, this circuit will disconnect the analog output amplifier from the deltasigma DAC when the input is continuously zero for 65,536 consecutive cycles of BCKIN. IZD 0 Infinite Zero Detection Disabled (default) 1 Infinite Zero Detection Enabled Bit 3 DAC Output Enable Control LOP: When set to “1”, the outputs are forced to VCC/2 (bipolar zero). In this case, all registers in PCM3000 hold the present data. Therefore, when set to “0”, the outputs return to the previous programmed state. 0 DAC Outputs Enabled (default normal operation) DAC Outputs Disabled (forced to BPZ) LRP: DAC De-emphasis Control These bits select the de-emphasis mode as shown below: DM0 0 0 1 0 1 0 De-emphasis OFF (default) De-emphasis 48kHz ON De-emphasis 44.1kHz ON 1 1 De-emphasis 32kHz ON Loop-back Disable (default) 1 Loop-back Enable Bit 1 Polarity of LRCIN Applies only to Formats 0 through 4. LRP The input and output data formats are controlled by pins 27 (FMT0), 26 (FMT1), and 25 (FMT2). Set these pins to the same values shown for the bit-mapped PCM3000 controls in PROGRAM REGISTER 3. When set to “1”, both left and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on. MUT Mute Disable (default) Mute Enable ® PCM3000/3001 Left-Channel is “H”, Right-Channel is “L”. (default) Left-Channel is “L”, Right-Channel is “H”. PCM3001 DATA FORMAT CONTROL DAC Soft Mute Control 0 1 0 0 1 DM1 Bit 0 ADC to DAC Loop-back Control LOP 1 DM (1:0):Bit 2,1 Bit 5 When this bit is set to “1”, the ADC’s audio data is sent directly to the DAC. The data format will default to I2S. In Format 6 (DSP Frame), Loopback is not supported. OUT MUT: A0 FMT (2:0) Bit 4:2 ATC OUT: A1 These bits are reserved, and should be set to “0”. When set to “1”, the REGISTER 0 attenuation data can be used for both DAC channels. In this case, the REGISTER 1 attenuation data is ignored. IZD: Register Address 18 +5V Register Control Interface 1 (1) Line In Left-Channel 2.2µF(2) Line In Right-Channel 2.2µF(2) + 4.7µF + 4.7µF + + 28 2 27 3 26 4 Analog Front-End 6 24 Analog Front-End (1) 23 7 22 470pF Serial Control or Format Control 25 Reference 5 Reset Delta-Sigma 8 10 to 33pF 21 CLK/OSC Manager 9 20 470pF Decimation Filter 10 Line Out Right-Channel 10µF Post Low-Pass Filter + 11 Interpolation Filter 12 19 Digital Audio Interface 18 17 Delta-Sigma (1) 13 Digital Audio Data 16 Bias 14 LPF and Buffer Line Out Left-Channel 15 LPF and Buffer Post Low-Pass Filter NOTES: (1) Bypass capacitor = 0.1µF to 10µF. (2) The input capacitor affects the pole of the HPF. Example: 2.2µF sets the cut-off frequency to 4.8Hz, with a 66ms time constant. FIGURE 13. Typical Connection Diagram for PCM3000/3001. VOLTAGE INPUT PINS APPLICATION AND LAYOUT CONSIDERATIONS A tantalum or aluminum electrolytic capacitor, between 2.2µF and 10µF, is recommended as an AC-coupling capacitor at the inputs. Combined with the 15kΩ characteristic input impedance, a 2.2µF coupling capacitor will establish a 4.8Hz cutoff frequency for blocking DC. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 15kΩ input impedance, creates a voltage divider and enables larger input ranges. POWER SUPPLY BYPASSING The digital and analog power supply lines to PCM3000/ 3001 should be bypassed to the corresponding ground pins with both 0.1µF ceramic and 10µF tantalum capacitors as close to the device pins as possible. Although PCM3000/ 3001 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power supply sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems. VREF INPUTS A 4.7µF to 10µF tantalum capacitor is recommended between VREFL, VREFR, and AGND to ensure low source impedance for the ADC’s references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference. GROUNDING In order to optimize dynamic performance of PCM3000/ 3001, the analog and digital grounds are not internally connected. PCM3000/3001 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3000/3001 ground pins with low impedance connections to the analog ground plane. PCM3000/3001 should reside entirely over this plane to avoid coupling high frequency digital switching noise into the analog ground plane. CINP AND CINN INPUTS A 470pF to 1000pF film or NPO ceramic capacitor is recommended between CINPL and CINNL, CINPR, and CINNR to create an anti-alias filter, which will have an 170kHz to 80kHz cut-off frequency. These capacitors should be located as close as possible to the CINP and CINN pins to avoid introducing undesirable noise or dynamic errors into the delta-sigma modulator. ® 19 PCM3000/3001 VCOM INPUTS The input signal is sampled at 64X oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. A 4.7µF to 10µF tantalum capacitor is recommended between VCOM and AGND to ensure low source impedance of the DAC output common. This capacitor should be located as close as possible to the VCOM pin to reduce dynamic errors on the DAC common. SYSTEM CLOCK The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3000/ 3001. The duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN) and a word clock (LCRIN) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipation limit is exceeded. The 64fS one-bit data stream from the modulator is converted to 1fS 18-bit data words by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. The DC components are removed by a high pass filter function contained within the decimation filter. THEORY OF OPERATION DAC SECTION THEORY OF OPERATION The delta-sigma DAC section of PCM3000/3001 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level delta-sigma format. A block diagram of the 5-level deltasigma modulator is shown in Figure 15. This 5-level deltasigma modulator has the advantage of improved stability and reduced clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. ADC SECTION The PCM3000/3001 ADC consists of a bandgap reference, a stereo single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The Block Diagram in this data sheet illustrates the architecture of the ADC section, Figure 1 shows the single-to-differential converter, and Figure 14 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 16. An internal high precision reference with two external capacitors provides all reference voltages which are required by the ADC, which defines the full scale range for the converter. The internal single-to-differential voltage converter saves the space and extra parts needed for external circuitry required by many delta-sigma converters. The internal full differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. ® PCM3000/3001 20 Analog In X(z) + – 1st SW-CAP Integrator – – 2nd SW-CAP Integrator + 3rd SW-CAP Integrator 4th SW-CAP Integrator + 5th SW-CAP Integrator Qn(z) + + + + + + + + Digital Out Y(z) H(z) Comparator 1-Bit DAC Y(z) = STF(z) • X(z) + NTF(z) • Qn(z) Signal Transfer Function Noise Transfer Function STF(z) = H(z)/[1 + H(z)] NTF(z) = 1/[1 + H(z)] FIGURE 14. Simplified 5th-Order Delta-Sigma Modulator. + In + 8fS 18-Bit + + + Z–1 – + Z–1 Z–1 – + + + 5-level Quantizer 4 3 Out 2 1 64fS (256fS) 0 FIGURE 15. 5-Level ∆Σ Modulator Block Diagram. Gain (–dB) 3rd ORDER ∆Σ MODULATOR 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 0 5 10 15 20 25 30 Frequency (kHz) FIGURE 16. Quantization Noise Spectrum. ® 21 PCM3000/3001