® PCM1728 49% 172 8 FPO PCM 24-Bit, 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER TM FEATURES DESCRIPTION ● ENHANCED MULTI-LEVEL DELTA-SIGMA DAC ● SAMPLING FREQUENCY (fS): 16kHz - 96kHz ● INPUT AUDIO DATA WORD: 16-, 20-, 24-Bit ● HIGH PERFORMANCE: THD+N: –96dB Dynamic Range: 106dB SNR: 106dB Analog Output Range: 0.62 x VCC (Vp-p) ● 8x OVERSAMPLING DIGITAL FILTER: Stop Band Attenuation: –82dB Passband Ripple: ±0.002dB ● MULTI FUNCTIONS: Digital De-emphasis Soft Mute Zero Flag ● +5V SINGLE SUPPLY OPERATION ● SMALL 28-LEAD SSOP PACKAGE The PCM1728 is designed for mid- to high-grade digital audio applications which achieve 96kHz sampling rates with 24-bit audio data. PCM1728 uses a newly developed, enhanced multi-level delta-sigma modulator architecture that improves audio dynamic performance and reduces jitter sensitivity in actual applications. The internal digital filter operates at 8X oversampling at a 96kHz sampling rate. VCC2R AGND2L VCC2L AGND2L The PCM1728 has superior audio dynamic performance, 24-bit resolution, and 96kHz sampling, making it ideal for mid- to high-grade audio applications such as CD, DVD, and musical instruments. BCKIN LRCIN DIN Serial Input I/F Low-pass Filter DAC 8X Oversampling Digital Filter with Function Controller Enhanced Multi-level Delta-Sigma Modulator Low-pass Filter DAC I2S VOUTL EXTL VOUTR EXTR DM1 DM0 IW0 IW1 Mode Control I/F ZERO SCK Open Drain MUTE RST Crystal/OSC XTI XTO Power Supply CLKO VCC1 AGND1 VDD DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1453A Printed in U.S.A. April, 1998 SPECIFICATIONS All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1728 PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 24 DATA FORMAT Audio Data Interface Format Data Bit Length Audio Data Format Sampling Frequency (fS) System Clock Frequency(1) UNITS Bits Standard/I2S 16/20/24 Selectable MSB-First, Two’s Binary Comp 16 96 kHz 256/384/512/768fS DIGITAL INPUT/OUTPUT LOGIC LEVEL Input Logic Level VIH VIL Output Logic Level (CLKO) VOH VOL CLKO PERFORMANCE(2) Output Rise Time Output Fall Time Output Duty Cycle DYNAMIC PERFORMANCE(3) (24-Bit Data) THD+N VO = 0dB VO = –60dB Dynamic Range Signal-to-Noise Ratio Channel Separation DYNAMIC PERFORMANCE(3) (16-Bit Data) THD+N VO = 0dB Dynamic Range DC ACCURACY Gain Error Gain Mismatch: Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Filter Characteristics Passband Stopband Passband Ripple Stopband Attenuation 2.0 0.8 IOH = 2mA IOL = 4mA 4.5 0.5 20 ~ 80% VDD, 10pF 80 ~ 20% VDD, 10pF 10pF Load 5.5 4 37 fS = 44.1kHz fS = 96kHz fS = 44.1kHz –97 –94 –42 fS =44.1kHz EIAJ A-weighted fS = 96kHz A-weighted fS =44.1kHz EIAJ A-weighted fS = 96kHz A-weighted fS = 44.1kHz fS = 96kHz 98 POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: ICC +IDD Power Dissipation ns ns % –90 dB dB dB 106 103 106 103 102 101 dB dB dB dB dB dB fS = 44.1kHz fS = 96kHz fS = 44.1kHz EIAJ A-weighted fS = 96kHz A-weighted –94 –92 98 97 dB dB dB dB VO = 0.5VCC at Bipolar Zero ±1.0 ±1.0 ±30 98 96 Full Scale (0dB) ±3.0 ±3.0 ±60 0.62 VCC 0.5 VCC AC Load ±0.002dB –3dB % of FSR % of FSR mV Vp-p V kΩ 5 0.454fS 0.490fS 0.546fS Stop Band = 0.546fS Stop Band = 0.567fS ±0.002 –75 –82 Delay Time De-emphasis Error INTERNAL ANALOG FILTER –3dB Bandwidth Passband Response V V V V 30/fS ±0.1 100 –0.16 f = 20kHz VDD, VCC fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz 4.5 TEMPERATURE RANGE Operation Storage –25 –55 5 32 45 160 225 dB dB dB sec dB kHz dB 5.5 45 225 +85 +100 VDC mA mA mW mW °C °C NOTES: (1) Refer section of system clock. (2) External buffer is recommended. (3) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average Mode. ® PCM1728 2 PIN CONFIGURATION LRCIN PIN ASSIGNMENTS 28 I2S 1 DIN 2 27 DM1 BCKIN 3 26 DM0 CLKO 4 25 MUTE XTI 5 24 IW1 XTO 6 23 IW0 DGND 7 22 RST VDD 8 21 ZERO VCC2R 9 20 VCC2L PCM1728E PIN NAME I/O 1 LRCIN IN DESCRIPTION Left and Right Clock Input. This clock is equal to the sampling rate - fS.(1) 2 DIN IN Serial Audio Data Input(1) 3 BCKIN IN Bit Clock Input for Serial Audio Data.(1) 4 CLKO OUT Buffered Output of Oscillator. Equivalent to System Clock. 5 XTI IN 6 XTO OUT Oscillator Input (External Clock Input) 7 DGND — Digital Ground Digital Power +5V Oscillator Output 8 VDD — 9 VCC2R — Analog Power +5V 10 AGND2R — Analog Ground 11 EXTR OUT 12 NC — 13 VOUTR OUT 14 AGND1 — Analog Ground Analog Power +5V AGND2R 10 19 AGND2L 15 VCC1 — EXTR 11 18 EXTL 16 VOUTL OUT 17 NC — Rch, Common Pin of Analog Output Amp No Connection Rch, Analog Voltage Output of Audio Signal Lch, Analog Voltage Output of Audio Signal No Connection NC 12 17 NC 18 EXTL OUT VOUTR 13 16 VOUTL 19 AGND2L — AGND1 14 15 VCC1 20 VCC2L — 21 ZERO OUT 22 RST IN Reset. When this pin is LOW, the DF and modulators are held in reset.(2) 23 IW0 IN Input Format Selection(3) PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) PCM1728E 28-Pin SSOP 324 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. Lch, Common Pin of Analog Output Amp Analog Ground Analog Power +5V Zero Data Flag 24 IW1 IN Input Format Selection(3) 25 MUTE IN Mute Control 26 DM0 IN De-emphasis Selection 1(2) 27 DM1 IN De-emphasis Selection 2(2) 28 I2S IN Input Format Selection(2) NOTES: (1) Pins 1, 2, 3; Schmitt Trigger input. (2) Pins 22, 25, 26, 27, 28; Schmitt Trigger input with pull-up resister. (3) Pins 23, 24; Schmitt Trigger input with pull-down resister. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ...................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Input Current (except power supply) ............................................... ±10mA Power Dissipation .......................................................................... 400mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) ................................................. +260°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1728 TYPICAL PERFORMANCE CURVES All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted. THD+N vs SAMPLING FREQUENCY (VCC = VDD = 5V, 24-Bit) THD+N vs LEVEL (fS = 44.1kHz) 88 –20 10 –30 256fs 97 –60 0.1 –70 0.010 –80 24-Bit 384fs –90 103 –100 0.001 32 110 44.1 48 96 –60 –50 –40 –30 –20 –10 Sampling Frequency fS (kHz) Amplitude (dB) DYNAMIC RANGE vs SAMPLING FREQUENCY (VCC = VDD = 5V, 24-Bit) SNR vs SAMPLING FREQUENCY (VCC = VDD = 5V, 24-Bit) 110 108 SNR (A-weighted) (dB) Dynamic Range (A-weighted) (dB) –50 16-Bit 106 256/384fS 104 102 100 0 108 106 256/384fS 104 102 100 32 –60 44.1 48 96 32 44.1 48 96 Sampling Frequency fS (kHz) Sampling Frequency fS (kHz) –60dB OUTPUT SPECTRUM (f = 1kHz, fS = 44.1kHz, 16-Bit Data) –60dB OUTPUT SPECTRUM (f = 1kHz, fS = 44.1kHz, 24-Bit Data) –60 –70 –80 –80 –90 –90 Amplitude (dB) –70 –100 –110 –120 –100 –110 –120 –130 –130 –140 –140 –150 –150 20 2 4 6 8 10 12 14 16 18 20 20 Frequency (Hz) 4 6 8 10 12 Frequency (Hz) ® PCM1728 2 4 14 16 18 20 THD+N (dB) 94 100 Amplitude (dB) –40 1 THD+N (%) THD+N at F/S (dB) 91 TYPICAL PERFORMANCE CURVES (CONT) PASSBAND RIPPLE CHARACTERISTIC OVERALL FREQUENCY CHARACTERISTIC 0 0.003 –20 0.002 Amplitude (dB) Amplitude (dB) –40 –60 –80 –100 0.001 0 –0.001 –120 –0.002 –140 –160 –0.003 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.1 0.2 DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz) 0 –2 –4 –6 –8 –10 0 2 4 6 8 10 12 14 0 2 Level (dB) Level (dB) 2 4 6 8 10 12 4 14 16 18 20 0 2 4 Level (dB) Level (dB) 2 4 6 8 10 12 14 8 10 12 14 6 8 10 12 14 16 18 20 20 22 Frequency (kHz) DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz) 0 6 DE-EMPHASIS ERROR (fS = 44.1kHz) 0.5 0.3 0.1 –0.1 –0.3 –0.5 Frequency (kHz) 0 –2 –4 –6 –8 –10 0.5 Frequency (kHz) DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz) 0 0.4 DE-EMPHASIS ERROR (fS = 32kHz) 0.5 0.3 0.1 –0.1 –0.3 –0.5 Frequency (kHz) 0 –2 –4 –6 –8 –10 0.3 Frequency (x fS) Level (dB) Level (dB) Frequency (x fS) 16 18 20 22 DE-EMPHASIS ERR0R (fS = 48kHz) 0.5 0.3 0.1 –0.1 –0.3 –0.5 0 Frequency (kHz) 2 4 6 8 10 12 14 16 18 Frequency (kHz) ® 5 PCM1728 SYSTEM CLOCK Typical input system clock frequencies to the PCM1728 are shown in Table I, also, external input clock timing requirements are shown in Figure 2. The system clock for PCM1728 must be either 256fS, 384fS, 512fS or 768fS, where fS is the audio sampling frequency (typically 32kHz, 44.1kHz, 48kHz, or 96kHz). But 768fS at 96kHz is not accepted. The system clock can be either a crystal oscillator placed between XTI (pin 5) and XTO (pin 6), or an external clock input to XTI. If an external system clock is used, XTO is open (floating). Figure 1 illustrates the typical system clock connections. tSCKH “H” 2.0V XTI 0.8V “L” PCM1728 has a system clock detection circuit which automatically senses if the system clock is operating at 256fS ~ 768fS. The system clock should be synchronized with LRCIN (pin 1) clock. LRCIN (left-right clock) operates at the sampling frequency fS. In the event these clocks are not synchronized, PCM1728 can compensate for the phase difference internally. If the phase difference between left-right and system clocks is greater than 6-bit clocks (BCKIN), the synchronization is performed internally. While the synchronization is processing, the analog output is forced to a DC level at bipolar zero. The synchronization typically occurs in less than 1 cycle of LRCIN. tSCKL System Clock Pulse Width High tSCKIH : 7ns MIN System Clock Pulse Width Low tSCKIL : 7ns MIN FIGURE 2. XTI Clock Timing. DATA INTERFACE FORMATS Digital audio data is interfaced to PCM1728 on pins 1, 2, and 3, LRCIN (left-right clock), DIN (data input) and BCKIN (bit clock). PCM1728 can accept both standard, I2S, and left justified data formats. Figure 3 illustrates acceptable input data formats. Figure 4 shows required timing specification for digital audio data. Externl Clock Input Reset System Clock (256/384/ 512/768fS) 4 CLKO 5 XTI 6 XTO PCM1728 has both internal power-on reset circuit and the RST pin (pin 22), which accepts an external forced reset by RST = LOW. For internal power on reset, initialization is done automatically at power on VDD >2.2V (typ). During internal reset = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC /2. Figure 5 illustrates the timing of the internal power on reset. PCM1728 PCM1728 accepts an external forced reset when RST = LOW. When RST = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC /2 after internal initialization (1024 system clocks count after RST = HIGH.) Figure 6 illustrates the timing of the RST pin. Crystal Resonator Oscillation System Clock Buffer Out 4 CLKO 5 XTI 6 XTO Buffer C1 Zero Out (pin 21) C2 XTAL If the input data is continuously zero for 65536 cycles of BCK, an internal FET is switched to “ON”. The drain of the internal FET is the zero-pin, it will enable “wired-or” with external circuit. PCM1728 C1 C2 : 10pF ~ 30pF FIGURE 1. System Clock Connection. SYSTEM CLOCK FREQUENCY - MHz SAMPLING RATE FREQUENCY (fS) - LRCIN 256fS 384fS 512fS 768fS 32kHz 8.1920 12.2880 16.3840 24.5760 44.1kHz 11.2896 16.9340 22.5792 33.8688(1) 48kHz 12.2880 18.4320 24.5760 36.8640(1) 24.5760 36.8640(1) 49.1520(1) — 96kHz NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz. TABLE I. Typical System Clock Frequency. ® PCM1728 6 1/fS L_ch R_ch LRCIN (pin 1) BCKIN (pin 3) (1) 16-Bit Right Justified DIN (pin 2) 14 15 16 1 2 MSB (2) 20-Bit Right Justified DIN (pin 2) 18 19 20 1 2 23 24 1 18 3 1 2 1 22 3 19 20 1 2 22 MSB 14 3 23 24 1 18 3 2 1 2 22 3 LSB MSB 23 24 LSB 22 3 19 20 LSB MSB 23 24 15 16 LSB MSB LSB 3 2 MSB LSB MSB (4) 24-Bit Left Justified DIN (pin 2) 2 15 16 LSB MSB (3) 24-Bit Right Justified DIN (pin 2) 14 3 23 24 LSB 1/fS L_ch LRCIN (pin 1) R_ch BCKIN (pin 3) (5) 16-Bit I2S DIN (pin 2) 1 2 MSB (6) 24-Bit I2S DIN (pin 2) 14 3 1 2 15 16 1 2 LSB 3 MSB 22 3 MSB 23 24 1 LSB 2 14 15 16 1 2 1 2 LSB 3 MSB 22 23 24 LSB FIGURE 3. Audio Data Input Formats. LRCKIN 1.4V tBCH tBCL tLB BCKIN 1.4V tBL tBCY 1.4V DIN tDS tDH BCKIN Pulse Cycle Time : tBCY : 100ns (min) BCKIN Pulse Width High : tBCH : 50ns (min) BCKIN Pulse Width Low : tBCL : 50ns (min) BCKIN Rising Edge to LRCIN Edge : tBL : 30ns (min) LRCIN Edge to BCKIN Rising Edge : tLB : 30ns (min) DIN Set-up Time : tDS : 30ns (min) DIN Hold Time : tDH : 30ns (min) FIGURE 4. Audio Data Input Timing Specification. ® 7 PCM1728 VCC = VDD Reset Reset Removal Internal Reset 1024 system (= XTI) clocks XTI Clock FIGURE 5. Internal Power-On Reset Timing. RST tRST(1) Reset Reset Removal Internal Reset 1024 system (XTI) clocks XTI Clock NOTE: (1) tRST = 20ns min. FIGURE 6. External Forced Reset Timing. SOFT MUTE Soft Mute function can be controlled by MUTE (pin 25). FUNCTIONAL DESCRIPTION PCM1728 has several built-in functions including digital input data format selection, soft mute, and digital de-emphasis. These functions are hardware controlled where static control signals are used on pin 28 (I2S), pin 27 (DM1), pin 26 (DM0), pin 25 (MUTE), pin 24 (IW1), and pin23 (IW0). MUTE (Pin 25) SOFT MUTE L Mute ON H Mute OFF (Normal Operation) TABLE III. Soft Mute Control. DATA FORMAL SELECTION PCM audio data format can be selected by pin 28 (I2S), pin 24 (IW1), and pin 23 (IW0), as shown in Table II. IW1 IW0 I 2S AUDIO INTERFACE 0 0 0 16-Bit Standard, Right-Justified 0 1 0 20-Bit Standard, Right-Justified 1 0 0 24-Bit Standard, Right-Justified 1 1 0 24-Bit Left-Justified, MSB-First 0 0 1 16-Bit I2S 0 1 1 24-Bit I2S 1 0 1 Reserved 1 1 1 Reserved DE-EMPHASIS CONTROL De-emphasis control can be selected by DM1 (pin 27) and DM0 (pin 26). DM0 (Pin 26) DE-EMPHASIS L L H H L H L H OFF 48kHz 44.1kHz 32kHz TABLE IV. De-emphasis Control. TABLE II. Data Format Control. ® PCM1728 DM1 (Pin 27) 8 THEORY OF OPERATION the advantage of stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The delta-sigma section of PCM1728 is based on an 8-level amplitude quantizer and a 4th-order noise shaper. This section converts the oversampled input data to 8-level deltasigma format. The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 64fS for all system clock ratios (256/384/512/768fS). The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 8. This enhanced multi-level delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, simulated jitter sensitivity is shown in Figure 9. This newly developed, “Enhanced Multi-level Delta-Sigma” architecture achieves high-grade audio dynamic performance and sound quality. A block diagram of the 8-level delta-sigma modulator is shown in Figure 7. This 8-level delta-sigma modulator has – + + Z–1 Z–1 + Z–1 + Z–1 + + 8-Level Quantizer FIGURE 7. 8-Level Delta-Sigma Modulator. 125 –20 120 –40 115 Dynamic Range (dB) Amplitude (dB) CLOCK JITTER 0 –60 –80 –100 –120 110 105 100 95 –140 90 –160 85 80 –180 0 1 2 3 4 5 6 7 0 8 100 200 300 400 500 600 Jitter (ps) Frequency (fS) FIGURE 8. Quantization Noise Spectrum. FIGURE 9. Jitter Sensitivity. ® 9 PCM1728 APPLICATION CONSIDERATIONS 1 DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1728: Level (dB) 0.5 0 –0.5 TD = 30 x 1/fS –1 1 10 100 For fS = 44.1kHz, TD = 30/44.1kHz = 680µs Applications using data from a disc or tape source, such as CD audio, DVD audio, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. 10k 100k FIGURE 10. Low Pass Filter Response. 20 0 Level (dB) OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1728 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. –20 –40 –60 –80 –100 1 The performance of the internal low pass filter from DC to 40kHz is shown in Figure 10. The higher frequency roll-off of the filter is shown in Figure 11. If the user’s application has the PCM1728 driving a wideband amplifier, it is recommended to use an external low pass filter. 10 100 1k 10k 100k 1M 10M Log Frequency (Hz) FIGURE 11. Low Pass Filter Response. POWER SUPPLY CONNECTIONS BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. Refer to Figure 12 for optimal values of bypass capacitors. PCM1728 has four power supply pin for digital (VDD), and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.1V. ® PCM1728 1k Log Frequency (Hz) 10 PCM1728E 1 LRCIN 2 DIN DM1 27 3 BCKIN DM0 26 XTI Buffer Out 4 CLKO System Clock (256/384/512/768fS) 5 XTI IW1 24 6 XTO IW0 23 7 DGND RST 22 8 VDD ZERO 21 9 VCC2R VCC2L 20 PCM Audio Data Input To DGND of Digital Source C2 C4 C6 10µF IIS 28 MUTE 25 10 AGND2R + Mode Control External Reset 10kΩ C3 AGND2L 19 11 EXTR EXTL 18 12 NC NC 17 13 VOUTR VOUTL 16 14 AGND1 VCC1 15 + C5 10µF C1 +5V VCC Post Low-Pass Filter C1, C2 : 10µF + 0.1µF Ceramic C3, C4 : 1µF ~ 10µF Post Low-Pass Filter Analog Mute Analog Mute Rch Audio Out Lch Audio Out External Mute Control FIGURE 12. Typical Circuit Connection Diagram. ® 11 PCM1728