SRC4192(1) SRC4193(1) SRC 419 2 SRC 419 3 SBFS022A – JULY 2003 192kHz Stereo Asynchronous Sample Rate Converters FEATURES ● AUTOMATIC SENSING OF THE INPUT-TOOUTPUT SAMPLING RATIO ● WIDE INPUT-TO-OUTPUT SAMPLING RANGE: 16:1 to 1:16 ● SUPPORTS INPUT & OUTPUT SAMPLING RATES UP TO 212kHz ● DYNAMIC RANGE: 144dB (-60dbFS input, BW = 20Hz to fS /2, A-Weighted) ● THD+N: -140dB (0dbFS input, BW = 20Hz to fS /2) ● ATTENUATES SAMPLING AND REFERENCE CLOCK JITTER ● HIGH PERFORMANCE, LINEAR PHASE DIGITAL FILTERING WITH BETTER THAN 140dB OF STOP BAND ATTENUATION ● FLEXIBLE AUDIO SERIAL PORTS: Master or Slave Mode Operation Supports I2S, Left Justified, Right Justified, and TDM Data Formats Supports 16, 18, 20, or 24-Bit Audio Data TDM Mode allows daisy chaining of up to eight devices ● SUPPORTS 24-, 20-, 18-, or 16-BIT INPUT AND OUTPUT DATA All output data is dithered from the internal 28-Bit data path ● LOW GROUP DELAY OPTION FOR INTERPOLATION FILTER ● DIRECT DOWNSAMPLING OPTION FOR DECIMATION FILTER (SRC4193 ONLY) ● SPI PORT PROVIDES ACCESS TO INTERNAL CONTROL REGISTERS (SRC4193 ONLY) ● SOFT MUTE FUNCTION ● BYPASS MODE ● PROGRAMMABLE DIGITAL OUTPUT ATTENUATION (SRC4193 ONLY) 256 steps: 0dB to –127.5dB, 0.5dB/step (1) Patents Pending. (2) Refer to the Applications Information section of this data sheet for details. ● POWER DOWN MODE ● OPERATES FROM A SINGLE +3.3 VOLT POWER SUPPLY ● SMALL 28-LEAD SSOP PACKAGE ● PIN COMPATIBLE WITH THE AD1896 (SRC4192 ONLY)(2) APPLICATIONS ● ● ● ● ● ● DIGITAL MIXING CONSOLES DIGITAL AUDIO WORKSTATIONS AUDIO DISTRIBUTION SYSTEMS BROADCAST STUDIO EQUIPMENT HIGH-END A/V RECEIVERS GENERAL DIGITAL AUDIO PROCESSING DESCRIPTION The SRC4192 and SRC4193 are asynchronous sample rate converters designed for professional and broadcast audio applications. The SRC4192 and SRC4193 combine a wide input-to-output sampling ratio with outstanding dynamic range and ultra low distortion. Input and output serial ports support standard audio formats, as well as a Time Division Multiplexed (TDM) mode. Flexible audio interfaces allow the SRC4192 and SRC4193 to connect to a wide range of audio data converters, digital audio receivers and transmitters, and digital signal processors. The SRC4192 is a standalone pin programmed device, with control pins for mode, data format, mute, bypass, and low group delay functions. The SRC4193 is a software-controlled device featuring a serial peripheral interface (SPI) port, which is utilized to program all functions via internal control registers. The SRC4192 and SRC4193 may be operated from a single +3.3V power supply. A separate digital I/O supply (VIO) operates over the +1.65V to +3.6V supply range, allowing greater flexibility when interfacing to current and future generation signal processors and logic devices. Both the SRC4192 and SRC4193 are available in a 28-lead SSOP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage, VDD .......................................................... –0.3V to +4.0V Supply Voltage, VIO ........................................................... –0.3V to +4.0V Digital Input Voltage .......................................................... –0.3V to +4.0V Operating Temperature Range ........................................ –45°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT SRC4192 " SRC4193 " PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY SSOP-28 DB –45°C to +85°C SRC4192I " " " " SRC4192IDB SRC4192IDBR Rails, 50 Tape and Reel, 2000 SSOP-28 DB –45°C to +85°C SRC4193I " " " " SRC4193IDB SRC4193IDBR Rails, 50 Tape and Reel, 2000 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATION (SRC4192) PIN DESCRIPTIONS (SRC4192) Top View LGRP 2 27 MODE1 NC 3 26 MODE0 SDIN 4 25 BCKO BCKI 5 24 LRCKO 2 7 DGND 8 DESCRIPTION LGRP Low Group Delay Control Input (Active High) 2 RCKI Reference Clock Input 3 N.C. No Connection 4 SDIN Audio Serial Data Input 5 BCKI Input Port Bit Clock I/O 6 LRCKI 7 VIO SRC4192 Input Port Left/Right Word Clock I/O Digital I/O Supply, +1.65V to VDD 8 DGND Digital Ground 9 BYPAS ASRC Bypass Control Input (Active High) 10 IFMT0 Input Port Data Format Control Input 11 IFMT1 Input Port Data Format Control Input 12 IFMT2 22 VDD 13 RST 21 DGND 14 MUTE 15 RDY 23 SDOUT 6 VIO NAME 1 28 MODE2 1 RCKI LRCKI PIN# Input Port Data Format Control Input Reset Input (Active Low) Output Mute Control Input (Active High) ASRC Ready Status Output (Active Low) BYPAS 9 20 TDMI 16 OWL1 Output Port Data Word Length Control Input IFMT0 10 19 OFMT0 17 OWL0 Output Port Data Word Length Control Input 18 OFMT1 Output Port Data Format Control Input IFMT1 11 18 OFMT1 19 OFMT0 IFMT2 12 17 OWL0 20 TDMI TDM Data Input (Connect to DGND when not in use) RST 16 OWL1 21 DGND Digital Ground 13 22 VDD MUTE 14 15 RDY 23 SDOUT 24 LRCKO 25 BCKO 26 MODE0 Serial Port Mode Control Input 27 MODE1 Serial Port Mode Control Input 28 MODE2 Serial Port Mode Control Input Output Port Data Format Control Input Digital Core Supply, +3.3V Audio Serial Data Output Output Port Left/Right Word Clock I/O Output Port Bit Clock I/O SRC4192, SRC4193 www.ti.com SBFS022A PIN CONFIGURATION (SRC4193) PIN DESCRIPTIONS (SRC4193) Top View RCKI NC 2 27 CCLK NC 3 26 CS SDIN 4 25 BCKO BCKI 5 24 LRCKO 6 VIO 7 DGND 8 NAME 1 RCKI Reference Clock Input 2 N.C. No Connection 3 N.C. No Connection 4 SDIN Audio Serial Data Input 5 BCKI Input Port Bit Clock I/O 6 LRCKI 7 VIO 28 CDATA 1 LRCKI PIN# Input Port Left/Right Word Clock I/O Digital I/O Supply, +1.65V to VDD 8 DGND Digital Ground 9 BYPAS ASRC Bypass Control Input (Active High) 10 N.C. No Connection 11 N.C. No Connection 12 N.C. No Connection 22 VDD 13 RST Reset Input (Active Low) 21 DGND 14 MUTE 15 RDY 16 RATIO 23 SDOUT SRC4193 DESCRIPTION Output Mute Control Input (Active High) ASRC Ready Status Output (Active Low) BYPAS 9 20 TDMI NC 10 19 NC NC 11 18 NC 17 N.C. No Connection NC 12 17 NC 18 N.C. No Connection 19 N.C. No Connection 20 TDMI TDM Data Input (Connect to DGND when not in use) 21 DGND Digital Ground 22 VDD 23 SDOUT 24 LRCKO 25 BCKO Input-to-Output Ratio Flag Output Low output denotes Output rate lower than Input rate. High output denotes Output rate higher than Input rate. RST 13 16 RATIO MUTE 14 15 RDY SRC4192, SRC4193 SBFS022A www.ti.com Digital Core Supply, +3.3V Audio Serial Data Output Output Port Left/Right Word Clock I/O Output Port Bit Clock I/O 26 CS 27 CCLK SPI Port Data Clock Input SPI Port Chip Select Input (Active Low) 28 CDATA SPI Port Serial Data Input 3 ELECTRICAL CHARACTERISTICS All parameters specified with TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. SRC4192, SRC4193 PARAMETER DYNAMIC PERFORMANCE(1) Resolution Input Sampling Frequency Output Sampling Frequency Input: Output Sampling Ratio Upsampling Downsampling Dynamic Range CONDITION 4 4 fSOUT MAX UNITS 212 212 Bits kHz kHz 1:16 16:1 BW = 20Hz to fSOUT /2, –60dBFS Input fIN = 1kHz, Unweighted (add 3dB to spec for A-weighted result) 140 140 140 138 141 141 141 141 140 138 dB dB dB dB dB dB dB dB dB dB –140 –140 –140 –137 –140 –140 –141 –141 –140 –137 0 0 dB dB dB dB dB dB dB dB dB dB dB Degrees 0 –127.5 0.5 –144 dB dB dB dB BW = 20Hz to fSOUT /2, 0dBFS Input fIN = 1kHz, Unweighted 44.1kHz; 48kHz 48kHz; 44.1kHz 48kHz; 96kHz 44.1kHz; 192kHz 96kHz; 48kHz 192kHz; 12kHz 192kHz; 32kHz 192kHz; 48kHz 32kHz; 48kHz 12kHz; 192kHz Interchannel Gain Mismatch Interchannel Phase Deviation Digital Attenuation Minimum Maximum Step Size Mute Attenuation SRC4193 Only 24-Bit Word Length, A-weighted DIGITAL INTERPOLATION FILTER CHARACTERISTICS Passband Passband Ripple Transition Band Stop Band Stop Band Attenuation Normal Group Delay (LGRP = 0) Normal Group Delay (LGRP = 0) Low Group Delay (LGRP = 1) Low Group Delay (LGRP = 1) 0.4535 x fSIN 0.5465 x fSIN –144 Decimation Filter On (DFLT = 0) Decimation Filter Off (DFLT = 1) Decimation Filter On (DFLT = 0) Decimation Filter Off (DFLT = 1) DIGITAL DECIMATION FILTER CHARACTERISTICS Passband Passband Ripple Transition Band Stop Band Stop Band Attenuation Group Delay Decimation Filter Direct Down-Sampling 4 TYP 24 fSIN 44.1kHz; 48kHz 48kHz; 44.1kHz 48kHz; 96kHz 44.1kHz; 192kHz 96kHz; 48kHz 192kHz; 12kHz 192kHz; 32kHz 192kHz; 48kHz 32kHz; 48kHz 12kHz; 192kHz Total Harmonic Distortion + Noise DIGITAL I/O CHARACTERISTICS High-Level Input Voltage Low Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage Input Capacitance MIN DFLT = 0 for SRC4193 SRC4193 Only, DFLT = 1 0.4535 x fSOUT ±0.008 0.5465 x fSOUT Hz dB Hz Hz dB 36.46875/fSOUT 0 0.7 x VIO 0 0.5 0.5 IO = –4mA IO = +4mA Hz dB Hz Hz dB Seconds Seconds Seconds Seconds 102.53125/fSIN 102/fSIN 70.53125/fSIN 70/fSIN 0.4535 x fSOUT 0.5465 x fSOUT –143 VIH VIL IIH IIL VOH VOL CIN 0.4535 x fSIN ±0.007 0.5465 x fSIN 0.8 x VIO 0 3 Seconds Seconds VIO 0.3 x VIO 10 10 VIO 0.2 x VIO V V µA µA V V pF SRC4192, SRC4193 www.ti.com SBFS022A ELECTRICAL CHARACTERISTICS (Cont.) All parameters specified with TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. SRC4192, SRC4193 PARAMETER SWITCHING CHARACTERISTICS Reference Clock Timing RCKI Frequency(2), (3) RCKI Period RCKI Pulsewidth High RCKI Pulsewidth Low Reset Timing RST Pulse Width Low Delay Following RST Rising Edge Input Serial Port Timing LRCKI to BCKI Setup Time BCKI Pulsewidth High BCKI Pulsewidth Low SDIN Data Setup Time SDIN Data Hold Time Output Serial Port Timing SDOUT Data Delay Time SDOUT Data Hold Time BCKO Pulsewidth High BCKO Pulsewidth Low TDM Mode Timing LRCKO Setup Time LRCKO Hold Time TDMI Data Setup Time TDMI Data Hold Time SPI Timing CCLK Frequency CDATA Setup Time CDATA Hold Time CS Falling to CCLK Rising CCLK Falling to CS Rising POWER SUPPLIES Operating Voltage VDD VIO Supply Current IDD, Power Down IDD, Power Down (SRC4193 only) IDD, Dynamic IIO, Power Down IIO, Power Down (SRC4193 only) IIO, Dynamic Total Power Dissipation PD, Power Down PD, Power Down (SRC4193) PD, Dynamic CONDITION MIN TYP 128 x fSMIN 20 0.4 x tRCKIP 0.4 x tRCKIP tRCKIP tRCKIH tRCKIL tRSTL MAX UNITS 50 1/(128 x fSMIN) MHz ns ns ns 500 500 ns µs tLRIS tSIH tSIL tLDIS tLDIH 10 10 10 10 10 ns ns ns ns ns tDOPD tDOH tSOH tSOL 2 10 5 ns ns ns ns tLROS tLROH tTDMS tTDMH 10 10 10 10 ns ns ns ns tCDS tCDH 12 8 15 12 SRC4193 Only 10 tCSCR tCFCS 3.0 1.65 VDD = +3.3V, VIO = +3.3V RST = 0, No Clocks PDN Bit = 0, No Clocks fSIN = fsOUT = 192kHz RST = 0, No Clocks PDN Bit = 0, No Clocks fSIN = fSOUT = 192kHz VDD = +3.3V, VIO = +3.3V RST = 0, No Clocks PDN Bit = 0, No Clocks fSIN = fSOUT = 192kHz +3.3 +3.3 25 MHz ns ns ns ns 3.6 3.6 V V 100 µA mA mA µA µA mA 5 66 100 21 2 660 16.6 225 µW mW mW NOTES: (1) Dynamic performance measured with an Audio Precision System Two Cascade or Cascade Plus. (2) fSMIN = min (fSIN, fSOUT). (3) fSMAX = max (fSIN, fSOUT). SRC4192, SRC4193 SBFS022A www.ti.com 5 TYPICAL CHARACTERISTICS At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FFT with 1kHz INPUT TONE at 0dBFS (12kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (12kHz:192kHz) 0 –60 –20 –70 –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 20k 40k 60k 80k 96k 0 20k 40k 60k 80k Frequency (Hz) Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (32kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (32kHz:48kHz) 0 –60 –20 –70 96k –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k Frequency (Hz) Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (44.1kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (44.1kHz:48kHz) 0 –60 –20 –70 24k –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k 24k Frequency (Hz) Frequency (Hz) 6 –110 –120 SRC4192, SRC4193 www.ti.com SBFS022A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FFT with 1kHz INPUT TONE at 0dBFS (44.1kHz:96kHz) FFT with 1kHz INPUT TONE at –60dBFS (44.1kHz:96kHz) 0 –60 –20 –70 –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 10k 20k 30k 40k 48k 0 10k 20k 30k 40k Frequency (Hz) Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (44.1kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (44.1kHz:192kHz) 0 –60 –20 –70 48k –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 20k 40k 60k 80k 96k 0 20k 40k 60k 80k Frequency (Hz) Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (48kHz:44.1kHz) FFT with 1kHz INPUT TONE at –60dBFS (48kHz:44.1kHz) 0 –60 –20 –70 96k –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 5k 10k 15k 20k 22k 0 Frequency (Hz) 10k 15k 20k 22k Frequency (Hz) SRC4192, SRC4193 SBFS022A 5k www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FFT with 1kHz INPUT TONE at 0dBFS (48kHz:96kHz) FFT with 1kHz INPUT TONE at –60dBFS (48kHz:96kHz) 0 –60 –20 –70 –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 10k 20k 30k 40k 48k 0 10k 20k 30k 40k Frequency (Hz) Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (48kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (48kHz:192kHz) 0 –60 –20 –70 48k –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 20k 40k 60k 80k 96k 0 40k 60k 80k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (96kHz:44.1kHz) FFT with 1kHz INPUT TONE at –60dBFS (96kHz:44.1kHz) 96k –60 –70 –20 –80 –40 –90 –60 –100 dBFS dBFS 20k Frequency (Hz) 0 –80 –100 –110 –120 –130 –140 –120 –150 –140 –160 –160 –170 –180 –180 0 5k 10k 15k 0 20k 22k 5k 10k 15k 20k 22k Frequency (Hz) Frequency (Hz) 8 –110 –120 SRC4192, SRC4193 www.ti.com SBFS022A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FFT with 1kHz INPUT TONE at 0dBFS (96kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (96kHz:48kHz) 0 –60 –20 –70 –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k Frequency (Hz) Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (96kHz:192kHz) FFT with 1kHz INPUT TONE at –60dBFS (96kHz:192kHz) 0 –60 –20 –70 24k –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 20k 40k 60k 80k 96k 0 20k 40k 60k 80k Frequency (Hz) Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:12kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:12kHz) 0 –60 –20 –70 96k –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 1k 2k 3k 4k 5k 6k 0 Frequency (Hz) 2k 3k 4k 5k 6k Frequency (Hz) SRC4192, SRC4193 SBFS022A 1k www.ti.com 9 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FFT with 1kHz INPUT TONE at 0dBFS (192kHz:32kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:32kHz) 0 –60 –20 –70 –80 –40 –90 –100 dBFS dBFS –60 –80 –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 2.5 5k 7.5k 10k 12.5k 15k 16k 0 5k 7.5k 10k 12.5k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:44.1kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:44.1kHz) 0 –60 –20 –70 15k 16k –80 –40 –90 –60 –100 –80 dBFS dBFS 2.5k Frequency (Hz) –100 –110 –120 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 5k 10k 15k 20k 22k 0 5k Frequency (Hz) 10k 15k 20k 22k Frequency (Hz) FFT with 1kHz INPUT TONE at 0dBFS (192kHz:48kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:48kHz) 0 –60 –20 –70 –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 0 5k 10k 15k 20k 24k Frequency (Hz) 10 –110 –120 0 10k 20k 30k 40k 24k Frequency (Hz) SRC4192, SRC4193 www.ti.com SBFS022A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FFT with 1kHz INPUT TONE at 0dBFS (192kHz:96kHz) FFT with 1kHz INPUT TONE at –60dBFS (192kHz:96kHz) 0 –60 –20 –70 –80 –40 –90 –100 –80 dBFS dBFS –60 –100 –130 –120 –140 –140 –150 –160 –160 –170 –180 –180 10k 20k 30k 40k 48k 0 20k 30k 40k Frequency (Hz) FFT with 20kHz INPUT TONE at 0dBFS (44.1kHz:48kHz) FFT with 20kHz INPUT TONE at 0dBFS (48kHz:44.1kHz) 0 0 –20 –20 –40 –40 –60 –60 –80 –100 –80 –120 –140 –140 –160 –160 –180 48k –100 –120 –180 0 5k 10k 15k 20k 24k 0 5k 10k 15k 20k 22k Frequency (Hz) Frequency (Hz) FFT with 20kHz INPUT TONE at 0dBFS (48kHz:48kHz) FFT with 20kHz INPUT TONE at 0dBFS (48kHz:96kHz) 0 0 –20 –20 –40 –40 –60 –60 dBFS –80 –100 –80 –100 –120 –120 –140 –140 –160 –160 –180 –180 0 5k 10k 15k 20k 24k Frequency (Hz) 0 10k 20k 30k 40k 48k Frequency (Hz) SRC4192, SRC4193 SBFS022A 10k Frequency (Hz) dBFS dBFS 0 dBFS –110 –120 www.ti.com 11 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FFT with 80kHz INPUT TONE at 0dBFS (192kHz:192kHz) 0 0 –20 –20 –40 –40 –60 –60 –80 dBFS dBFS FFT with 20kHz INPUT TONE at 0dBFS (96kHz:48kHz) –100 –120 –120 –140 –140 –160 –160 –180 –180 0 5k 10k 15k 20k 24k 0 96k –120 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) 80k THD+N vs INPUT AMPLITUDE fIN = 1kHz (48kHz:44.1kHz) –135 –140 –145 –150 –155 –120 –100 –80 –60 –40 –20 –125 –130 –135 –140 –145 –150 –155 –160 –140 0 –120 –100 –80 –60 –40 –20 Input Amplitude (dBFS) Input Amplitude (dBFS) THD+N vs INPUT AMPLITUDE fIN = 1kHz (48kHz:96kHz) THD+N vs INPUT AMPLITUDE fIN = 1kHz (96kHz:48kHz) 0 –120 Total Harmonic Distortion+Noise (dB) –120 Total Harmonic Distortion+Noise (dB) 60k THD+N vs INPUT AMPLITUDE fIN = 1kHz (44.1kHz:48kHz) –130 –125 –130 –135 –140 –145 –150 –155 –160 –140 40k Frequency (Hz) –125 –160 –140 20k Frequency (Hz) –120 –120 –100 –80 –60 –40 –20 –125 –130 –135 –140 –145 –150 –155 –160 –140 0 Input Amplitude (dBFS) 12 –80 –100 –120 –100 –80 –60 –40 –20 0 Input Amplitude (dBFS) SRC4192, SRC4193 www.ti.com SBFS022A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. THD+N vs INPUT AMPLITUDE fIN = 1kHz (44.1kHz:192kHz) THD+N vs INPUT AMPLITUDE fIN = 1kHz (192kHz:48kHz) –120 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –120 –125 –130 –135 –140 –145 –150 –155 –160 –140 –120 –100 –80 –60 –40 –20 –140 –145 –150 –155 –120 –100 –80 –60 –40 –20 Input Amplitude (dBFS) THD+N vs INPUT FREQUENCY, 0dBFS INPUT (44.1kHz:48kHz) THD+N vs INPUT FREQUENCY, 0dBFS INPUT (48kHz:44.1kHz) 0 –120 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –135 Input Amplitude (dBFS) –125 –130 –135 –140 –145 –150 –155 –160 –125 –130 –135 –140 –145 –150 –155 –160 0 5k 10k 15k 20k 0 5k 10k 15k Input Frequency (Hz) Input Frequency (Hz) THD+N vs INPUT FREQUENCY, 0dBFS INPUT (48kHz:96kHz) THD+N vs INPUT FREQUENCY, 0dBFS INPUT (96kHz:48kHz) –120 20k –120 Total Harmonic Distortion+Noise (dB) Total Harmonic Distortion+Noise (dB) –130 –160 –140 0 –120 –125 –130 –135 –140 –145 –150 –155 –160 –125 –130 –135 –140 –145 –150 –155 –160 0 5k 10k 15k 20k 0 Input Frequency (Hz) 5k 10k 15k 20k Input Frequency (Hz) SRC4192, SRC4193 SBFS022A –125 www.ti.com 13 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. LINEARITY with fIN = 200Hz (48kHz:44.1kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 Output Amplitude (dBFS) Output Amplitude (dBFS) LINEARITY with fIN = 200Hz (44.1kHz:48kHz) Input Amplitude (dBFS) LINEARITY with fIN = 200Hz (48kHz:48kHz) LINEARITY with fIN = 200Hz (48kHz:96kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 Input Amplitude (dBFS) LINEARITY with fIN = 200Hz (96kHz:48kHz) LINEARITY with fIN = 200Hz (44.1kHz:192kHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 14 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 Input Amplitude (dBFS) 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 Input Amplitude (dBFS) Output Amplitude (dBFS) Output Amplitude (dBFS) –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 Input Amplitude (dBFS) Output Amplitude (dBFS) Output Amplitude (dBFS) –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 Input Amplitude (dBFS) SRC4192, SRC4193 www.ti.com SBFS022A TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VDD = +3.3V, and VIO = +3.3V, unless otherwise noted. FREQUENCY RESPONE with 0dBFS INPUT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 dBFS Output Amplitude (dBFS) LINEARITY with fIN = 200Hz (192kHz:44.1kHz) –140 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 0 192kHz:48kHz 192kHz:32kHz 192kHz:96kHz 0 10k 20k 30k 40k Input Amplitude (dBFS) Frequency (Hz) PASS BAND RIPPLE (48k:48k) PASS BAND RIPPLE (192k:48k) 0 50k 60k 0 –0.004 –0.009 –0.01 –0.019 (dBFS) dBFS –0.014 –0.024 –0.02 –0.03 –0.029 –0.034 –0.04 –0.039 –0.044 –0.05 –0.049 0 2k 4k 6k 8k 0 10k 12k 14k 16k 18k 20k 22k SRC4192, SRC4193 SBFS022A 5k 10k 15k 20k 22k Input Amplitude (dBFS) Frequency (Hz) www.ti.com 15 PRODUCT OVERVIEW A bypass mode is included, which allows audio data to be passed directly from the input port to the output port, bypassing the ASRC function. The bypass option is useful for passing through encoded or compressed audio data, or nonaudio control or status data. The SRC4192 and SRC4193 are asynchronous sample rate converters (ASRC) designed for professional audio applications. Operation at input and output sampling frequencies up to 212kHz is supported, with an input/output sampling ratio range of 16:1 to 1:16. Excellent dynamic range and Total Harmonic Distortion + Noise (THD+N) are achieved by employing high performance, linear phase digital filtering with better than 140dB of image rejection. Digital filtering options allow for lower group delay processing. These include a low group delay option for the interpolation and re-sampler function, as well as a direct down-sampling option for the decimation function (SRC4193 only). A soft mute function is available on both the SRC4192 and SRC4193. Digital output attenuation is available only for the SRC4193. Both soft mute and digital attenuation functions provide artifact-free operation, while allowing muting or level adjustment of the audio output signal. The mute attenuation is typically –144dB, while the digital attenuation control is adjustable from 0dB to –127.5dB in 0.5dB steps. The SRC4193 includes a three-wire SPI port, which is used to access on-chip control registers for configuration of internal functions. The port can be easily interfaced to microprocessors or digital signal processors with synchronous serial port peripherals. The audio input and output ports support standard audio data formats, as well as a TDM interface mode. Word lengths of 24-, 20-, 18-, and 16-bits are supported. Both ports may operate in Slave mode, deriving their word and bit clocks from external input and output devices. Alternatively, one port may operate in Master mode while the other remains in Slave mode. In Master mode, the LRCK and BCK clocks are derived from the reference clock input, RCKI. The flexible configuration of the input and output ports allows connection to a wide variety of audio data converters, interface devices, digital signal processors, and programmable logic. LRCKI BCKI SDIN Audio Input Port FUNCTIONAL BLOCK DIAGRAM Figure 1 shows a functional block diagram of the SRC4192 and SRC4193. Audio data is received at the input port, clocked by either the audio data source in Slave mode, or by the SRC4192/4193 in Master mode. The output port data is clocked by either the audio data source in Slave mode, or by fSIN Interpolation Filters 16fSIN Re-Sampler 16fSOUT MODE [2:0] IFMT [2:0 REFCLK OFMT [1:0] OWL [1:0] MUTE LRCKI Control Logic (SRC4192) Rate Estimator BYPAS LGRP RST LRCKO RDY RATIO (SRC4193 only) MUTE BYPASS RST CS SPI and Control Logic (SRC4193) fSOUT Decimation Filters fSOUT Direct Down-Sampler (SRC4193 only) CCLK CDATA LRCKO BCKO SDOUT Audio Output Port Mux TDMI VDD DGND RCKI Reference Clock Power REFCLK VIO DGND FIGURE 1. SRC4192/4193 Functional Block Diagram. 16 SRC4192, SRC4193 www.ti.com SBFS022A the SRC4192/4193 in Master mode. The input data is passed through interpolation filters which up-sample the data, which is then passed on to the re-sampler. The rate estimator compares the input and output sampling frequencies by comparing LRCKI, LRCKO, and a reference clock. The results include an offset for the FIFO pointer and the coefficients needed for re-sampling function. The output of the re-sampler is passed on to either the decimation filter or direct down-sampler function. The decimation filter performs down-sampling and anti-alias filtering functions, and is required when the output sampling frequency is lower than the input sampling frequency. The direct down-sampler function does not provide any filtering, and may be used in cases when aliasing is not an issue. This includes the case when the output sampling frequency is equal to or greater than the input sampling frequency. The advantage of direct down-sampling is a significant reduction in the group delay associated with the decimation filter, allowing lower latency sample rate conversion. The direct down-sampler function is available only for the SRC4193. REFERENCE CLOCK The SRC4192 and SRC4193 require a reference clock for operation. The reference clock is applied at the RCKI input (pin 1 for the SRC4193, pin 2 for the SRC4192). Figure 2 illustrates the reference clock connections and requirements for the SRC4192 and SRC4193. The reference clock may operate at 128fS, 256fS, or 512fS, where fS are the input or output sampling frequency. The maximum external reference clock input frequency is 50 MHz. RESET AND POWER DOWN OPERATION The SRC4192 and SRC4193 may be reset using the RST input (pin 13). There is no internal power on reset, so the user should force a reset sequence after power up in order to initialize the device. In order to force a reset, the reference clock input must be active, with an external clock source supplying a valid reference clock signal (refer to Figure 2). The user must assert RST low for a minimum of 500 nanoseconds and then bring RST high again to force a reset. Figure 3 shows the reset timing for the SRC4192 and SRC4193. For the SRC4193, there is an additional 500 microsecond delay after the RST rising edge, due to internal logic requirements. The customer should wait at least 500 microseconds after the RST rising edge before attempting to write to the SPI port of the SRC4193. The SRC4192 and SRC4193 also support a power-down mode. Power-down mode may be set by either holding the RST input low (SRC4192 and SRC4193), or by setting the PDN bit in Control Register 1 to zero (SRC4193 only). The SRC4193 will be in power-down mode by default after an external reset has been issued. In order to enable normal operation for the SRC4193, the customer must disable power down mode by writing a 1 to the PDN bit in Control Register 1. Finally, for the SRC4193, when using the PDN bit in Control Register 1 to enable power-down mode, the current state of the control registers is maintained through the power down /power up transition. SRC4192 SRC4193 RCKI RCKI 2 1 From External Clock Source 50MHz max From External Clock Source 50MHz max tRCKIP tRCKIP > 20ns min tRCKIH > 0.4 tRCKIP tRCKIL > 0.4 tRCKIP RCKI tRCKIH tRCKIL FIGURE 2. Reference Clock Input Connections and Timing Requirements. RCKI RST tRSTL > 500ns FIGURE 3. Reset Pulse Width Requirement. SRC4192, SRC4193 SBFS022A www.ti.com 17 AUDIO PORT MODES INPUT PORT OPERATION The SRC4192 and SRC4193 both support seven serial port modes, which are shown in Table 1. For the SRC4192, the audio port mode is selected using the MODE0 (pin 26), MODE1 (pin 27), and MODE2 (pin 28) inputs. For the SRC4193, the mode is selected using the MODE[2:0] bits in Control Register 1. The default mode setting for the SRC4193 is both input and output ports set to Slave mode. The audio input port is a three-wire synchronous serial interface that may operate in either Slave or Master mode. The SDIN input (pin 4) is the serial audio data input. Audio data is input at this pin in one of three standard audio data formats: Philips I2S, Left Justified, or Right Justified. The audio data word length may be up to 24-bits for I2S and Left Justified formats, while the Right Justified format supports 16-, 18-, 20-, or 24-bit data. The data formats are shown in Figure 4, while critical timing parameters are shown in Figure 5 and listed in the Electrical Characteristics table. In Slave mode, the port LRCK and BCK clocks are configured as inputs, and receive their clocks from an external audio device. In Master mode, the LRCK and BCK clocks are configured as outputs, being derived from the reference clock input (RCKI). Only one port can be set to Master mode at any given time, as indicated in Table 1. LRCKI MODE2 MODE1 MODE0 tLRIS SERIAL PORT MODE 0 0 0 Both Input and Output Ports are Slave mode 0 0 1 Output Port is Master mode with RCKI = 128f S 0 1 0 Output Port is Master mode with RCKI = 512f S 0 1 1 Output Port is Master mode with RCKI = 256f S 1 0 0 Both Input and Output Ports are Slave Mode 1 0 1 Input Port is Master mode with RCKI = 128f S 1 1 0 Input Port is Master mode with RCKI = 512f S 1 1 1 Input Port is Master mode with RCKI = 256f S tSIH BCKI tLDIS tSIL SDIN tLDIH FIGURE 5. Input Port Timing. TABLE 1. Setting the Serial Port Modes. Left Channel Right Channel LRCKO BCKI SDIN MSB LSB MSB LSB (a) Left Justified Data Format LRCKI BCKI MSB SDIN LSB MSB LSB (b) Right Justified Data Format LRCKI BCKI SDIN MSB LSB MSB LSB (c) I2S Data Format 1/fS FIGURE 4. Input Data Formats. 18 SRC4192, SRC4193 www.ti.com SBFS022A The bit clock is either an input or output at BCKI (pin 5). In slave mode, BCKI is configured as an input pin, and may operate at rates from 32fS to 128fS,with a minimum of one clock cycle per data bit. In Master mode, BCKI operates at a fixed rate of 64fS. The left/right word clock, LRCKI (pin 6), may be configured as an input or output pin. In Slave mode, LRCKI is an input pin, while in Master mode LRCKI is an output pin. In either case, the clock rate is equal to fS, the input sampling frequency. The LRCKI duty cycle is fixed to 50% for Master mode operation. Table 2 illustrates data format selection for the input port. For the SRC4192, the IFMT0 (pin 10), IFMT1 (pin 11), and IFMT2 (pin 12) inputs are utilized to set the input port data format. For the SRC4193, the IFMT[2:0] bits in Control Register 3 are used to select the data format. OUTPUT PORT OPERATION The audio output port is a four-wire synchronous serial interface that may operate in either Slave or Master mode. The SDOUT output (pin 23) is the serial audio data output. Audio data is output at this pin in one of four data formats: Philips I2S, Left Justified, Right Justified, or TDM. The audio data word length may be 16-, 18-, 20-, or 24-bits. For all word lengths, the data is triangular PDF dithered from the internal 28-bit data path. The data formats (with the exception of TDM mode) are shown in Figure 6, while critical timing parameters are shown in Figure 7 and listed in the Electrical Characteristics table. The TDM format and timing are shown in Figures 14 and 15, respectively, while examples of standard TDM configurations are shown in Figures 16 and 17. LRCKO IFMT2 IFMT1 IFMT0 INPUT PORT DATA FORMAT 0 0 0 24-Bit Left Justified 0 0 1 24-Bit I2S 0 1 0 Unused 0 1 1 Unused 1 1 0 0 0 1 16-Bit Right Justified 18-Bit Right Justified 1 1 0 20-Bit Right Justified 1 1 1 24-Bit Right Justified tSOH BCKO tSOL tDOPD SDOUT tDOH FIGURE 7. Output Port Timing. TABLE 2. Input Port Data Format Selection. Left Channel Right Channel LRCKO BCKO SDOUT MSB LSB MSB LSB (a) Left Justified Data Format LRCKO BCKO MSB SDOUT LSB MSB LSB (b) Right Justified Data Format LRCKO BCKO SDOUT MSB LSB MSB LSB (c) I2S Data Format 1/fS FIGURE 6. Output Data Formats. SRC4192, SRC4193 SBFS022A www.ti.com 19 The bit clock is either input or output at BCKO (pin 25). In Slave mode, BCKO is configured as an input pin, and may operate at rates from 32fS to 128fS, with a minimum of one clock cycle for each data bit. The exception is the TDM mode, where the BCKO must operate at N x 64fS, where N is equal to the number of SRC4192 or SRC4193 devices included on the TDM interface. In Master mode, BCKO operates at a fixed rate of 64fS for all data formats except TDM, where BCKO operates at the reference clock (RCKI) frequency. Additional information regarding TDM mode operation is included in the Applications Information section of this data sheet. The left/right word clock, LRCKO (pin 24), may be configured as an input or output pin. In Slave mode, LRCKO is an input pin, while in Master mode it is an output pin. In either case, the clock rate is equal to fS, the output sampling frequency. The clock duty cycle is fixed to 50% for I2S, Left justified, and Right Justified formats in Master mode. The LRCKO pulse width is fixed to 32 BCKO cycles for the TDM format in Master mode. Table 3 illustrates data format selection for the output port. For the SRC4192, the OFMT0 (pin 19), OFMT1 (pin 18), OWL0 (pin 17), and OWL1 (pin 16) inputs are utilized to set the output port data format and word length. For the SRC4193, the OFMT[1:0] and OWL[1:0] bits in Control Register 3 are used to select the data format and word length. OFMT1 OFMT0 OUTPUT PORT DATA FORMAT 0 0 Left Justified 0 1 I2S 1 0 TDM 1 1 Right Justified OWL1 OWL0 OUTPUT PORT DATA WORD LENGTH 0 0 24-Bits 0 1 20-Bits 1 0 18-Bits 1 1 16-Bits The soft mute function of the SRC4192 and SRC4193 may be invoked by forcing the MUTE input (pin 14) high. For the SRC4193, the mute function may also be accessed using the MUTE bit in Control Register 1. The Soft mute function slowly attenuates the output signal level down to all zeroes plus ±1LSB of dither. This provides an artifact-free muting of the audio output port. DIGITAL ATTENUATION (SRC4193 ONLY) The SRC4193 includes independent digital attenuation for the Left and Right audio channels. The attenuation ranges from 0dB (or unity) to -127.5dB in 0.5dB steps. The attenuation settings are programmed using Control Registers 4 and 5, corresponding to the Left and Right channels, respectively. The TRACK bit in Control Register 1 is used to select Independent or Tracking attenuation modes. When TRACK = 0, the Left and Right channels are controlled independently. When TRACK = 1, the attenuation setting for the Left channel is also used for the Right channel, and the Right channel is said to track the Left channel attenuation setting. READY OUTPUT The SRC4192 and SRC4193 include an active low ready output named RDY (pin 15). This is an output from the rate estimator block, which indicates that the input-to-output sampling frequency ratio has been determined. The ready signal can be used as a flag or indicator output. The ready signal can also be connected to the active high MUTE input (pin 14) to provide an auto-mute function, so that the output port is muted when the rate estimator is in transition. RATIO OUTPUT (SRC4193 ONLY) TABLE 2. Output Port Data Format Selection. BYPASS MODE The SRC4192 and SRC4193 include a bypass function, which routes the input port data directly to the output port, bypassing the ASRC function. Bypass mode may be invoked by forcing the BYPAS input (pin 9) high for either the SRC4192 or SRC4193. For the SRC4193, the bypass mode may also be accessed using the BYPAS bit in Control Register 1. For normal ASRC operation, the BYPAS pin and control bit should be set to 0. No dithering is applied to the output data in bypass mode, and the digital attenuation and mute functions are also unavailable. 20 SOFT MUTE FUNCTION The SRC4193 includes a simple ratio flag output named RATIO (pin 16). When RATIO is low, it indicates that the output sampling frequency is lower than the input sampling frequency. When RATIO is high, it indicates that the output sampling frequency is higher than the input sampling frequency. The ratio output can be used as an indicator or flag output for an LED or host device. SERIAL PERIPHERAL INTERFACE (SPI) PORT: SRC4193 ONLY The SPI port is a three-wire synchronous serial interface used to access the on-chip control registers of the SRC4193. The interface is comprised of a serial data clock input, CCLK (pin 27), a serial data input, CDATA (pin 28), and an active low chip-select input, CS (pin 26). Figure 8 illustrates the protocol for writing control registers via the serial control port. Figure 9 shows the critical timing parameters for the SPI port interface, which are also listed in the Electrical Characteristics table. SRC4192, SRC4193 www.ti.com SBFS022A Set CS = 1 here to write one register or buffer location. Keep CS = 0 to enable auto-increment mode. CS Header Byte 0 CDIN Register or Buffer Data Byte 2 Byte 3 Byte 1 Byte N CCLK BYTE DEFINITION MSB BYTE 0: 0 LSB 0 0 0 0 A2 A1 A0 Register Address Set to 0. Set to 0. Byte 1: All 8 bits are Don’t Care. Set to 0 or 1. Bytes 2 through N: Register Data. All Bytes are written MSB first. FIGURE 8. SPI Port Protocol. tCFCS CS tCSCR tCDS CCLK tCDH CDATA FIGURE 9. SPI Port Timing. Byte 0 indicates the address of the control register to be written. The two most significant bits are set to 0, while the six least significant bits contain the control register address. Byte 1 is a don’t care byte. This byte is included in the protocol in order to maintain compatibility with current and future Texas Instruments’ digital audio products, including the DIT4096 and DIT4192 digital audio transmitters. Byte 2 contains the 8-bit data for the control register addressed in Byte 0. to be written. The address is automatically incremented by 1 after each byte is written as long as the CS input remains low. This is referred to as auto-increment operation, and is always enabled for the SPI port. CONTROL REGISTER MAP (SRC4193 ONLY) The control register map for the SRC4193 is shown in Table 4. Register 0 is reserved for factory use and defaults to all zeros upon reset. The user should avoid writing this register, as unexpected operation may result if Register 0 is programmed to an arbitrary value. Registers 1 through 5 contain control bits, which are used to configure the internal functions of the SRC4193. All other register addresses are reserved and should not be used in customer applications. As shown in Figure 8, a write sequence starts by bringing the CS input low. Bytes 0, 1, and 2 are then written to program a single control register. Bringing the CS input high after the third byte will write just one register. However, if CS remains low after writing the first control byte, the port will autoincrement the address by 1, allowing successive addresses Register Address (Dec/Hex) D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) 0 1 2 3 4 5 0 PDN 0 OWL1 AL7 AR7 0 TRACK 0 OWL0 AL6 AR6 0 0 0 OFMT1 AL5 AR5 0 MUTE 0 OFMT0 AL4 AR4 0 BYPAS 0 0 AL3 AR3 0 MODE2 0 IFMT2 AL2 AR2 0 MODE1 DFLT IFMT1 AL1 AR1 0 MODE0 LGRP IFMT0 AL0 AR0 TABLE 4. The SRC4193 Control Register Map. SRC4192, SRC4193 SBFS022A www.ti.com 21 CONTROL REGISTER DEFINITIONS (SRC4193 ONLY) This section contains detailed descriptions for each control register. Reset defaults are also defined for each register bit. Register 1: System Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) PDN TRACK 0 MUTE BYPAS MODE2 MODE1 MODE0 MODE[2:0] Audio Serial Port Mode BYPAS MODE2 MODE1 MODE0 Audio Serial Port Mode 0 0 0 Both Serial Ports are in Slave Mode (Default) 0 0 1 Output Serial Port is Master with RCKI = 128fs 0 1 0 Output Serial Port is Master with RCKI = 512fs 0 1 1 Output Serial Port is Master with RCKI = 256fs 1 0 0 Both Serial Ports are in Slave Mode 1 0 1 Input Serial Port is Master with RCKI = 128fs 1 1 0 Input Serial Port is Master with RCKI = 512fs 1 1 1 Input Serial Port is Master with RCKI = 256fs Bypass Mode This bit is logically OR’d with the BYPAS input (pin 9) BYPAS MUTE Function 0 Bypass Mode Disabled with normal ASRC operation. (Default) 1 Bypass Mode Enabled with data routed directly from the input port to the output port, bypassing the ARSC function. Output Soft Mute This bit is logically OR’d with the MUTE input (pin 14) MUTE TRACK 0 Soft Mute Disabled (Default) 1 Soft Mute Enabled with data attenuated to all 0’s Digital Attenuation Tracking TRACK PDN Output Mute Function Attenuation Tracking 0 Tracking Off: Attenuation for the Left and Right channels is controlled independently. (Default) 1 Tracking On: Left channel attenuation setting is used for both channels. Power Down Setting this bit to 0 will set the SRC4193 to the power-down state. All other register settings are preserved and the SPI port remains active. (Default) Setting this bit to 1 will power up the SRC4193 using the current register settings. 22 SRC4192, SRC4193 www.ti.com SBFS022A Register 2: Filter Control Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 DFLT LGRP LGRP Low Group Delay This bit is used to select the number of input audio samples to be stored in the data buffer before the ASRC starts processing the audio data. LGRP DFLT Group Delay 0 Normal Delay, 64 samples. (Default) 1 Low Delay, 32 samples. Decimation Filtering / Direct Down-Sampling The DFLT bit is used to enable or disable the direct down-sampling function. DFLT Decimation Filter Operation 0 Decimation Filter Enabled (Default) (Must be used when fsOUT is less than fsIN) 1 Direct Down-Sampling enabled without filtering. (May be enabled when fsOUT is equal to or greater than fsIN) Register 3: Audio Data Format Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) OWL1 OWL0 OFMT1 OFMT0 0 IFMT2 IFMT1 IFMT0 IFMT[2:0] OFMT[1:0] OWL[1:0] Input Port Data Format IFMT2 IFMT1 IFMT0 Input Format 0 0 0 24-Bit Left Justified (Default) 0 0 1 24-Bit I2S 0 1 0 - Not Used - 0 1 1 - Not Used - 1 0 0 Right Justified, 16-Bit Data 1 0 1 Right Justified, 18-Bit Data 1 1 0 Right Justified, 20-Bit Data 1 1 1 Right Justified, 24-Bit Data Output Port Data Format OFMT1 OFMT0 0 0 Output Format Left Justified (Default) 0 1 I2S 1 0 TDM 1 1 Right Justified Output Port Data Word Length OWL1 OWL0 Output Word Length 0 0 24-Bits (Default) 0 1 20-Bits 1 0 18-Bits 1 1 16-Bits SRC4192, SRC4193 SBFS022A www.ti.com 23 Register 4: Digital Attenuation Register – Left Channel Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 Register defaults to 00HEX, or 0dB (unity gain). Output Attenuation (dB) = (–N x 0.5), where N = AL[7:0]DEC Register 5: Digital Attenuation Register – Right Channel Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 Register defaults to 00HEX, or 0dB (unity gain). Output Attenuation (dB) = (–N x 0.5), where N = AR[7:0]DEC When the TRACK bit in Control Register 1 is set to 1, the Left Channel attenuation setting will be used for the Right Channel attenuation. APPLICATIONS INFORMATION RECOMMENDED CIRCUIT CONFIGURATION This section of the data sheet provides practical applications information for hardware and systems engineers who will be designing the SRC4192 and SRC4193 into their end equipment. Typical connection diagrams for the SRC4192 and SRC4193 are shown in Figures 10 and 11, respectively. Recommended values for power supply bypass capacitors are included. These capacitors should be placed as close to the IC package as possible. From Control Logic SRC4192 1 2 3 Reference Clock 4 5 6 7 8 9 10 11 12 13 14 Audio Input Device From/To Control Logic LGRP RCKI NC MODE2 MODE1 MODE0 SDIN BCKI LRCKI VIO DGND BYPAS IFMT0 IFMT1 IFMT2 RST MUTE BCKO LRCKO SDOUT VDD DGND TDMI OFMT0 OFMT1 OWL0 OWL1 RDY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD = +3.3V VIO = +1.65V to VDD To Pin 7 10µF Audio Output Device To Pin 22 0.1µF 0.1µF To Pin 8 10µF To Pin 21 FIGURE 10. Typical Connection Diagram for the SRC4192. 24 SRC4192, SRC4193 www.ti.com SBFS022A Host (MCU, DSP) SRC4193 1 2 3 Reference Clock 4 5 6 7 8 9 10 11 12 13 14 Audio Input Device To/From Host or Control Logic RCKI NC NC CDATA CCLK CS SDIN BCKI LRCKI VIO DGND BYPAS NC NC NC RST MUTE BCKO LRCKO SDOUT VDD DGND TDMI NC NC NC RATIO RDY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD = +3.3V VIO = +1.65V to VDD To Pin 7 10µF Audio Output Device To Pin 22 0.1µF 10µF 0.1µF To Pin 8 To Pin 21 FIGURE 11. Typical Connection Diagram for the SRC4193. INTERFACING TO DIGITAL AUDIO RECEIVERS AND TRANSMITTERS SRC4192, SRC4193 DIR1703 The SRC4192 and SRC4193 input and output ports are designed to interface to a variety of audio devices, including receivers and transmitters commonly used for AES/EBU, S/PDIF, and CP1201 communications. LRCKO AES3, S/PDIF Input RCV DIN LRCKI BCKO BCKI DATA SDIN SCKO Texas Instruments manufactures the DIR1703 digital audio interface receiver and DIT4096/4192 digital audio transmitters to address these applications. RCLI Clock Generator Figure 12 illustrates interfacing the DIR1703 to the SRC4192 or SRC4193 input port. The DIR1703 operates from a single +3.3V supply, which requires the VIO supply (pin 7) for the SRC4192 or SRC4193 to be set to +3.3V for interface compatibility. Clock Select Assumes VIO = +3.3V for SRC4192, SRC4293 FIGURE 12. Interfacing the SRC4193 to the DIR1703 Digital Audio Interface Receiver. SRC4192, SRC4193 SBFS022A www.ti.com 25 Figure 13 shows the interface between the SRC4192 or SRC4193 output port and the DIT4096 or DIT4192 audio serial port. Once again, the VIO supplies for both the SRC4192/4193 and DIT4096/4192 are set to +3.3V for compatibility. Like the SRC4192 or SRC4193 output port, the DIT4096 and DIT4192 audio serial port may be configured as a Master or Slave. In cases where the SRC4192/4193 output port is set to Master mode, it is recommended to use the reference clock source (RCKI) as the master clock source (MCLK) for the DIT4096/4192, to ensure that the transmitter is synchronized to the SRC4192/4193 output port data. DIT4096, DIT4192 SRC4192, SRC4193 TDM APPLICATIONS LRCKO SYNC TX+ BCKO SCLK TX– AES3, S/PDIF OUTPUT The SRC4192 and SRC4193 support a TDM output mode, which allows multiple devices to be daisy-chained together to create a serial frame. Each device occupies one subframe within a frame, and each sub-frame carries two channels (Left followed by Right). Each sub-frame is 64 bits long, with 32 bits allotted for each channel. The audio data for each channel is left justified within the allotted 32 bits. Figure 14 illustrates the TDM frame format, while Figure 15 shows TDM input timing parameters, which are listed in the Electrical Characteristics table of this data sheet. SDATA SDOUT RCKI MCLK REF Clock Generator DIT Clock Generator Clock Select Assumes VIO = +3.3V for SRC4192, SRC4293 and DIT4096, DIT4192 FIGURE 13. Interfacing the SRC4193 to the DIT4096/4192 Digital Audio Interface Transmitter. LRCKO BCKO SDOUT Left Right Left Sub-Frame 1 Right Sub-Frame 2 Left Right Sub-Frame N One Frame = 1/fs N = Number of Daisy-Chained Devices One Sub-Frame contains 64 bits, with 32 bits per channel. For each channel, the audio data is left justified, MSB first format, with the word length determined by the OWL[1:0] pins/bits. FIGURE 14. TDM Frame Format. tLROS LRCKO tLROH BCKO tTDMS TDMI tTDMH FIGURE 15. Input Timing for TDM Mode. 26 SRC4192, SRC4193 www.ti.com SBFS022A The frame rate is equal to the output sampling frequency, fs. The BCKO frequency for the TDM interface is N*64fs, where N is the number of devices included in the daisy chain. For Master mode, the output BCKO frequency is fixed to the reference clock (RCKI) input frequency. The number of devices that can be daisy-chained in TDM mode is dependent upon the output sampling frequency and the BCKO frequency, leading to the following numerical relationship: Figures 16 and 17 show typical connection schemes for TDM mode. Although the TMS320C671x DSP family is shown as the audio processing engine in these figures, other TI digital signal processors with a multi-channel buffered serial port (McBSPTM) may also function with this arrangement. Interfacing to processors from other manufacturers is also possible. Refer to Figure 7 in this data sheet, along with the equivalent serial port timing diagrams shown in the DSP data sheet, to determine compatibility. Number of Daisy-Chained Devices = (fBCKO / fs) / 64 Where: fBCKO = Output Port Bit Clock (BCKO), 27.648 MHz maximum fs = Output Port Sampling (or LRCKO) Frequency, 216kHz maximum. This relationship holds true for both Slave and Master modes. SRC4192, SRC4193 Slave #N SRC4192, SRC4193 Slave #2 SRC4192, SRC4193 Slave #1 TDMI TDMI TDMI SDOUT SDOUT TMS320C671x McBSP SDOUT DRn FSRn LRCKO LRCKO LRCKO BCKO BCKO BCKO RCKI RCKI RCKI n = 0 or 1 CLKRn CLKIN or CLKSn Clock Generator FIGURE 16. TDM Interface where all Devices are Slaves. SRC4192, SRC4193 Master SRC4192, SRC4193 Slave #2 SRC4192, SRC4193 Slave #1 TDMI TDMI TDMI TMS320C671x McBSP SDOUT DRn LRCKO LRCKO LRCKO FSRn BCKO BCKO BCKO RCKI RCKI RCKI SDOUT SDOUT n = 0 or 1 CLKRn CLKIN or CLKSn Clock Generator FIGURE 17. TDM Interface where one Device is Master to Multiple Slaves. SRC4192, SRC4193 SBFS022A www.ti.com 27 PIN COMPATIBILITY WITH THE ANALOG DEVICES AD1896 (SRC4192 ONLY) The SRC4192 is pin-and function-compatible with the AD1896 when observing the guidelines indicated in the following paragraphs. Power Supplies. To ensure compatibility, the VDD_IO and VDD_CORE supplies of the AD1896 must be set to +3.3V, while the VIO and VDD supplies of the SRC4192 must be set to +3.3V. Crystal Oscillator. The SRC4192 does not have an on-chip crystal oscillator. An external reference clock is required at the RCKI input (pin 2). Master Mode Maximum Sampling Frequency. When the input or output ports are set to Master mode, the maximum sampling frequency must be limited to 96kHz in order to support the AD1896 specification. This is despite the fact that the SRC4192 supports a maximum sampling frequency of 212kHz in Master mode. The user should consider building an option into his or her design to support the higher sampling frequency of the SRC4192. Matched Phase Mode. Due to the internal architecture of the SRC4192, it does not require or support the matched phase mode of the AD1896. Given multiple SRC4192 devices, if all reference clock (RCKI) inputs are driven from the same clock source, the devices will be phase matched. Reference Clock Frequency. The reference clock input frequency for the SRC4192 must be no higher than 30 MHz, in order to match the master clock frequency specification of the AD1896. In addition, the SRC4192 does not support the 768fS reference clock rate. 28 SRC4192, SRC4193 www.ti.com SBFS022A PACKAGE DRAWING DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°– 8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 SRC4192, SRC4193 SBFS022A www.ti.com 29 PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY SRC4192IDB ACTIVE SSOP DB 28 50 SRC4192IDBR ACTIVE SSOP DB 28 2000 SRC4193IDB ACTIVE SSOP DB 28 50 SRC4193IDBR ACTIVE SSOP DB 28 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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