TAS5101 SLES039 – JUNE 2002 TRUE DIGITAL STEREO AUDIO AMPLIFIER WITH PWM STEREO POWER OUTPUT STAGE FEATURES D 2 × 15 W High-Quality Digital Amplifier Power D D D D D D D D D Stage Single-Ended Output >95-dB Dynamic Range (TDAA System) THD+N < 0.1% (1 kHz, 1 W to 15 W RMS Into 4 Ω) Power Efficiency > 90% Into 4-Ω to 8-Ω Load Low Profile, SMD 32-Pin PowerPAD Package Requires No Heat-Sink When Using Recommended Layout 2 × 15-W RMS Continuous Power Into 4 Ω Self-Protecting Design 3.3-V Digital Interface EMI Compliant When Used With Recommended System Design APPLICATIONS D Digital TV Audio Amplifier D Car Audio Amplifiers and Head Units D Internet Music Appliance D Mini/Micro Component Systems DESCRIPTION The TAS5101 is a high-performance true digital stereo audio amplifier (TDAA) Power Stage, designed to drive 2 × 15 watts per channel. The TAS5101 incorporates TI’s equibitt technology and is used in conjunction with a Digital Audio PWM processor (TAS50xx) to deliver high-power, true digital audio amplification. The efficiency of this digital amplifier can be greater than 90%, reducing the size of both the power supplies and heat sinks needed. The TAS5101 accepts a stereo PWM 3.3V input and controls the switching of an internal CMOS H-bridge. When used with the TAS50xx PWM Processor, system performance of less than 0.09% THD is attainable. Over-current protection, over-temperature, and under-voltage protections are built into the TAS5101, safeguarding the H-bridge and speakers against output shorts, over-voltage conditions, and other fault conditions that could damage the system. TYPICAL TDAA STEREO AUDIO SYSTEM L-C Filter Digital Audio • TAS3001 • TAS3103 • DSP • DIR1703 • 1394 • • • • • Volume EQ DRC Bass Treble TAS5010 TAS5101 L-C Filter • Serial Audio Input Port • Internal PLL • PCM–PWM Modulator • 2 × 15 W Single-Ended H-Bridge Power Devices NOTE: The TAS5000 in NOT recommended for use with the TAS5101 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and Equibit are trademarks of Texas Instruments. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 TAS5101 SLES039 – JUNE 2002 terminal assignments The TAS5101 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP). DAP PACKAGE (TOP VIEW) PWM_AP PWM_AM ERR1 ERR0 SHUTDOWN DVDD DVSS DVSS DVSS VRFILT BIAS_A BIAS_B HiZ RESET PWM_BM PWM_BP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PVDDA2 LDROUTA BOOTSTRAPA PVDDA1 PVDDA1 OUTPUTA OUTPUTA PVSS PVSS OUTPUTB OUTPUTB PVDDB1 PVDDB1 BOOTSTRAPB LDROUTB PVDDB2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ordering information TA 0°C to 70°C PACKAGE TAPE and Reel TAS5101DAP TAS5101DAPR –40°C to 85°C TAS5101IDAP TAS5101IDAPR references TAS5010 Digital Audio PWM Processor Data Manual – TI Literature Number SLAS328 System Design Considerations for True Digital Audio Power Amplifiers – TI Literature Number SLAA117 Digital Audio Measurements – TI Literature Number SLAA114 PowerPAD Thermally Enhanced Package – TI Literature Number SLMA002 TAS5101_SE Application Report – TI Literature Number SLEA001 suggested system block diagrams See application note SLAA117 for more details. Digital Audio • TAS3001 • TAS3103 • DSP • DIR1703 • 1394 • Digital Parametric EQ • Volume • DRC • Bass • Treble L-C Filter TAS5010 TAS5101 L-C Filter • Serial Audio Input Port • Internal PLL • 2 × 1/2 H-Bridge Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor 2 www.ti.com TAS5101 SLES039 – JUNE 2002 PVDDA1 PVDDA1 BOOTSTRAPA PVDDA2 LDROUTA functional block diagram 1/2 H-Bridge LDR OUTPUTA PWM_AP PWM_AM DIFF RCVR OUTPUTA Boot Strap Gate Drive PVSS BIAS_A HiZ RESET SHUTDOWN ERR1 ERR0 Control/Sense Circuit Bandgap Reference LDROUTB PVDDB2 VRFILT BOOTSTRAPB PVDDB1 1/2 H-Bridge BIAS_B PVDDB1 LDR DIFF RCVR OUTPUTB Boot Strap Gate Drive OUTPUTB PVSS DVSS PWM_BP DVDD PWM_BM www.ti.com 3 TAS5101 SLES039 – JUNE 2002 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BIAS_A 11 I Connect external resistor to DVSS. See application note SLAA117 BIAS_B 12 I Connect external resistor to DVSS. See application note SLAA117 BOOTSTRAPA 30 O Bootstrap capacitor pin for H-bridge A BOOTSTRAPB 19 O Bootstrap capacitor pin for H-bridge B DVDD 6 I 3.3-V digital voltage supply for logic DVSS 7, 8, 9 I Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not connected externally to PVSS. See Figure 5. ERR1 3 O Error/warning report indicator. This output is open drain with internal pullup resistor. ERR0 4 O Error/warning report indicator. This output is open drain with internal pullup resistor. LDROUTA 31 O Low voltage drop-out regulator output A (not to be used to supply current to external circuitry) LDROUTB 18 O Low voltage drop-out regulator output B (not to be used to supply current to external circuitry) OUTPUTA 26, 27 O H-bridge output A OUTPUTB 22, 23 O H-bridge output B PVDDA1 28, 29 I High voltage power supply, H-bridge A PVDDA2 32 I High voltage power supply for low-dropout voltage regulator A-side PVDDB1 20, 21 I High voltage power supply, H-bridge B PVDDB2 17 I High voltage power supply for low-dropout voltage regulator B-side PVSS 24, 25 I High voltage power supply ground HiZ 13 I HiZ = 0, when asserted, the H-bridge output is set to high-impedance mode PWM_AP 1 I PWM input A(+) PWM_AM 2 I PWM input A(–) PWM_BP 16 I PWM input B(+) PWM_BM 15 I PWM input B(–) RESET 14 I Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low output state. Asserting the RESET signal low causes all fault conditions to be cleared. SHUTDOWN 5 O Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0. The shutdown condition can be cleared by asserting the RESET signal. This output is open drain with internal pullup resistor. VRFILT 10 O A filter capacitor should be added between VRFILT and DVSS pins. NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5010 output pins, and never left floating. Floating PWM input pins will cause an illegal PWM input state signal to be asserted. Dual pins: OUTPUTA, OUTPUTB, PVDDA1 and PVDDB1 must have both pins connected externally to the same point on the circuit board, respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires and can cause the device to fail. All electrical characteristics are specified and measured with all of the multiple pins connected to the same node, respectively. 4 www.ti.com TAS5101 SLES039 – JUNE 2002 functional description PWM H-bridge state control The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals are a complementary differential signal format for the A-side H-bridge and the B-side H-bridge. bootstrapped gate drive The TAS5101 includes 2 dedicated bootstrapped power supplies. A bootstrap capacitor is connected between the individual bootstrap pin and the associated output as described in the application note SLAA117. For example, a capacitor will be connected between the BOOTSTRAPA pin and OUTPUTA pin, and another capacitor will be connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power supply minimizes the number of high voltage power supply levels externally supplied to the system while providing a low noise supply level for driving the high-side N-channel DMOS transistors. See application note SLAA117 for details. low-dropout voltage regulator Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for external circuitry. Each LDO is dedicated to an H-bridge and its gate driver. An LDO output capacitor is connected between the individual LDO output pin and the associated output return as described in the application note SLAA117. For example, a capacitor will be connected between the LDROUTA pin and PVSS pin, and another capacitor will be connected between the LDROUTB pin and PVSS pin. This capacitor is usually 0.1 µF. high-current H-bridge output stage The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output mapping section below. When the TAS5101 is in the normal mode, as seen in the H-bridge output mapping tables, the outputs are decoded from the inputs. However, the TAS5101 is immediately shut down if any of the following error conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified in the H-bridge output mapping section, and the SHUTDOWN pin is set low. H-bridge output mapping The A-side and B-side H-bridge output is designed to the following truth table: INPUTS OUTPUTS DESCRIPTION RESET HiZ PWM_AP/BP PWM_AM/BM SHUTDOWN X X X X 0 OUTPUTA/B 0 or Hi-Z† X 0 X X 1 Hi-Z High Impedance 0 1 X X 1 0 Low 1 1 0 0 0 0 Low 1 1 0 1 1 0 Normal 1 1 1 0 1 1 Normal 1 1 1 1 0 0 † Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current. www.ti.com Shutdown Low 5 TAS5101 SLES039 – JUNE 2002 control/sense circuitry The control/sense circuitry consists of the following 3.3-V logic level pins: HiZ, RESET, ERR0, ERR1, and SHUTDOWN. The active-low HiZ input pin powers down all internal circuitry and forces the H-bridge outputs to the Hi-Z state. When the HiZ pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also disabled so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs to the low-low state and resets the over-current shutdown latch. The HiZ pin overrides the RESET pin. The ERR0, ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5101 as shown in the table below. These three outputs are open-drain connections with internal pullup resistors so that wire-ORed connections can be made by the user with other external control devices. The short circuit protect error condition will latch the TAS5101 in this shutdown state and force the H-bridge outputs to the Hi-Z state until the device is reset by means of the RESET pin. The illegal PWM input state, over-temperature, and low regulator voltage error conditions will not latch the device in the shutdown condition. Instead the H-bridge outputs are forced to the low-low state and the TAS5101 will return to normal operation as soon as the error condition ends. Loss of clocking PWM signal is also considered an illegal PWM input state. 6 SHUTDOWN ERR1 ERR0 FUNCTION 0 0 0 Illegal PWM input state Low Low 0 0 1 Short circuit protect (latch) Hi-Z Hi-Z 0 1 0 Over temperature protect Low Low 0 1 1 Low regulator voltage protect Low Low 1 0 0 Reserved — — 1 0 1 Reserved — — 1 1 0 High temperature – warning Normal Normal 1 1 1 Normal operation Normal Normal www.ti.com OUTPUTA OUTPUTB TAS5101 SLES039 – JUNE 2002 device operation power sequences system power-up/power-down sequencing The recommended power-up/power-down sequence is shown in Figure 3. For proper operation the RESET signal should be kept LOW when both DVDD and output power (PVDDA1, PVDDA2, PVDDB1, and PVDDB2) are being applied. The RESET signal should remain LOW for at least 1 ms after output power is applied. DVDD > 1 ms > 1 ms PVDDA1 PVDDA2 PVDDB1 PVDDB2 > 100 ms RESET/HiZ NOTE: This power-up/power-down sequence will ensure that there are no device reliability issues. However, audio artifacts during power cycling may occur (see TAS5101_SE Application Report (SLEA001) for more information). Figure 2. Power-Up/Power-Down Sequence RESET function The device is put into a reset condition when the (active low) RESET signal is asserted. While in the reset state, the input H-bridge control signals consisting of PWM_AP, PWM_AM, PWM_BP, and PWM_BM are ignored, and the H-bridge MOSFETs are placed in a state where OUTPUTA and OUTPUTB are both low. Asserting the RESET signal low also causes the short circuit protection latch to be reset. The RESET and HiZ signals are normally connected to the VALID signal from the TAS5010, when used in a single-ended configuration. HiZ function The HiZ function places the output MOSFETs in a high-impedance state when this function is asserted by placing pin 13 at logic low. This function is usually used in conjunction with the RESET function during power on and off to reduce or eliminate “pops and clicks” associated with powering the amplifier. reinitialization sequence Proper initial conditions for this device include asserting the RESET and HiZ signals until the reset operation has completed (1 ms). Additionally, when using this device with the TAS5010 controller, this function can be accomplished by asserting the reset pin on the TAS5010 during the reset sequence (see Figure 3). audio application considerations power supply decoupling Power supply decoupling and layout optimization information should be obtained by following the detailed information in the application note SLEA005. optimal power transfer for H-bridge The TAS5101 is a power H-bridge that is designed to deliver 2 × 15 W/rms into loads of 4 Ω in a single-ended configuration. Rather than requiring the usual heatsink, the package is designed to deliver this wattage by careful layout as described in the application note SLAA117. Careful attention must be given to the value of the high-voltage power supply level for a given load resistance. See recommended operating conditions. www.ti.com 7 TAS5101 SLES039 – JUNE 2002 audio application considerations (continued) reconstruction output filter An output reconstruction filter is required between the H-bridge outputs and the loudspeaker load. This second order low-pass filter passes the audio information to the loudspeaker, while filtering out the high frequency out-of-band information contained in the H-bridge output PWM pulses. The values of the L and C components selected are dependent on the loudspeaker load impedance. See application note SLAA117. fault indicator usage The TAS5101 is a self-protecting device that provides device fault reporting, including over-temperature protect, under-voltage lockout (low-regulator voltage), and short circuit protection. The short circuit protection protects against short circuits that may occur at the loudspeaker load when configured according to the application note SLAA117. The TAS5101 is not recommended for driving loads less than 4 Ω, since the internal current limit protection might be activated. An under-voltage lockout signal occurs when an insufficient voltage level is present on the LDROUTA or LDROUTB pins. During this condition gate drive levels are not sufficient for driving the power MOSFETs. Normal operation is resumed when the minimum proper LDROUTA or LDROUTB level is obtained, and the low regulator voltage protect signal is de-asserted. See the control/sense circuitry section for error and warning conditions. A high temperature warning signal is asserted on pin ERR0 when the device temperature exceeds 125°C typical. If the internal device temperature exceeds 150°C typical, the over temperature protect signal is asserted and the TAS5101 is shut down. The device will re-enable once the temperature drops to 125°C typical. See the control/sense circuitry section for error and warning conditions. Detection of an illegal PWM input state or the loss of a clocking PWM input signal will cause an illegal PWM input state signal to be asserted on the ERR1and ERR0 pins and will set the SHUTDOWN pin to the low state. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† DC supply voltage range: DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.5 V PWM_AP, PWM_AM, PWM_BP, PWM_BM . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V RESET, HiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V PVDDA1 to PVSS, PVDDB1 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 28 V PVDDA2 to PVSS, PVDDB2 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 28 V Output DMOS drain-to-source breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 8 www.ti.com TAS5101 SLES039 – JUNE 2002 recommended operating conditions (nominal output power = 2 × 15 W (RMS), TA = 25°C) thermal data† PARAMETER MIN NOM MAX UNIT Shutdown junction temperature, TJ(SD) 150 °C Warning junction temperature, TJ(W) 125 °C Commercial Operating ambient temperature temperature, TA Industrial 0 25 70 –40 25 85 °C Thermal resistance junction-to-ambient, θja 2 oz. trace and copper pad with solder 23.5 °C/W Thermal resistance junction-to-case, θjc 2 oz. trace and copper pad without solder 0.32 °C/W Thermal resistance junction-to-ambient, θja 2 oz. trace and copper pad without solder 44.3 °C/W † One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and solderable), deep downset pad. See Appendix A of the PowerPAD Thermally Enhanced Package application note, TI literature number SLMA002 and the Thermal Design of the PowerPad PCB Layout section of the System Design Considerations for True Digital Audio Power Amplifiers application note, TI literature number SLAA117. RL = 4 Ω to 8 Ω Digital Supply y voltage g Regulator PARAMETER MIN NOM MAX DVDD to DVSS 3 3.3 3.6 PVDDA2 to PVSS 16.5 26.5 28 PVDDB2 to PVSS 16.5 26.5 28 PVDDA2 to PVSS} 10.5 16.5 PVDDB2 to PVSS} 10.5 16.5 UNIT V V † If PVDD is greater than 26.5 V, 15 Watts per channel is still the maximum specified continuous output power. ‡ If using a PVVD power supply less than 16.5 V, connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition H-Bridge forward on-state resistance is increased. This will increase internal power dissipation. Maximum output power may need to be reduced to meet thermal conditions. maximum available power at common load impedance for DAP package unclipped (0 dB) level LOAD IMPEDANCE (Ω) APPROXIMATE MAX OUTPUT POWER (W) 15 THD+N AT MAX POWER AND 1 kHz INPUT† 4 PVDAA1/PVDDB1 (VDC) 26.5 6 27 12.85 < 0.09% 8 27 9.64 < 0.09% < 0.1% † Dependent on board design and component selection. www.ti.com 9 TAS5101 SLES039 – JUNE 2002 static digital specifications RESET, HiZ, PWM_AP, PWM_AM, PWM_BP, PWM_BM, TA = 25°C, DVDD = 3.3 V PARAMETERS MIN High-level input voltage, VIH MAX 2 Low-level input voltage, VIL Input leakage current UNIT V 0.8 V 10 µA –10 ERR0, ERR1, SHUTDOWN, (open drain with internal pullup resistor) TA = 25°C, DVDD = 3.3 V) PARAMETERS MIN Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD MAX 15 Low-level output voltage (IO = 4 mA), VOL UNIT kΩ 0.4 V TAS5010/TAS5101 system performance measured at the speaker terminals See the TI Literature Number SLAA117 for TAS5010/TAS5101 system performance. electrical characteristics supply, TA = 25°C (Fswitching = 384 kHz, OUTPUTA and OUTPUTB not connected, DVDD = 3.3 V, PVDDA1 = 26.5 V, PVDDB1 = 26.5 V, PVDDA2 = 26.5 V, PVDDB2 = 26.5 V, 50% input duty cycle) PARAMETER Supply current TYP MAX UNIT DVDD Operating 2 mA PVDDA1+PVDDB1+ PVDDA2+PVDDB2 Operating† 20 mA † 13-kΩ resistor from BIAS_A (pin 11) to DVSS and 13-kΩ resistor from BIAS_B (pin 12) to DVSS. H-Bridge transistors, PVDDA2 = PVDDB2 = 22 V, DVDD = 3.3 V, TA = 25°C (unless otherwise noted) PARAMETER Drain-to-source breakdown voltage TEST CONDITIONS Forward on-state resistance, low-side drivers OUTPUTA and OUTPUTB to PVSS ID = 1 mA, HiZ = 0, Hi-Z state ISINK = 2.5 A, PWM_AP = PWM_BP = 0, See Notes 2, 3, and 4, PWM_AM = PWM_BM = 1 Forward on-state resistance, high-side drivers PVDDA1 to OUTPUTA, PVDDB1 to OUTPUTB ISOURCE = 2.5 A, See Notes 2, 3, and 5, MIN TYP MAX 28 PWM_AP = PWM_BP = 1, PWM_AM = PWM_BM = 0 UNIT V 0.2 Ω 0.2 Ω On-state resistance matching low side 98% On-state resistance matching high side 98% NOTES: 1. Test time should be < 1 ms to avoid temperature change. 2. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 3. Connect PVDDA2 and PVDDB2 to 26.5-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and BOOTSTRAPB pins open. 4. Connect PVDDA2 to 26.5-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA and BOOTSTRAPB capacitors are connected respectively. Clock PWM inputs to allow bootstrap capacitors to charge. 93–99% modulation must be used on PWM_AP, PWM_AM, PWM_BP, and PWM_BM inputs to prevent the activity detector from shutting down the device during this measurement. Note that Fswitching = 384 kHz. electrical characteristics, voltage regulator, TA = 25°C (unless otherwise noted) PARAMETER Output voltage (LDROUTA, LDROUTB) TEST CONDITIONS IO = 5 mA, See Note 6, PVDDA2 = PVDDB2 = 18 V to 28 V, DVDD = 3.3 V MIN TYP MAX 14.5 15.3 16 UNIT V NOTE 5: These voltage regulators are for internal gate drive circuits only and are not to be used under any circumstances to supply current to external circuity. 10 www.ti.com TAS5101 SLES039 – JUNE 2002 THERMAL INFORMATION The thermally enhanced DAP package is based on the 32-pin HTSSOP, but includes a thermal pad (see Figure 4) to provide an effective thermal contact between the IC and the PWB. Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO-220 type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, have two shortcomings: they do not address the very low profile requirements (<2 mm) of many of today’s advanced systems, and they do not offer a terminal-count high enough to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits. The PowerPAD package (thermally enhanced HTSSOP) combines fine-pitch surface-mount technology with thermal performance comparable to much larger power packages. The PowerPAD package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a HTSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a patented lead-frame design and manufacturing technique to provide a direct connection to the heat-generating IC. When this pad is soldered or otherwise thermally coupled to an external heat dissipater, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. DIE Thermal Pad Side View (a) DIE End View (b) Bottom View (c) Figure 3. Views of Thermally Enhanced DAP Package www.ti.com 11 TAS5101 SLES039 – JUNE 2002 APPLICATION INFORMATION TAS5010 C11 TAS5101 1 PWM_BP 2 PWM_BM 3 RESET Error Reporting 4 5 VALID_L 6 PWM_AM 7 C10 8 PWM_AP 9 C9 10 R1 R2 11 12 PWM_AP PVDDA2 PWM_AM LDROUTA ERR1 BOOTSTRAPA ERR0 PVDDA1 SHUTDOWN DVDD DVSS PVDDA1 OUTPUTA OUTPUTA PVSS DVSS PVSS VRFILT OUTPUTB BIAS_A OUTPUTB BIAS_B PVDDB1 HiZ PVDDB1 14 RESET 26.5 V 31 30 C8 29 C7 Snubber Circuit 28 27 L1 26 C1 25 DVSS 13 32 BOOTSTRAPB 15 PWM_BM LDROUTB PWM_BP PVDDB2 16 24 C2 23 22 L2 21 Snubber Circuit 20 19 C5 C6 18 17 26.5 V 26.5 V C3 R3 C4 NOTE: C1, C2 = 1.0 µF C3, C4 = 470 µF C5, C8 = 0.033 µF C6, C7 = 0.1 µF C9, C10 = 0.1 µF C11, C12 = 0.1 µF R1, R2 = 13 kΩ R3, R4 =4.7 kΩ L1, L2 = 10 µH Figure 4. Typical TAS5101 Application (One Channel Shown) See the application note, TI literature number SLEA001 for detailed application information. 12 www.ti.com R4 TAS5101 SLES039 – JUNE 2002 MECHANICAL DATA DAP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 38 PINS SHOWN 0,30 0,19 0,65 38 0,13 M 20 Thermal Pad (see Note D) 6,20 NOM 8,40 7,80 0,15 NOM Gage Plane 1 19 0,25 A 0°–ā8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 28 30 32 38 A MAX 9,80 11,10 11,10 12,60 A MIN 9,60 10,90 10,90 12,40 DIM 4073257/A 07/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. Thermal pad size is 3,86 mm X 3,91 mm for the 32-pin TAS5101 device. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments. www.ti.com 13 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated