® XTR101 Precision, Low Drift 4-20mA TWO-WIRE TRANSMITTER FEATURES APPLICATIONS ● INSTRUMENTATION AMPLIFIER INPUT Low Offset Voltage, 30µV max Low Voltage Drift, 0.75µV/°C max Low Nonlinearity, 0.01% max ● INDUSTRIAL PROCESS CONTROL Pressure Transmitters Temperature Transmitters Millivolt Transmitters ● TRUE TWO-WIRE OPERATION Power and Signal on One Wire Pair Current Mode Signal Transmission High Noise Immunity ● RESISTANCE BRIDGE INPUTS ● THERMOCOUPLE INPUTS ● RTD INPUTS ● CURRENT SHUNT (mV) INPUTS ● PRECISION DUAL CURRENT SOURCES ● DUAL MATCHED CURRENT SOURCES ● WIDE SUPPLY RANGE: 11.6V to 40V ● –40°C to +85°C SPECIFICATION RANGE ● AUTOMATED MANUFACTURING ● POWER/PLANT ENERGY SYSTEM MONITORING ● SMALL 14-PIN DIP PACKAGE, CERAMIC AND PLASTIC DESCRIPTION The XTR101 is a microcircuit, 4-20mA, two-wire transmitter containing a high accuracy instrumentation amplifier (IA), a voltage-controlled output current source, and dual-matched precision current reference. This combination is ideally suited for remote signal conditioning of a wide variety of transducers such as thermocouples, RTDs, thermistors, and strain gauge bridges. State-of-the-art design and laser-trimming, wide temperature range operation and small size make it very suitable for industrial process control applications. In addition, the optional external transistor allows even higher precision. The two-wire transmitter allows signal and power to be supplied on a single wire-pair by modulating the power supply current with the input signal source. The transmitter is immune to voltage drops from long runs and noise from motors, relays, actuators, switches, transformers, and industrial equipment. It can be used by OEMs producing transmitter modules or by data acquisition system manufacturers. IREF1 Optional External Transistor IREF2 10 e1 3 +VCC 11 – 8 5 (1) 12 XTR101 Span B 6 e2 4 + (1) 13 1 2 14 7 9 E IOUT Optional Offset Null NOTE: (1) Pins 12 and 13 are used for optional BW control. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1986 Burr-Brown Corporation PDS-627G Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL At TA = +25°C, +VCC = 24VDC, and RL = 100Ω with external transistor connected, unless otherwise noted XTR101AG PARAMETER CONDITIONS MIN TYP XTR101BG MAX MIN 20 22 38 ±10 ±20 ±40 ±40 ✻ ✻ TYP XTR101AP MAX MIN ✻ ✻ ✻ ±6 ±15 ±30 ✻ ✻ ✻ TYP XTR101AU MAX MIN ✻ ✻ ✻ ±19 ±20 ±60 ✻ ✻ ✻ TYP MAX UNITS ✻ ✻ ✻ ±19 ±60 ✻ mA mA mA µA ppm, FS/°C µA VDC ✻ ✻ Ω Ω OUTPUT AND LOAD CHARACTERISTICS Current Linear Operating Region Derated Performance Current Limit Offset Current Error vs Temperature Full Scale Output Current Error Power Supply Voltage Load Resistance SPAN Output Current Equation Span Equation vs Temperature Untrimmed Error(2) Nonlinearity Hysteresis Dead Band INPUT CHARACTERISTICS Impedance: Differential Common-Mode Voltage Range, Full Scale Offset Voltage vs Temperature Power Supply Rejection Bias Current vs Temperature Offset Current vs Temperature Common-Mode Rejection(4) Common-Mode Range CURRENT SOURCES Magnitude Accuracy 4 3.8 IOS, IO = 4mA ∆IOS /∆T Full Scale = 20mA VCC, Pins 7 and 8, +11.6 Compliance(1) At VCC = +24V, IO = 20mA At VCC = +40V, IO = 20mA RS in Ω, e1 and e2 in V RS in Ω Excluding TCR of RS εSPAN εNONLINEARITY –5 28 ±3.9 ±10.5 ±20 ✻ ±2.5 ±8 ±15 ✻ ±100 0 0.01 ✻ 0 0 0 110 90 ±30 ±0.75 125 60 0.30 10 0.1 100 4 ✻ 150 1 ±30 0.3 ✻ vs Temperature vs VCC vs Time Compliance Voltage Ratio Match Accuracy vs Tempeature vs VCC vs Time Output Impedance With Respect to Pin 7 Tracking (1 – IREF1/IREF2) X 100% ±0.06 ±50 ±3 ±8 0 10 TEMPERATURE RANGE Specification Operating Storage –40 –55 –55 ±0.17 ±80 ±10 ±1 20 ✻ ±30 ±0.75 ✻ ✻ ✻ ✻ ±20 ✻ ✻ ✻ ±0.025 ±30 ✻ ✻ ✻ ±0.06 ±15 ✻ ✻ ✻ ✻ +85 +125 +165 ✻ ✻ ✻ ✻ ✻ ✻ 122 ✻ ✻ ✻ ✻ ✻ ✻ ±0.075 ±50 ✻ ±0.04 10 ✻ ±100 ✻ ✻ 110 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ –40 –40 –55 ✻ ✻ 122 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±100 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±0.37 ✻ ✻ ±0.031 ✻ ✻ ✻ ✻ ✻ ✻ ±0.2 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±0.009 ✻ ✻ ✻ ✻ VCC – 3.5 ±0.014 ±20 ±0.35 ✻ ✻ ✻ ✻ ✻ ✻ ✻ 6 1 VCC = 24V, VPIN 8 – V PIN 10, 11 = 19V R2 = 5kΩ, Fig. 5 iO = 4mA + [0.016Ω + (40/RS)] (e2 – e1) S = [0.016Ω + (40/RS)] ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 1 ±60 ±1.5 31 ±8.5 ✻ ±30 600 1400 ✻ ✻ 0.4 || 3 10 || 3 ∆e = (e2 – e1)(3) VOS ∆VOS/∆T ∆VCC/PSRR = VOS Error IB ∆IB/∆T IOSI ∆IOSI/∆T DC e1 and e2 with Respect to Pin 7 ✻ ✻ ✻ 600 1400 ±30 –2.5 31 ±8.5 ±10.5 ±30 ±0.2 ✻ ✻ ✻ ✻ ±0.088 ✻ ✻ ✻ 15 ✻ +85 +85 +125 ✻ –40 –55 GΩ || pF GΩ || pF V µV µV/°C dB nA nA/°C nA nA/°C dB V mA ±0.37 ✻ ✻ ±0.031 A/V ppm/°C % % % % % ppm/°C ppm/V ppm/month V ±0.088 ✻ % ppm/°C ppm/V ppm/month MΩ ✻ +85 +125 °C °C °C ✻ ✻ 15 ✻ Same as XTR101AG. NOTES: (1) See Typical Performance Curves. (2) Span error shown is untrimmed and may be adjusted to zero. (3) e1 and e2 are signals on the –In and +In terminals with respect to the output, pin 7. While the maximum permissible ∆e is 1V, it is primarily intended for much lower input signal levels, e.g., 10mV or 50mV full scale for the XTR101A and XTR101B grades respectively. 2mV FS is also possible with the B grade, but accuracy will degrade due to possible errors in the low value span resistance and very high amplification of offset, drift, and noise. (4) Offset voltage is trimmed with the application of a 5V common-mode voltage. Thus the associated common-mode error is removed. See Application Information section. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® XTR101 2 PIN CONFIGURATION Top View DIP Zero Adjust 1 14 Zero Adjust Zero Adjust 2 13 Bandwidth –In 3 12 B Control +In 4 Span 5 Span Out DIP 11 IREF2 10 IREF1 6 9 7 8 Top View E +VCC Power Supply, +VCC ........................................................................... 40V Input Voltage, e1 or e2 ........................................................ ≥VOUT, ≤+VCC Storage Temperature Range, Ceramic ........................ –55°C to +165°C Plastic ............. –55°C to +125°C Lead Temperature (soldering 10s) G, P ...................................... +300°C (wave soldering, 3s) U .......................... +260°C Output Short-Circuit Duration ........................... Continuous +VCC to IOUT Junction Temperature ................................................................... +165°C PACKAGE XTR101AG XTR101BG XTR101AP XTR101AU 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Plastic DIP 16-Lead SOIC 169 169 010 211 to to to to 16 Zero Adjust Zero Adjust 2 15 Bandwidth –In 3 14 B Control 13 IREF2 SOL-16 Surface-Mount +In 4 Span 5 12 IREF1 Span 6 11 E Out 7 10 +VCC NC 8 9 NC ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TEMPERATURE RANGE –40°C –40°C –40°C –40°C 1 This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. PACKAGE/ORDERING INFORMATION PRODUCT Zero Adjust ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS PACKAGE DRAWING NUMBER(1) SOIC +85°C +85°C +85°C +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 XTR101 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VCC = 24VDC, unless otherwise noted. SPAN vs FREQUENCY STEP RESPONSE 25 CC = 0 RS = 25Ω Ω RS = ∞ 20 60 Output Current (mA) Transconductance (20 Log m ) 80 RS = 100Ω RS = 400Ω 40 RS = 2kΩ RS = ∞ 20 RS = 25Ω 15 10 5 0 0 100 1k 10k 100k 1M 0 200 400 Frequency (Hz) 600 800 1000 Time (µs) FULL SCALE INPUT VOLTAGE vs RS RS (kΩ) 0 2 4 6 8 COMMON-MODE REJECTION vs FREQUENCY 0.08 0.8 0.06 0.6 120 0.04 0.4 0.02 0.2 80 CMR (dB) 0 to 800mV and 0 to 8kΩ scale ∆eIN Full Scale (V) ∆eIN Full Scale (V) 100 40 20 0 to 80mV (low level signals) and 0 to 400Ω scale 0 0 0 100 200 60 300 0 400 0.1 1 10 RS (Ω) POWER SUPPLY REJECTION vs FREQUENCY 1k 10k 100k BANDWIDTH vs PHASE COMPENSATION 140 100k 120 10k 100 Bandwidth (Hz) Power Supply Rejection (dB) 100 Frequency (Hz) 80 60 40 RS = ∞ 1k RS = 400Ω RS = 100Ω 100 RS = 25Ω 10 1 20 0 0.1 10 0.1 100 1k 10k 100k 1M 10M 1 ® XTR101 10 100 1k 10k Bandwidth Control, CC (pF) Frequency (Hz) 4 100k 1M TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, +VCC = 24VDC, unless otherwise noted. INPUT CURRENT NOISE DENSITY vs FREQUENCY INPUT VOLTAGE NOISE DENSITY vs FREQUENCY 6 Input Noise Current (pA/ Hz ) Input Noise Voltage (nV/ Hz ) 60 50 40 30 20 10 0 5 4 3 2 1 0 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) OUTPUT CURRENT NOISE DENSITY vs FREQUENCY Output Noise Current (nA/ Hz ) 6 5 4 3 2 1 0 1 10 100 1k 10k 100k Frequency (Hz) THEORY OF OPERATION since IO is unipolar e2 must be kept larger than e1; i.e., e2 ≥ e1 or eIN ≥ 0. Also note that in order not to exceed the output upper range limit of 20mA, eIN must be kept less than 1V when RS = ∞ and proportionately less as RS is reduced. A simplified schematic of the XTR101 is shown in Figure 1. Basically the amplifiers, A1 and A2, act as a single power supply instrumentation amplifier controlling a current source, A3 and Q1. Operation is determined by an internal feedback loop. e1 applied to pin 3 will also appear at pin 5 and similarly e2 will appear at pin 6. Therefore the current in RS, the span setting resistor, will be IS = (e2 – e1)/RS = eIN/RS. This current combines with the current, I3, to form I1. The circuit is configured such that I2 is 19 times I1. From this point the derivation of the transfer function is straightforward but lengthy. The result is shown in Figure 1. INSTALLATION AND OPERATING INSTRUCTIONS BASIC CONNECTION The basic connection of the XTR101 is shown in Figure 1. A difference voltage applied between input pins 3 and 4 will cause a current of 4-20mA to circulate in the two-wire output loop (through RL, VPS, and D1). For applications requiring moderate accuracy, the XTR101 operates very cost-effectively with just its internal drive transistor. For more demanding applications (high accuracy in high gain) an external NPN transistor can be added in parallel with the internal one. This keeps the heat out of the XTR101 package Examination of the transfer function shows that IO has a lower range-limit of 4mA when eIN = e2 – e1 = 0V. This 4mA is composed of 2mA quiescent current exiting pin 7 plus 2mA from the current sources. The upper range limit of IO is set to 20mA by the proper selection of RS based on the upper range limit of eIN. Specifically RS is chosen for a 16mA output current span for the given full scale input voltage span; i.e., (0.016 + 40/RS)(eIN full scale) = 16mA. Note that Ω ® 5 XTR101 eIN – + RS (e1) IS 5 6 I3 I4 R3 1.25kΩ (e1) IB1 +VCC R4 1.25kΩ A1 –In3 eIN (e2) +VCC A2 +VCC 8 D1 IB2 VPS +In4 (e2) 100µA 7 IO + eL Q1 +VCC +VCC I1 R1 1kΩ 2mA – RL A3 R2 52.6Ω I2 IO Voltage Controlled Current Source 11 I REF2 IO = 4mA + (0.016 2.5kΩ Ω 10 IREF1 + 40/RS) eIN, eIN = e2 – e1 FIGURE 1. Simplified Schematic of the XTR101. and minimizes thermal feedback to the input stage. Also in such applications where eIN full scale is small (<50mV) and RSPAN is small (<150Ω), caution should be taken to consider errors from the external span circuit plus high amplification of offset drift and noise. tions shown in Figure 2. Thus the 2N2222 will safely operate below its 400mW rating at the upper temperature of +85°C. Heat sinking the 2N2222 will result in greatly reduced accuracy improvement and is not recommended. 2. TIP29B in the TO-220 package. This transistor will operate over the specified temperature and output voltage range without a series collector resistor. Heat sinking the TIP29B will result in slightly less accuracy improvement. It can be done, however, when mechanical constraints require it. OPTIONAL EXTERNAL TRANSISTOR The optional external transistor, when used, is connected in parallel with the XTR101’s internal transistor. The purpose is to increase accuracy by reducing heat change inside the XTR101 package as the output current spans from 4-20mA. Under normal operating conditions, the internal transistor is never completely turned off as shown in Figure 2. This maintains frequency stability with varying external transistor characteristics and wiring capacitance. The actual “current sharing” between internal and external transistors is dependent on two factors: (1) relative geometry of emitter areas and (2) relative package dissipation (case size and thermal conductivity). For best results, the external device should have a larger base-emitter area and smaller package. It will, upon turn on, take about [0.95 (IO – 3.3mA)]mA. However, it will heat faster and take a greater share after a few seconds. ACCURACY WITH AND WITHOUT EXTERNAL TRANSISTOR The XTR101 has been tested in a circuit using an external transistor. The relative difference in accuracy with and without an external transistor is shown in Figure 3. Notice that a dramatic improvement in offset voltage change with supply voltage is evident for any value of load resistor. MAJOR POINTS TO CONSIDER WHEN USING THE XTR101 1. The leads to RS should be kept as short as possible to reduce noise pick-up and parasitic resistance. Although any NPN of suitable power rating will operate with the XTR101, two readily available transistors are recommended. 2. +VCC should be bypassed with a 0.01µF capacitor as close to the unit as possible (pin 8 to 7). 3. Always keep the input voltages within their range of linear operation, +4V to +6V (e1 and e2 measured with respect to pin 7). 1. 2N2222 in the TO-18 package. For power supply voltages above 24V, a 750Ω, 1/2W resistor should be connected in series with the collector. This will limit the power dissipation to 377mW under the worst-case condi® XTR101 6 4mA 20mA 16mA +VCC 8 750Ω (2) 12V, 200mW 3.5mA 0.5mA XTR101 B 12 QEXT 23.6V, 377mW 2N2222 QINT 18mW (1) Other Suitable Types Package Type 9 E 3.47V, 60mW 210Ω 2N4922 TIP29B TIP31B 1.5mA Quiescent 0.95V, 17mW 52.6Ω 7 IOUT 11 Short Circuit Worst Case 10 1mA VPS 40V TO-225 TO-220 TO-220 1mA RL 250Ω 18mA 20mA 2mA NOTES: (1) An external transistor is used in the maufacturing test circuit for testing electrical specifications. (2) This resistor is required for the 2N2222 with VPS > 24V to limit power dissipation. FIGURE 2. Power Calculation of XTR101 with External Transistor. 50 ∆VOS (µV) Without external transistor 20 RL = Ω 100 40 00Ω 15 RL kΩ 10 RL 0 10 30 =6 =1 With external transistor 10 RL = 1kΩ RL = 600Ω RL = 100Ω 20 Load Resistance, RL (Ω ) 25 5 1500 60 Span = ∆IO = 16mA Self-Heating ∆ Temperature (°C) 30 30 RL max = 1000 VPS – 11.6V 20mA 750 Operating Region 500 250 0 0 20 1250 0 40 VCC (V) 10 20 30 40 50 60 Power Supply Voltage, VPS (V) FIGURE 3. Thermal Feedback Due to Change in Output Current. FIGURE 4. Power Supply Operating Range. 4. The maximum input signal level (eINFS) is 1V with RS = ∞ and proportionally less as RS decreases. 6. Always choose RL (including line resistance) so that the voltage between pins 7 and 8 (+VCC) remains within the 11.6V to 40V range as the output changes between the 4-20mA range (see Figure 4). 5. Always return the current references (pins 10 and 11) to the output (pin 7) through an appropriate resistor. If the references are not used for biasing or excitation, connect them together to pin 7. Each reference must have between 0V and +(VCC – 4V) with respect to pin 7. 7. It is recommended that a reverse polarity protection diode (D1 in Figure 1) be used. This will prevent damage to the XTR101 caused by a momentary (e.g., transient) or long term application of the wrong polarity of voltage between pins 7 and 8. ® 7 XTR101 Figure 6 shows a similar connection for a resistive transducer. The transducer could be excited either by one (as shown) or both current sources. Also, the offset adjustment has higher resolution compared to Figure 5. 8. Consider PC board layout which minimizes parasitic capacitance, especially in high gain. SELECTING RS RSPAN is chosen to that a given full scale input span eINFS will result in the desired full scale output span of ∆IOFS, ) + (40/RS)] ∆eIN = ∆IO = 16mA. Solving for RS: 40 ∆IO/∆eIN – 0.016 (1) Ω RS = If the inputs are biased at some other CMV then an input offset error term is (CMV – 5)/CMRR; CMR is in dB, CMRR is in V/V. For example, if ∆eINFS = 100mV for ∆IOFS = 16mA, 40 40 = 16mA/100mV) – 0.016 0.16 – 0.016 RS = SIGNAL SUPPRESSION AND ELEVATION In some applications it is desired to have suppressed zero range (input signal elevation) or elevated zero range (input signal suppression). This is easily accomplished with the XTR101 by using the current sources to create the suppression/elevation voltage. The basic concept is shown in Figures 7 and 8(a). In this example the sensor voltage is derived from RT (a thermistor, RTD, or other variable resistance element) excited by one of the 1mA current sources. The other current source is used to create the elevated zero range voltage. Figures 8(b), (c) and (d) show some of the possible circuit variations. These circuits have the desirable feature of noninteractive span and suppression/elevation adjustments. Note: It is not recommended to use the optional offset voltage null (pins 1, 2 and 14) for elevation/suppression. This trim capability is used only to null the amplifier’s input offset voltage. In many applications the already low offset voltage (typically 20µV) will not need to be nulled at all. Adjusting the offset voltage to nonzero values will disturb the voltage drift by ±0.3µV/°C per 100µV or induced offset. 40 = = 278Ω 0.144 See Typical Performance Curves for a plot of RS vs ∆eINFS. Note that in order not to exceed the 20mA upper range limit, eIN must be less than 1V when RS = ∞ and proportionately smaller as RS decreases. BIASING THE INPUTS Because the XTR operates from a single supply both e1 and e2 must be biased approximately 5V above the voltage at pin 7 to assure linear response. This is easily done by using one or both current sources and an external resistor R2. Figure 5 shows the simplest case— a floating voltage source e'2. The 2mA from the current sources flows through the 2.5kΩ value of R2 and both e1 and e2 are raised by the required 5V with respect to pin 7. For linear operation the constraint is +4V ≤ e1 ≤ +6V +4V ≤ e2 ≤ +6V The offset adjustment is used to remove the offset voltage of the input amplifier. When the input differential voltage (eIN) equals zero, adjust for 4mA output. e1 3 1mA 11 – + eIN – 8 5 – 2mA eIN RS Adj. + 6 e2 4 e'2 8 RS XTR101 0.01µF 6 + 24V + eL – RL – 4-20 mA 4 XTR101 e2 0.01µF + 24V + + 2 1 1MΩ + 10 5 D1 10 0.01µF R2 2.5kΩ 2mA +5V 14 eL – RL 7 + e2 – 2 14 1 100kΩ 1MΩ IO = 4mA + (0.016 Alternate circuitry shown in Figure 8. + 40 )eIN RS 7 Offset Adjust R2 2.5kΩ IO Offset Adjust 2mA +5V IO = 4mA + (0.016 + 40 )eIN RS eIN = e'2 = 1mA X RT 0.01µF eIN = e2 FIGURE 6. Basic Connection for Resistive Source. FIGURE 5. Basic Connection for Floating Voltage Source. ® XTR101 + RT – Ω e1 3 1mA D1 11 – Ω Ω [(0.016 CMV AND CMR The XTR101 is designed to operate with a nominal 5V common-mode voltage at the input and will function properly with either input operating over the range of 4V to 6V with respect to pin 7. The error caused by the 5V CMV is already included in the accuracy specifications. 8 20 at the transducer. Thus the XTR101 is, in general, very suitable for individualized and special purpose applications. Span Adjust EXAMPLE 1 RTD Transducer shown in Figure 9. 10 Elevated Zero Range Given a process with temperature limits of +25°C and +150°C, configure the XTR101 to measure the temperature with a platinum RTD which produces 100Ω at 0°C and 200Ω at +266°C (obtained from standard RTD tables). Transmit 4mA for +25°C and 20mA for +150°C. Suppressed Zero Range 5 COMPUTING RS: 0 The sensitivity of the RTD is ∆R/∆T = 100Ω/266°C. When excited with a 1mA current source for a 25°C to 150°C range (i.e., 125°C span), the span of eIN is 1mA X (100Ω/266°C) X 125°C = 47mV = ∆eIN. –0+ eIN (V) FIGURE 7. Elevation and Suppression Graph. From equation 1, RS = 1mA 1mA 1mA – eIN – RS = RT – RT e'2 40 = 123.3Ω 0.3244 = Span adjustment (calibration) is accomplished by trimming RS. + V4 R4 COMPUTING R4: – 2mA eIN = (e'2 +V4) V4 = 1mA X R4 e'2 = 1mA X RT (a) Elevated Zero Range (b) Suppressed Zero Range 2mA At +25°C, e'2 = 1mA (RT + ∆RT) 2mA eIN = (e'2 –V4) V4 = 1mA X R4 e'2 = 1mA X RT – e'2 In order to make the lower range limit of 25°C correspond to the output lower range limit of 4mA, the input circuitry shown in Figure 9 is used. – eIN + + eIN, the XTR101 differential input, is made 0 at 25°C or + R4 e'2 25°C – V4 = 0 + + e'2 – V4 100Ω X 25°C] 266°C = 1mA (109.4Ω) = 109.4mV = 1mA [100Ω + 2mA – eIN + – 40 16mA/47mV – 0.016 + e'2 + R4 – V4 ∆IO/∆eIN – 0.016Ω – eIN + + + V4 1mA 40 Ω i0 (mA) 15 R4 thus, V4 = e'2 25°C = 109.4mV – R4 = 2mA 2mA eIN = (e'2 –V4) eIN = (e'2 +V4) V4 = 2mA X R4 V4 = 2mA X R4 (c) Elevated Zero Range (d) Suppressed Zero Range V4 = 109.4mV 1mA = 109.4Ω 1mA COMPUTING R2 AND CHECKING CMV: At +25°C, e'2 = 109.4mV FIGURE 8. Elevation and Suppression Circuits. At +150°C, e'2 = 1mA (RT + ∆RT) APPLICATION INFORMATION = 1mA [100Ω +( The small size, low offset voltage and drift, excellent linearity, and internal precision current sources, make the XTR101 ideal for a variety of two-wire transmitter applications. It can be used by OEMs producing different types of transducer transmitter modules and by data acquisition systems manufacturers who gather transducer data. Current mode transmission greatly reduces noise interference. The two-wire nature of the device allows economical signal conditioning = 156.4mV 100Ω X 150°C)] 266°C Since both e'2 and V4 are small relative to the desired 5V common-mode voltage, they may be ignored in computing R2 as long as the CMV is met. R2 = 5V/2mA = 2.5kΩ e2 min = 5V + 0.1094V e2 max = 5V + 0.1564V The +4V to +6V CMV requirement is met. e1 = 5V + 0.1094V ® 9 XTR101 e1 3 11 – 1mA D1 10 8 RS XTR101 4 R4 e2 + 24V + eL – RL – 7 + + e1 – 0.01µF 6 + V4 – 11 10 – 8 R6 51Ω eIN XTR101 Thermocouple TTC 4 + e'2 – 3 D 5 – eIN + 1mA R5 2kΩ VTC RT R2 + V4 – + e2 – R4 Temperature T1 7 + 0.01µF 2.5kΩ Temperature T2 = TD 0.01µF FIGURE 9. Circuit for Example 1. FIGURE 10. Thermocouple Input Circuit with Two Temperature Regions and Diode (D) Cold Junction Compensation. EXAMPLE 2 Thermocouple Transducer shown in Figure 10. With eIN = 0 and VTC = –1.28mV, V4 = e1 + eIN – VTC Given a process with temperature (T1) limits of 0°C and +1000°C, configure the XTR101 to measure the temperature with a type J thermocouple that produces a 58mV change for 1000°C change. Use a semiconductor diode for a cold junction compensation to make the measurement relative to 0°C. This is accomplished by supplying a compensating voltage, VR6, equal to that normally produced by the thermocouple with its “cold junction” (T2) at ambient. At a typical ambient of +25°C this is 1.28mV (obtained from standard thermocouple tables with reference junction of 0°C). Transmit 4mA for T1 = 0°C and 20mA for T1 = +1000°C. Note: eIN = e2 – e1 indicates that T1 is relative to T2. = 14.9mV + 0V – (–1.28mV) 1mA (R4) = 16.18mV R4 = 16.18Ω COLD JUNCTION COMPENSATION: The temperature reference circuit is shown in Figure 11. The diode voltage has the form VD = Typically at T2 = +25°C, VD = 0.6V and ∆VD/∆T = –2mV/°C. R5 and R6 form a voltage divider for the diode voltage VD. The divider values are selected so that the gradient ∆VD/∆T equals the gradient of the thermocouple at the reference temperature. At +25°C this is approximately 52µV/°C (obtained from standard thermocouple table); therefore, ESTABLISHING RS: The input full scale span is 58mV (∆eINFS = 58mV). RS is found from equation (1) 40 40 = 16mA/58mV – 0.016 Ω ∆IO/∆eIN – 0.016 Ω RS = 40 = = 153.9Ω 0.2599 ∆TC/∆T = ∆VD/∆T R6 R5 + R6 52µV/°C = 2000µV/°C SELECTING R4: R4 is chosen to make the output 4mA at TTC = 0°C (VTC= –1.28mV) and TD = +25°C (VD = 0.6V). A circuit is shown in Figure 10. (2) R6 R5 + R6 R5 is chosen as 2kΩ to be much larger than the resistance of the diode. Solving for R6 yields 51Ω. VTC will be –1.28mV when TTC = 0°C and the reference junction is at +25°C. e1 must be computed for the condition of TD = +25°C to make eIN = 0V. THERMOCOUPLE BURN-OUT INDICATION In process control applications it is desirable to detect when a thermocouple has burned out. This is typically done by forcing the two-wire transmitter current to either limit when VD 25°C = 600mV e1 25°C = 600mV (51/2051) = 14.9mV eIN = e2 – e1 = VTC + V4 – e1 ® XTR101 IDIODE KT ln q ISAT 10 1mA 0.0047µF 1mA R3(1) R5 + VD – + V5 3 11 – 1mA – C2 D R6 + V6 – XTR101 R1 R4(1) R2 FIGURE 11. Cold Junction Compensation Circuit. 4 13 + 12 C1 NOTE: (1) R3 and R4 should be equal if used. the thermocouple impedance goes very high. The circuits of Figures 16 and 17 inherently have down scale indication. When the impedance of the thermocouple gets very large (open) the bias current flowing into the + input (large impedance) will cause IO to go to its lower range limit value (about 3.8mA). If up scale indication is desired the circuit of Figure 18 should be used. When the TC opens the output will go to its upper range limit value (about 25mA or higher). Internally eNOISE RTI = e2INPUT STAGE + e2OUTPUT STAGE Gain FIGURE 12. Optional Filtering. APPLICATION CIRCUITS Voltage Reference + OPTIONAL INPUT OFFSET VOLTAGE TRIM The XTR101 has provisions for nulling the input offset voltage associated with the input amplifiers. In many applications the already low offset voltages (30µV max for the B grade, 60µV max for the A grade) will not need to be nulled at all. The null adjustment can be done with a potentiometer at pins 1, 2 and 14 as shown in Figures 5 and 6. Either of these two circuits may be used. NOTE: It is not recommended to use this input offset voltage nulling capability for elevation or suppression. See the Signal Suppression and Elevation section for the proper techniques. MC1403A VR = 2.5V – 100pF XTR101 V+ IO (4-20mA) OPA27 V– R1 125Ω R2 500Ω IO(1) (0-20mA) OPTIONAL BANDWIDTH CONTROL Low-pass filtering is recommended where possible and can be done by either one of two techniques shown in Figure 12. C2 connected to pins 3 and 4 will reduce the bandwidth with a cutoff frequency given by, fCO 2 NOTE: (1) IO = 1 + R1 R2 IO – VR R2 = 1.25 IO – 5mA Other conversions are readily achievable by changing the reference and ratio of R1 to R2. 15.9 = (R1 + R2 + R3 + R4) (C2 + 3pF) FIGURE 13. 0-20mA Output Converter. This method has the disadvantage of having fCO vary with R1, R2, R3, R4, and it may require large values of R3 and R4. The other method, using C1, will use smaller values of capacitance and is not a function of the input resistors. It is, however, more subject to nonlinear distortion caused by slew rate limiting. This is normally not a problem with the slow signals associated with most process control transducers. The relationship between C1 and fCO is shown in the Typical Performance Curves. ® 11 XTR101 2mA 0.9852mA 1.0147mA 1.8kΩ – R R LM129 6.9V Voltage Ref 300Ω R RS XTR101 R + 0.01µF 4.7kΩ FIGURE 14. Bridge Input, Voltage Excitation. 1mA 2mA R R 300Ω + – XTR101 RS – Type J – R R This circuit has down scale burn-out indication. 1mA 15Ω 20Ω RTD 100Ω RS XTR101 Zero Adjust J + + 2.2kΩ 2.5kΩ FIGURE 15. Bridge Input, Current Excitation. 1mA FIGURE 16. Thermocouple Input with RTD Cold Junction Compensation. 1mA This circuit has down scale burn-out indication. 1mA 2kΩ + – Type J + – 51Ω 20Ω RS XTR101 20Ω 15Ω RS XTR101 Zero Adjust 2.5kΩ 2.5kΩ FIGURE 17. Thermocouple Input with Diode Cold Junction Compensation. FIGURE 18. Thermocouple Input with RTD Cold Junction Compensation. ® XTR101 RTD 100Ω – – + + Zero Adjust This circuit has up scale burn-out indication. 1mA 12 11 I1 I2 10 +VCC 8 +VCC – 3 OPA21 15V 0.01µF R1 XTR101 + 7 VREF Out R2 4 2.5kΩ VREF = ImA R2 FIGURE 19. Dual Precision Current Sources Operated From One Supply. Isolation Barrier 8 –V2 ∆eIN 1kΩ E 7 1µF V– + 30V – XTR101 1µF V+ 722 C1 +V1 –V1 4-20mA +15V P+ +V2 C2 – +15V 1MΩ + 10 + 12 15 7 250Ω –15V 1MΩ 2 4 3 ISO100 9 VOUT(1) +1V to +5V 8 IREF2 17 – 16 18 IREF1 NOTE: (1) Can be shifted and amplified using ISO100 current sources. FIGURE 20. Isolated Two-Wire Current Loop. ® 13 XTR101 A. AT THE LOWER RANGE VALUE (T = +25°C). DETAILED ERROR ANALYSIS The ideal output current is σO = IOS RTO = ±6µA iO IDEAL = 4mA + K eIN K is the span (gain) term, (0.016Ω + (40/RS)) σI = VOSI + (IB1 ∆R + IOS1 R4) + (3) In the XTR101 there are three major components of error: + 1. σO = errors associated with the output stage. 2. σS = errors associated with span adjustment. 3. σI = errors associated with the input stage. ACTUAL CMRR ∆VCC = (24 X 0.005) + 4mA (250Ω + 100Ω) + 0.6V = 120mV + 1400mV + 600mV = 2120mV (4) When this expression is expanded, second order terms (σS σ1) dropped, and terms collected, the result is iO PSRR ∆R = RT 25°C – R4 = 109.4 – 109 ≈ 0 The transfer function including these errors is iO ACTUAL = (4mA + σO) + K (1 + σS)(eIN + σI) (e1 + e2)/2 – 5V ∆VCC e1 = (2mA X 2.5kΩ) + (1mA X 109Ω) = 5.109V e2 = (2mA X 2.5kΩ) + (1mA X 109.4Ω) = 5.1094V = (4mA + σO) + K eIN + KσI + KσS eIN (5) (e1 + e2)/2 – 5 = 0.1092V The error in the output current is iO ACTUAL – iO IDEAL and can be found by subtracting equations (5) and (3). CMRR = 31.6 X 103 for 90dB (6) σ1 = 30µV + (150nA X 0 + 20nA X 109Ω) This is a general error expression. The composition of each component of error depends on the circuitry inside the XTR101 and the particular circuit in which it is applied. The circuit of Figure 9 will be used to illustrate the principles. 3. σI = VOSI + (IB1 + R4 – IB2 RT) + + (e1 + e2)/2 – 5V ∆VCC (7) (8) (9) σS = εNONLIN + εSPAN = 0.0001 + 0 (assumes trim of RS) IO error = σO + K σI + K σS eIN PSRR K = 0.016 + CMRR PSRR* CMRR* εNONLIN* εSPAN* = = = = 40 RS = 0.016 + 40 123.3Ω = 0.340 eIN = e2 – V4 = IREF1 RT 25°C – IREF2 R4 since RT 25°C = R4, eIN = (IREF1 – IREF2) R4 = 0.4µA X 109Ω = 43.6µV input offset voltage input bias current input offset current output offset current error RT – R4 = mismatch in resistor change supply voltage between pins 7 and 8 away from 24V nominal power supply rejection ratio common-mode rejection ratio span nonlinearity span equation error. Untrimmed error = 5% max. May be trimmed to zero. Since the maximum mismatch of the current references is 0.04% of 1mA = 0.4µA, Ω = = = = = = (10) = 30µV + 2.18µV + 6.7µV + 3.46µV = 42.34µV The term in parentheses may be written in terms of offset current and resistor mismatches as IB1 ∆R + IOS' R4. VOSI* IB1*, IB2* IOSI* IOS RTO* ∆R ∆VCC 2120mV 0.1092V + 3.16 X 105 3.16 X 103 Ω 1. σO = IOS RTO 2. σS = εNONLINEARITY + εSPAN + Ω iO ERROR = σO + Kσ1 + KσS eIN PSRR= 3.16 X 105 for 110dB IO error = 6µA + (0.34 X 42.34µV) + (0.34 X 0.0001 X 43.6µV) = 6µA + 14.40µA + 0.0015µA = 20.40µA % error = 20.40µA 16mA X 100% 0.13% of span at lower range value. Items marked with an asterisk (*) can be found in the Electrical Specifications. B. AT THE UPPER RANGE VALUE (T = +150°C). EXAMPLE 3 The circuit in Figure 9 with the XTR101BG specifications and the following conditions: RT = 109.4Ω at 25°C, RT = 156.4Ω at 150°C, IO = 4mA at 25°C, IO = 20mA at 150°C, RS = 123.3Ω, R4 = 109Ω, RL = 250Ω, RLINE = 100Ω, VDI = 0.6V, VPS = 24V ±0.5%. Determine the % error at the upper and lower range values. ∆R = RT 150°C – R4 = 156.4 – 109.4 = 47Ω ∆VCC = (24 X 0.005) + 20mA (250Ω + 100Ω) + 0.6V = 7720mV e1 = 5.109V e2 = (2mA X 2.5kΩ) + (1mA X 156.4Ω) = 5.156V (e1 + e2)/2 – 5V = 0.1325V ® XTR101 14 σO = 6µA Upper Range: From equation (11), the predominant errors are IOS RTO (6µA), VOS RTI (30µV), and IB (150nA), max, B grade. Both IOS and VOS can be trimmed to zero; however, the result is an error of 0.09% of span instead of 0.19% span. σ1 = 30µV + (150nA X 47Ω + 20nA X 190Ω) + 7720mV 3.16 X 105 + 0.1325V 3.16 X 103 RECOMMENDED HANDLING PROCEDURES FOR INTEGRATED CIRCUITS All semiconductor devices are vulnerable, in varying degrees, to damage from the discharge of electrostatic energy. Such damage can cause performance degradation or failure, either immediate or latent. As a general practice, we recommend the following handling procedures to reduce the risk of electrostatic damage. = 30µV + 9.23µV + 24µV + 4.19µV = 67.42µV σS = 0.0001 eIN = e'2 – V4 = IREF1 RT 150°C – IREF2 R4 = (1mA X 156.4Ω) – (1mA X 109Ω) = 47mV IO error = σO + K σI + K σS eIN = 6µA + (0.34 X 67.42µV) + (0.34 X 0.0001 X 47000µV) = 6µA + 22.92µA + 1.60µA = 30.52µA Ω Ω % error = 1. Remove the static-generating materials, such as untreated plastic, from all areas that handle microcircuits. 30.52µA X 100% 16mA 2. Ground all operators, equipment, and work stations. 3. Transport and ship microcircuits, or products incorporat ing microcircuits, in static-free, shielded containers. = 0.19% of span at upper range value. 4. Connect together all leads of each device by means of a conductive material, when the device is not connected into a circuit. CONCLUSIONS Lower Range: From equation (10) it is observed that the predominant error term is the input offset voltage (30µV for the B grade). This is of little consequence in many applications. VOS RTI can, however, be nulled using the pot shown in Figures 5 and 6. The result is an error of 0.06% of span instead of 0.13% if span. 5. Control relative humidity to as high a value as practical (50% recommended). ® 15 XTR101