Wideband, Ring Demodulator CORPORATION SD8901 DESCRIPTION FEATURES • High Frequency Operation • Wide Dynamic Range • Low Capacitance The SD8901 is a ring demodulator/balanced mixer. Designed to utilize Calogic’s ultra high speed and low capacitance lateral DMOS process. The SD8901 offers significant performance improvements over JFET and diode balanced mixers when low third order harmonic distortion has been a problem. APPLICATIONS • Communications • RF Mixers PACKAGE INFORMATION Part Package Temperature Range SD8901HD Hermetic TO-78 SD8901CY Plastic Surface Mount XSD8901 Sorted Chips in Carriers PIN CONFIGURATIONS -55oC to 125oC -55oC to 125oC -55oC to 125oC Functional block diagram SO-14 TO-78 C LO1 IF2 RF2 5 7 3 IF 2 LO1 LO 2 IF1 RF2 RF 1 TOP VIEW LO1 RF 2 SUB SUB LO2 RF 1 SUB SUB IF2 SUB NC CD4 IF 1 SUB NC 1 2 3 4 5 6 7 IF 1 RF1 RF2 CASE LO 1 LO 2 IF 2 4 5 3 2 6 7 1 BOTTOM VIEW 6 2 1 LO2 RF1 IF1 4 SUBSTRATE SD8901 CORPORATION ABSOLUTE MAXIMUM RATINGS (TA = +25oC unless otherwise noted) ID Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Operating Temperature . . . . . . . . . . . . . . . . . . . . -55 to 125oC Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65 to 150oC Power Dissipation (A Package)* . . . . . . . . . . . . . . . . 640 mW * Derate 5 mW/ oC above 25oC Drain to Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Drain to Substrate . . . . . . . . . . . . . . . . . . . . . . . . 22.5 V Source to Substrate . . . . . . . . . . . . . . . . . . . . . . . 22.5 V Gate to Source. . . . . . . . . . . . . . . . . . . . -22.5 V to 30 V Gate to Substrate. . . . . . . . . . . . . . . . . . . . -0.3V to 30 V Gate to Drain . . . . . . . . . . . . . . . . . . . . . . -22.5V to 30 V VDS VDB VSB VGS VGB VGD ELECTRICAL CHARACTERISTCIS (TA = +25oC unless otherwise noted) SYMBOL CHARACTERISTICS MIN TYP 25 MAX UNIT TEST CONDITIONS STATIC V(BR)DS Drain-Source Breakdown Voltage 15 V(BR)SD Source-Drain Breakdown Voltage 15 V(BR)DB Drain-Substrate Breakdown Voltage 22.5 V(BR)SB Source-Substrate Breakdown Voltage 22.5 VT Threshold Voltage 0.1 rDS(ON) VGS = VSB = -5 V Is = 10 nA VGD = VDB = - 5 V ID = 10 nA Source Open VGB = 0 V, ID = 10 nA V Drain Open VGB = 0 V, ID = 10 nA 1 2.0 50 75 VDS = VGS = VT IS = 1 µA, VSB = 0V VGS = 5 V VGS = 10 V 30 Drain-Source "ON" Resistance ID = 1 mA VSB = 0 V Ω 23 VGS = 20 V 19 ∆rDS(ON) Resistance Matching VGS = 15 V 3 7 VGS = 5 V DYNAMIC Cgg LO1 - LO2 Capacitance 4.4 Lc Conversion Loss IMD3 Third Order Intercept +35 fMAX Maximum Operation Frequency 250 8 pF VDS = 0 V, VBS = -5.5 V VGS = 4 V dB See Figure 1, PLO = +17 dBm MHz Note: Guaranteed by design, not subject to production test PERFORMANCE COMPARISON SD8901 40 U350 3rd ORDER INPUT INTERCEPT POINT (+dBM) 30 20 DIODE RING 10 0 0 5 10 15 20 25 POWER LOCAL OSC. (+dBm) 30 35 SD8901 CORPORATION FIGURE 1. SD8901 +V GG u SIGNAL u T4-1 T1-1T OR T4-1 LO u u LOW-PASS IMAGE TERMINATING FILTER (OPTIONAL) 680 pF -Vu T4-1 680 pF i-f FIGURE 2. First and third Quadrand I-E Characteristic Showing Effect of Gate Voltage Leading to Large-Signal Overload Distortion. ID (ma) 16 V 12 V 50.00 8V 10.00 /DIV 4V 0V 0 -50.00 -5.000 VDS 0 1.000/DIV (V) 5.000