MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 D D D D D -- Active Mode: 220 µA at 1 MHz, 2.2 V -- Standby Mode: 0.5 µA -- Off Mode (RAM Retention): 0.1 µA Five Power-Saving Modes Ultrafast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.5 ns Instruction Cycle Time Basic Clock Module Configurations: -- Internal Frequencies up to 16 MHz With One Calibrated Frequency -- Internal Very Low Power LF Oscillator -- 32-kHz Crystal -- External Digital Clock Source 16-Bit Timer_A With Two Capture/Compare Registers D Brownout Detector D On-Chip Comparator for Analog Signal D D D D D Compare Function or Slope A/D (See Table 1) Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse On-Chip Emulation Logic With Spy-Bi-Wire Interface Family Members details see Table 1 Available in a 14-Pin Plastic Small-Outline Thin Package (TSSOP), 14-Pin Plastic Dual Inline Package (PDIP), and 16-Pin QFN For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide description The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs. The MSP430G2x01/11 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and ten I/O pins. The MSP430G2x11 family members have a versatile analog comparator. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2010 Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PRODUCT PREVIEW D Low Supply Voltage Range 1.8 V to 3.6 V D Ultralow Power Consumption MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Table 1. Available Options -- MSP430G2xxx Devices BSL EEM Flash (KB) RAM (B) Timer_A COMP_A+ Channel CLOCK I/O Package Type MSP430G2211IRSA16 MSP430G2211IPW14 MSP430G2211IN14 -- 1 2 128 1x TA2 8 LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2201IRSA16 MSP430G2201IPW14 MSP430G2201IN14 -- 1 2 128 1x TA2 -- LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2111IRSA16 MSP430G2111IPW14 MSP430G2111IN14 -- 1 1 128 1x TA2 8 LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2101IRSA16 MSP430G2101IPW14 MSP430G2101IN14 -- 1 1 128 1x TA2 -- LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP MSP430G2001IRSA16 MSP430G2001IPW14 MSP430G2001IN14 -- 1 0.5 128 1x TA2 -- LF, DCO, VLO 10 16-QFN 14-TSSOP 14-PDIP Device † PRODUCT PREVIEW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 device pinout, MSP430G2x01 DVCC 1 14 DVSS P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/ADC10CLK/CAOUT/CA3 P1.4/SMCLK/TCK P1.5/TA0.0/TMS 2 13 XIN/P2.6/TA0.1 3 N14 PW14 4 5 12 XOUT/P2.7 11 TEST/SBWTCK 10 RST/NMI/SBWTDIO 6 9 P1.7/TDO/TDI 7 8 P1.6/TA0.1/TDI/TCLK 3 P1.3 4 NC DVSS RSA XIN/P2.6/TA0.1 11 XOUT/P2.7 10 TEST/SBWTCK 9 RST/NMI/SBWTDIO 5 6 7 8 PRODUCT PREVIEW P1.2/TA0.1 12 P1.7/TDO/TDI 2 P1.6/TA0.1/TDI/TCLK P1.1/TA0.0 16 15 14 13 P1.5/TA0.0/TMS 1 P1.4/SMCLK/TCK P1.0/TA0CLK/ACLK NC DVCC NOTE: See port schematics section for detailed I/O information. NOTE: See port schematics section for detailed I/O information. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 device pinout, MSP430G2x11 DVCC 1 14 DVSS P1.0/TA0CLK/ACLKCA0 P1.1/TA0.0/CA1 P1.2/TA0.1/CA2 P1.3/CAOUT/CA3 P1.4/SMCLK/CA4/TCK P1.5/TA0.0/CA5/TMS 2 13 XIN/P2.6/TA0.1 3 N14 PW14 4 12 XOUT/P2.7 11 TEST/SBWTCK 10 RST/NMI/SBWTDIO 6 9 P1.7/CAOUT/CA7/TDO/TDI 7 8 P1.6/TA0.1/CA6/TDI/TCLK 5 NC DVSS NC 16 15 14 13 P1.0/TA0CLK/ACLK/CA0 1 12 P1.1/TA0.0/CA1 2 11 XOUT/P2.7 P1.2/TA0.1/CA2 3 10 TEST/SBWTCK P1.3/CAOUT/CA3 4 9 RST/NMI/SBWTDIO 7 8 P1.6/TA0.1/CA6/TDI/TCLK 6 P1.7/CAOUT/CA7/TDO/TDI 5 P1.5/TA0.0/CA5/TMS RSA P1.4/SMCLK/CA4/TCK PRODUCT PREVIEW DVCC NOTE: See port schematics section for detailed I/O information. XIN/P2.6/TA0.1 NOTE: See port schematics section for detailed I/O information. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 functional block diagram, MSP430G2x11 XIN XOUT DVCC DVSS P1.x P2.x 8 2 Port P1 Port P2 8 I/O Interrupt capability pull-up/down resistors 2 I/O Interrupt capability pull-up/down resistors ACLK SMCLK Flash 2KB 1KB MCLK 16MHz CPU MAB incl. 16 Registers MDB Emulation 2BP JTAG Interface RAM 128B Comp_A+ Brownout Protection 8 Channels Watchdog WDT+ 15-Bit Timer0_A2 PRODUCT PREVIEW Clock System 2 CC Registers Spy-Bi Wire RST/NMI POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 functional block diagram, MSP430G2x01 XIN XOUT DVCC P1.x DVSS P2.x 8 2 Port P1 Port P2 8 I/O Interrupt capability pull-up/down resistors 2 I/O Interrupt capability pull-up/down resistors ACLK Clock System MCLK SMCLK Flash RAM 2KB 1KB 0.5KB 16MHz CPU MAB incl. 16 Registers MDB PRODUCT PREVIEW Emulation 2BP JTAG Interface Brownout Protection 128B Watchdog WDT+ 15-Bit Timer0_A2 2 CC Registers Spy-Bi Wire RST/NMI 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Terminal Functions, MSP430G2x01 and MSP430G2x11 TERMINAL 14 N, PW 16 RSA NO. NO. DESCRIPTION I/O P1.0/ TA0CLK/ ACLK/ CA0 2 1 I/O General-purpose digital I/O pin Timer0_A, clock signal TACLK input ACLK signal ouput Comparator_A+, CA0 input (see Note 1) P1.1/ TA0.0/ CA1 3 2 I/O General-purpose digital I/O pin Timer0_A, capture: CCI0A input, compare: Out0 output Comparator_A+, CA1 input (see Note 1) P1.2/ TA0.1/ CA2 4 3 I/O General-purpose digital I/O pin Timer0_A, capture: CCI1A input, compare: Out1 output Comparator_A+, CA2 input (see Note 1) P1.3/ CA3/ CAOUT 5 4 I/O General-purpose digital I/O pin Comparator_A+, CA3 input (see Note 1) Comparator_A+, output (see Note 1) I/O General-purpose digital I/O pin SMCLK signal output Comparator_A+, CA4 input (see Note 1) JTAG test clock, input terminal for device programming and test I/O General-purpose digital I/O pin Timer0_A, compare: Out0 output Comparator_A+, CA5 input (see Note 1) JTAG test mode select, input terminal for device programming and test P1.4/ SMCLK/ CA4/ TCK P1.5/ TA0.0/ CA5/ TMS P1.6/ TA0.1/ CA6/ TDI/ TCLK P1.7/ CA7/ CAOUT TDO/ TDI 6 7 8 9 5 6 7 8 I/O I/O PRODUCT PREVIEW NAME General-purpose digital I/O pin Timer0_A, compare: Out1 output Comparator_A+, CA6 input (see Note 1) JTAG test data input or test clock input during programming and test General-purpose digital I/O pin CA7 input (see Note 1) Comparator_A+, output (see Note 1) JTAG test data output terminal or test data input during programming and test NOTES: 1. MSP430G2x11 only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Terminal Functions, MSP430G2x01 and MSP430G2x11 (continued) TERMINAL PRODUCT PREVIEW NAME 14 N, PW 16 RSA DESCRIPTION I/O NO. NO. XIN/ P2.6/ TA0.1 13 12 I/O Input terminal of crystal oscillator General-purpose digital I/O pin Timer0_A, compare: Out1 output XOUT/ P2.7 12 11 I/O Output terminal of crystal oscillator (see Note 1) General-purpose digital I/O pin RST/ NMI/ SBWTDIO 10 9 I Reset Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/ SBWTCK 11 10 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test DVCC 1 16 NA Supply voltage DVSS 14 14 NA Ground reference NC -- 15 13 NA Not connected. QFN Pad -- Pad NA QFN package pad connection to VSS recommended. NOTES: 1. If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. † TDO or TDI is selected via JTAG instruction. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 short-form description CPU Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 2 shows examples of the three types of instruction formats; Table 3 shows the address modes. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 PRODUCT PREVIEW The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Table 2. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5 Single operands, destination only e.g., CALL PC ---->(TOS), R8----> PC Relative jump, un/conditional e.g., JNE R8 Jump-on-equal bit = 0 Table 3. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE Register F F MOV Rs,Rd MOV R10,R11 Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) Symbolic (PC relative) F F MOV EDE,TONI Absolute F F MOV &MEM,&TCDAT OPERATION R10 ----> R11 M(2+R5)----> M(6+R6) M(EDE) ----> M(TONI) M(MEM) ----> M(TCDAT) Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) ----> M(Tab+R6) Indirect autoincrement F MOV @Rn+,Rm MOV @R10+,R11 M(R10) ----> R11 R10 + 2----> R10 F MOV #X,TONI MOV #45,TONI Immediate NOTE: S = source #45 ----> M(TONI) D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 operating modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode (AM) -- All clocks are active D Low-power mode 0 (LPM0) -- CPU is disabled -- ACLK and SMCLK remain active. MCLK is disabled PRODUCT PREVIEW D Low-power mode 1 (LPM1) -- CPU is disabled -- ACLK and SMCLK remain active. MCLK is disabled -- DCO’s dc-generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2) -- CPU is disabled -- MCLK and SMCLK are disabled -- DCO’s dc-generator remains enabled -- ACLK remains active D Low-power mode 3 (LPM3) -- CPU is disabled -- MCLK and SMCLK are disabled -- DCO’s dc-generator is disabled -- ACLK remains active D Low-power mode 4 (LPM4) 10 -- CPU is disabled -- ACLK is disabled -- MCLK and SMCLK are disabled -- DCO’s dc-generator is disabled -- Crystal oscillator is stopped POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Timer+ Flash key violation PC out-of-range (see Note 1) PORIFG RSTIFG WDTIFG KEYV (see Note 2) Reset 0FFFEh 31, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (see Notes 2 and 5) (non)-maskable, (non)-maskable, (non)-maskable 0FFFCh 30 0FFFAh 29 0FFF8h 28 COMP_A+ CAIFG (see Note 3 and 4) maskable 0FFF6h 27 Watchdog Timer+ WDTIFG maskable 0FFF4h 26 Timer_A2 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25 Timer_A2 TACCR1 CCIFG. TAIFG (see Notes 2 and 3) maskable 0FFF0h 24 0FFEEh 23 0FFECh 22 0FFEAh 21 0FFE8h 20 I/O Port P2 (two flags) P2IFG.6 to P2IFG.7 (see Notes 2 and 3) maskable 0FFE6h 19 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 2 and 3) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 0FFDEh ... 0FFC0h 15 ... 0, lowest (see Note 6) PRODUCT PREVIEW If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will go into LPM4 immediately after power-up. NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges. 2. Multiple source flags 3. Interrupt flags are located in the module 4. Devices with COMP_A+ only. 5. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. 6. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 Address 7 6 0h 5 4 ACCVIE NMIIE rw-0 WDTIE: OFIE: NMIIE: ACCVIE: PRODUCT PREVIEW Address 3 2 1 OFIE rw-0 0 WDTIE rw-0 rw-0 Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 6 5 4 3 2 1 0 01h interrupt flag register 1 and 2 Address 7 02h 4 3 2 1 NMIIFG RSTIFG PORIFG OFIFG rw-0 WDTIFG: OFIFG: RSTIFG: PORIFG: NMIIFG: Address rw-(0) 7 6 5 4 3 rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device 12 rw-(0) Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up Power-On Reset interrupt flag. Set on VCC power-up. Set via RST/NMI-pin 03h Legend rw-1 rw-(1) 0 WDTIFG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 1 0 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 memory organization MSP430G2001 MSP430G2011 MSP430G2101 MSP430G2111 MSP430G2201 MSP430G2211 Memory Main: interrupt vector Main: code memory Size Flash Flash 512B 0xFFFF to 0xFFC0 0xFFFF to 0xFE00 1kB 0xFFFF to 0xFFC0 0xFFFF to 0xFC00 2kB 0xFFFF to 0xFFC0 0xFFFF to 0xF800 Information memory Size Flash 256 Byte 010FFh -- 01000h 256 Byte 010FFh -- 01000h 256 Byte 010FFh -- 01000h Size 128B 027Fh -- 0200h 128B 027Fh -- 0200h 128B 027Fh -- 0200h 16-bit 8-bit 8-bit SFR 01FFh -- 0100h 0FFh -- 010h 0Fh -- 00h 01FFh -- 0100h 0FFh -- 010h 0Fh -- 00h 01FFh -- 0100h 0FFh -- 010h 0Fh -- 00h RAM Peripherals The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. D Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PRODUCT PREVIEW flash memory MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide. oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. PRODUCT PREVIEW DCO CALIBRATION DATA (PROVIDED FROM FACTORY IN FLASH INFO MEMORY SEGMENT A) DCO FREQUENCY CALIBRATION REGISTER SIZE 1 MHz CALBC1_1MHZ byte 010FFh CALDCO_1MHZ byte 010FEh ADDRESS brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 digital I/O There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2: D D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt condition is possible. Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2. Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pull-up/pull-down resistor. WDT+ watchdog timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A2 SIGNAL CONNECTIONS -- DEVICES WITH NO ANALOG INPUT PIN NUMBER PW, N RSA 2 - P1.0 1 - P1.0 DEVICE INPUT SIGNAL TACLK MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER PW, N RSA TACLK ACLK ACLK SMCLK SMCLK Timer NA 2 - P1.0 1 - P1.0 TACLK INCLK 3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1 ACLK (internal) CCI0B 7 - P1.5 6 - P1.5 VSS GND 4 - P1.2 3 - P1.2 4 - P1.2 3 - P1.2 VCC VCC TA1 CCI1A TA1 CCI1B VSS GND VCC VCC POST OFFICE BOX 655303 CCR0 CCR1 • DALLAS, TEXAS 75265 TA0 TA1 8 - P1.6 7 - P1.6 13 - P2.6 12 - P2.6 15 PRODUCT PREVIEW Timer_A2 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 TIMER_A2 SIGNAL CONNECTIONS -- DEVICES WITH COMP_A+ INPUT PIN NUMBER PW, N RSA 2 - P1.0 1 - P1.0 TACLK MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER PW, N RSA TACLK ACLK ACLK SMCLK SMCLK Timer NA 2 - P1.0 1 - P1.0 TACLK INCLK 3 - P1.1 2 - P1.1 TA0 CCI0A 3 - P1.1 2 - P1.1 ACLK (internal) CCI0B 7 - P1.5 6 - P1.5 VSS GND 4 - P1.2 3 - P1.2 4 - P1.2 PRODUCT PREVIEW MODULE INPUT NAME DEVICE INPUT SIGNAL 3 - P1.2 VCC VCC TA1 CCI1A CAOUT (internal) CCI1B VSS GND VCC VCC CCR0 CCR1 TA0 TA1 8 - P1.6 7 - P1.6 13 - P2.6 12 - P2.6 comparator_A+ (MSP430G2x11 only) The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 peripheral file map PERIPHERALS WITH WORD ACCESS Timer_A Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector TACCR1 TACCR0 TAR TACCTL1 TACCTL0 TACTL TAIV 0174h 0172h 0170h 0164h 0162h 0160h 012Eh Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog Timer+ Watchdog/timer control WDTCTL 0120h Comparator_A+ (MSP430G2x11 only) Comparator_A+ port disable Comparator_A+ control 2 Comparator_A+ control 1 CAPD CACTL2 CACTL1 05Bh 05Ah 059h Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL 053h 058h 057h 056h Port P2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 027h 026h 025h 024h 023h 022h 021h 020h Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 IFG2 IFG1 IE2 IE1 003h 002h 001h 000h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRODUCT PREVIEW PERIPHERALS WITH BYTE ACCESS 17 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 absolute maximum ratings† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 85°C NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. 3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. recommended operating conditions NOM MAX UNIT Supply voltage during program execution, VCC 1.8 3.6 V Supply voltage during program/erase flash memory, VCC 2.2 3.6 V Supply voltage, VSS 0 Operating free-air temperature range, TA I version Processor frequency fSYSTEM (Maximum MCLK frequency) V --40 85 VCC = 1.8 V, Duty Cycle = 50% ±10% dc 4.15 VCC = 2.7 V, Duty Cycle = 50% ±10% dc 12 VCC ≥ 3.3 V, Duty Cycle = 50% ±10% dc 16 °C MHz NOTES: 1. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet. Legend: 16 MHz System Frequency --MHz PRODUCT PREVIEW MIN Supply voltage range, during flash memory programming 12 MHz Supply voltage range, during program execution 7.5 MHz 4.15 MHz 1.8 V 2.2 V 2.7 V 3.3 V 3.6 V Supply Voltage --V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Save Operating Area 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) active mode supply current (into VCC) excluding external current (see Notes 1 and 2) PARAMETER IAM, 1MHz TEST CONDITIONS Active mode (AM) current (1MHz) TA VCC fDCO = fMCLK = fSMCLK = 1MHz, fACLK = 32,768Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, CALBC1 1MHZ DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 MIN 2.2 V TYP MAX UNIT 220 µA 3V 300 370 NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9pF. typical characteristics -- active mode supply current (into VCC) Active Mode Current -- mA Active Mode Current -- mA fDCO = 16 MHz 4.0 3.0 fDCO = 12 MHz 2.0 1.0 fDCO = 8 MHz 2.0 2.5 3.0 3.5 TA = 85 °C 3.0 TA = 25 °C 2.0 VCC = 3 V TA = 85 °C TA = 25 °C 1.0 fDCO = 1 MHz 0.0 1.5 PRODUCT PREVIEW 4.0 5.0 VCC = 2.2 V 4.0 0.0 0.0 VCC -- Supply Voltage -- V Figure 2. Active mode current vs VCC, TA = 25°C POST OFFICE BOX 655303 4.0 8.0 12.0 16.0 fDCO -- DCO Frequency -- MHz Figure 3. Active mode current vs DCO frequency • DALLAS, TEXAS 75265 19 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) low-power mode supply currents (into VCC) excluding external current (see Notes 1 and 2) PARAMETER TA VCC Low-power mode 0 (LPM0) current, see Note 3 fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32,768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25°C 2.2 V 65 µA ILPM2 Low-power mode 2 (LPM2) current, see Note 4 fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32,768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 22 µA ILPM3,LFXT1 Low-power mode 3 (LPM3) current, see Note 4 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32,768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 0.7 1.5 µA ILPM3,VLO Low-power mode 3 current, (LPM3) see Note 4 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25°C 2.2 V 0.5 0.7 µA fDCO = fMCLK = fSMCLK = 0MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 25°C 2.2 V 0.1 0.5 µA ILPM4 Low-power mode 4 (LPM4) current, current see Note 5 85°C 2.2 V 0.8 1.5 µA PRODUCT PREVIEW ILPM0, 1MHz NOTES: 1. 2. 3. 4. 5. 20 TEST CONDITIONS MIN TYP All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- LPM3 current ILPM4 -- Low--power mode current -- uA 10.0 9.0 8.0 7.0 6.0 5.0 Vcc = 3.6 V 4.0 Vcc = 3 V 3.0 Vcc = 2.2V 2.0 PRODUCT PREVIEW 1.0 Vcc = 1.8 V 0.0 --40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 TA -- Temperature -- °C typical characteristics -- LPM4 current ILPM4 -- Low--power mode current -- uA 10.0 9.0 8.0 7.0 6.0 5.0 Vcc = 3.6 V 4.0 Vcc = 3 V 3.0 Vcc = 2.2V 2.0 1.0 0.0 --40.0 --20.0 0.0 Vcc = 1.8 V 20.0 40.0 60.0 80.0 100.0 120.0 TA -- Temperature -- °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs -- Ports Px PARAMETER VIT+ TEST CONDITIONS VCC Positive going input threshold Positive-going voltage MIN MAX UNIT 0.45 0.75 VCC 1.35 2.25 V 0.25 0.55 VCC 3V 0.75 1.65 V 3V 0.3 1.0 V 3V 20 50 kΩ 3V VIT-- Negative going input threshold Negative-going voltage Vhys Input voltage hysteresis (VIT+ -VIT-- ) RPull Pull-up/pull-down resistor For pullup: VIN = VSS; For pulldown: VIN = VCC CI Input Capacitance VIN = VSS or VCC TYP 35 5 pF NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals shorter than t(int). PRODUCT PREVIEW leakage current -- Ports Px PARAMETER Ilkg(Px.x) TEST CONDITIONS High-impedance leakage current VCC see Notes 1 and 2 MIN TYP 3V MAX UNIT ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is disabled. outputs -- Ports Px TEST CONDITIONS VCC VOH PARAMETER High-level output voltage I(OHmax) = --6 mA (see Notes 2) 3V MIN VCC --0.3 TYP MAX UNIT V VOL Low-level output voltage I(OLmax) = 6 mA (see Notes 2) 3V VSS+0.3 V NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. output frequency -- Ports Px PARAMETER TEST CONDITIONS VCC fPx.y Port output frequency (with load) Px.y, CL = 20 pF, RL = 1 kOhm (see Note 1 and 2) MIN TYP MAX UNIT 3V 12 MHz fPort_CLK Clock output frequency Px.y, CL = 20 pF (see Note 2) 3V 16 MHz NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider. 2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- outputs TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 25.0 TA = 25°C TA = 85°C 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P1.7 40.0 TA = 85°C 30.0 20.0 10.0 0.0 0.0 2.5 0.5 VOL -- Low-Level Output Voltage -- V 1.5 2.0 2.5 3.0 3.5 Figure 5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 0.0 VCC = 2.2 V P1.7 I OH -- Typical High-Level Output Current -- mA I OH -- Typical High-Level Output Current -- mA 1.0 VOL -- Low-Level Output Voltage -- V Figure 4 --5.0 --10.0 --15.0 TA = 85°C --20.0 --25.0 0.0 TA = 25°C TA = 25°C 0.5 1.0 1.5 2.0 2.5 VOH -- High-Level Output Voltage -- V VCC = 3 V P1.7 --10.0 --20.0 --30.0 TA = 85°C --40.0 TA = 25°C --50.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH -- High-Level Output Voltage -- V Figure 6 Figure 7 NOTE: One output loaded at a time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 PRODUCT PREVIEW VCC = 2.2 V P1.7 I OL -- Typical Low-Level Output Current -- mA I OL -- Typical Low-Level Output Current -- mA 30.0 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) (see Figure 8) dVCC/dt ≤ 3 V/s 0.7 × V(B_IT--) V(B_IT--) (see Figure 8 through Figure 10) dVCC/dt ≤ 3 V/s 1.35 V Vhys(B_IT--) (see Figure 8) dVCC/dt ≤ 3 V/s 140 mV td(BOR) (see Figure 8) t(reset) Pulse length needed at RST/NMI pin to accepted reset internally 2000 2.2 V/3 V 2 V µs µs NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT--) + Vhys(B_IT--) is ≤ 1.8V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC PRODUCT PREVIEW Vhys(B_IT--) V(B_IT--) VCC(start) 1 0 t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- POR/brownout reset (BOR) VCC 3V VCC(drop) -- V 2 VCC = 3 V Typical Conditions 1.5 t pw 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns tpw -- Pulse Width -- µs 1 ns tpw -- Pulse Width -- µs Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 3V VCC(drop) -- V VCC = 3 V 1.5 t pw PRODUCT PREVIEW 2 Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 1000 tf tr tpw -- Pulse Width -- µs tpw -- Pulse Width -- µs Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. D DCO control bits DCOx have a step size as defined by parameter SDCO. D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: f average = 32 × f DCO(RSEL,DCO) × f DCO(RSEL,DCO+1) MOD × f DCO(RSEL,DCO)+(32−MOD) × f DCO(RSEL,DCO+1) DCO frequency PRODUCT PREVIEW PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT RSELx < 14 1.8 3.6 V RSELx = 14 2.2 3.6 V Vcc Supply voltage range fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3V fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3V 0.12 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3V 0.15 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3V 0.21 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3V 0.30 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3V 0.41 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3V 0.58 MHz fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3V 0.80 fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3V fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3V 1.60 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3V 2.30 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3V 3.40 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3V fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3V fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3V fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3V fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 15.25 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 21.00 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 3V 1.35 SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 3V 1.08 Measured at SMCLK output 3V 50 RSELx = 15 Duty Cycle 26 3.0 3.6 V 0.06 0.14 MHz 0.80 MHz 1.50 4.25 4.30 MHz 7.30 7.8 8.60 MHz MHz MHz 13.9 MHz ratio POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 % MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies -- tolerance PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1 MHz tolerance over temperature (see Note 1) BCSCTL1= CALBC1_1MHz DCOCTL = CALDCO_1MHz calibrated at 30°C and 3.0V 0°C to 85°C 3.0 V --3 ±0.5 +3 % 1 MHz tolerance over VCC BCSCTL1= CALBC1_1MHz DCOCTL = CALDCO_1MHz calibrated at 30°C and 3.0V 30°C 1.8 V to 3.6 V --3 ±2 +3 % 1 MHz tolerance overall BCSCTL1= CALBC1_1MHz DCOCTL = CALDCO_1MHz calibrated at 30°C and 3.0V --40°C to 85°C 1.8 V to 3.6 V --6 ±3 +6 % MIN TYP MAX NOTES: 1. This is the frequency change from the measured frequency at 30°C over temperature. wake-up from lower power modes (LPM3/4) tDCO,LPM3/4 tCPU,LPM3/4 CPU wake-up time from LPM3/4 (see Note 2) TEST CONDITIONS VCC BCSCTL1= CALBC1_1MHz DCOCTL = CALDCO_1MHz 3V 1.5 UNIT µs 1/fMCLK + tClock,LPM3/4 NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). 2. Parameter applicable only if DCOCLK is used for MCLK. typical characteristics -- DCO clock wake-up time from LPM3/4 DCO Wake Time -- us 10.00 RSELx = 0...11 1.00 0.10 0.10 RSELx = 12...15 1.00 10.00 DCO Frequency -- MHz Figure 11. DCO wake-up time from LPM3 vs DCO frequency POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 PRODUCT PREVIEW PARAMETER DCO clock wake-up time from LPM3/4 (see Note 1) MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, low frequency modes (see Note 4) PARAMETER VCC fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, LF mode XTS = 0, XCAPx = 0, LFXT1Sx = 3 1.8 V to 3.6 V Oscillation allowance for LF crystals OALF Integrated effective load capacitance LF mode capacitance, (see Note 1) CL,eff PRODUCT PREVIEW TEST CONDITIONS MIN TYP MAX 32768 10000 32768 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32,768 kHz, CL,eff = 6 pF 500 XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32,768 kHz, CL,eff = 12 pF 200 UNIT Hz 50,000 Hz kΩ XTS = 0, XCAPx = 0 1 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 Duty cycle LF mode XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32,768Hz fFault,LF Oscillator fault frequency, LF mode (see Note 3) XTS = 0, XCAPx = 0. LFXT1Sx = 3 (see Note 2) 2.2 V 30 2.2 V 10 50 pF 70 % 10000 Hz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Measured with logic level input frequency but also applies to operation with crystals. 3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. 4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. -- Keep the trace between the device and the crystal as short as possible. -- Design a good ground plane around the oscillator pins. -- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. -- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. ---- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. internal very low power, low frequency oscillator (VLO) TA VCC MIN TYP MAX fVLO PARAMETER VLO frequency -40 -- 85°C 3.0 V 4 12 20 dfVLO/dT VLO frequency temperature drift -40 -- 85°C 3.0 V dfVLO/dVCC VLO frequency supply voltage drift 25°C 1.8 V -- 3.6 V 28 TEST CONDITIONS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT kHz 0.5 %/°C 4 %/V MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Timer_A PARAMETER TEST CONDITIONS fTA Timer_A clock frequency Internal: SMCLK, ACLK; External: TACLK, INCLK; Duty Cycle = 50% ±10% tTA,cap Timer_A, capture timing TA0, TA1 VCC MIN TYP MAX fSYSTEM 3V UNIT MHz 20 ns Comparator_A+ (MSP430G2x11 only) TEST CONDITIONS VCC MIN TYP MAX UNIT CAON=1, CARSEL=0, CAREF=0 3V 45 µA I(Refladder/RefDiode) CAON=1, CARSEL=0, CAREF=1/2/3, no load at CA0 and CA1 3V 45 µA V(IC) CAON=1 3V PCA0=1, CARSEL=1, CAREF=1, no load at CA0 and CA1 3V 0.24 PCA0=1, CARSEL=1, CAREF=2, no load at CA0 and CA1 3V 0.48 V(Ref025) V(Ref050) Common-mode input voltage Voltage @ 0.25 V V Voltage @ 0.5V V CC CC CC node CC node 0 VCC --1 V V(RefVT) (see Figure 12 and Figure 13) PCA0=1, CARSEL=1, CAREF=3, no load at CA0 and CA1, TA = 85°C 3V 490 mV V(offset) Offset voltage See Note 2 3V ±10 mV Vhys Input hysteresis CAON=1 3V 0.7 mV TA = 25°C, Overdrive 10 mV, Without filter: CAF=0 3V 120 ns TA = 25°C, Overdrive 10 mV, With filter: CAF=1 3V 1.5 µs t(response) Response time (low--high and high--low) NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The two successive measurements are then summed together. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 PRODUCT PREVIEW PARAMETER I(DD) MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics -- Comparator_A+ 650 650 VCC = 2.2 V PRODUCT PREVIEW 600 V(REFVT) -- Reference Volts --mV V(REFVT) -- Reference Volts --mV VCC = 3 V Typical 550 500 450 400 --45 --25 --5 15 35 55 75 95 600 Typical 550 500 450 400 --45 115 --25 --5 15 Short Resistance -- kOhms 100.00 VCC = 1.8V VCC = 2.2V VCC = 3.0V VCC = 3.6V 1.00 0.0 0.2 0.4 0.6 0.8 VIN/VCC -- Normalized Input Voltage -- V/V 1.0 Figure 14. Short Resistance vs VIN/VCC 30 55 75 95 115 Figure 13. V(RefVT) vs Temperature, VCC = 2.2 V Figure 12. V(RefVT) vs Temperature, VCC = 3 V 10.00 35 TA -- Free-Air Temperature -- °C TA -- Free-Air Temperature -- °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) flash memory VCC(PGM/ ERASE) TEST CONDITIONS VCC Program and Erase supply voltage MIN TYP 2.2 fFTG Flash Timing Generator frequency IPGM Supply current from VCC during program 2.2 V/3.6 V 257 1 IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 tCPT Cumulative program time (see Note 1) 2.2 V/3.6 V tCMErase Cumulative mass erase time 2.2 V/3.6 V TJ = 25°C V 476 kHz 5 mA 7 mA 10 ms ms 105 tRetention Data retention duration tWord Word or byte program time 30 tBlock, 0 Block program time for 1st byte or word 25 tBlock, 1-63 Block program time for each additional byte or word tBlock, End Block program end-sequence wait time tMass Erase Mass erase time tSeg Erase Segment erase time cycles 100 years 18 see Note 2 UNIT 3.6 20 104 Program/Erase endurance MAX tFTG 6 10593 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). RAM PARAMETER V(RAMh) TEST CONDITIONS RAM retention supply voltage (see Note 1) CPU halted MIN 1.6 TYP MAX UNIT V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 PRODUCT PREVIEW PARAMETER MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) JTAG and Spy-Bi-Wire interface TEST CONDITIONS PARAMETER VCC MIN TYP MAX UNIT fSBW Spy-Bi-Wire input frequency 2.2 V / 3 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V / 3 V 0.025 15 us tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge, see Note 1) 2.2 V/ 3 V 1 us tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V/ 3 V 15 100 2.2 V 0 5 MHz 3V 0 10 MHz 2.2 V/ 3 V 25 90 kΩ fTCK TCK input frequency -- 4-wire 4 wire JTAG (see Note 2) RInternal Internal pull-down resistance on TEST 60 us PRODUCT PREVIEW NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. 2. fTCK may be restricted to meet the timing requirements of the module selected. JTAG fuse (see Note 1) TEST CONDITIONS PARAMETER VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TEST for fuse-blow IFB Supply current into TEST during fuse blow tFB Time to blow fuse TA = 25°C VCC MIN TYP MAX 2.5 6 UNIT V 7 V 100 mA 1 ms NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched to bypass mode. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 APPLICATION INFORMATION Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt trigger -- MSP430G2x10 PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y 0 From Timer 1 DVSS 0 DVCC 1 1 PRODUCT PREVIEW P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3 PxIN.y To Module PxIE.y PxIRQ.y Q EN Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y Port P1 (P1.0 to P1.3) pin functions -- MSP430G2x10 PIN NAME (P1.X) (P1 X) X 0 FUNCTION P1DIR.x P1SEL.x I: 0; O: 1 0 TA0CLK/ TA0.TACLK 0 1 ACLK ACLK 1 1 P1.0/ P1.1/ 1 TA0.0 P1.2/ 2 TA0.1 P1.3/ 3 P1.x (I/O) CONTROL BITS / SIGNALS P1.x (I/O) I: 0; O: 1 0 TA0.0 1 1 TA0.CCI0A 0 1 P1.x (I/O) I: 0; O: 1 0 TA0.1 1 1 TA0.CCI1A 0 1 I: 0; O: 1 0 P1.x (I/O) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt trigger -- MSP430G2x10 PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y PxOUT.y From Module DVSS 0 DVCC 1 1 0 1 P1.4/SMCLK/TCK P1.5/TA0.0/TMS P1.6/TA0.1/TDI/TCLK P1.7/TDO/TDI PRODUCT PREVIEW PxIN.y To Module PxIE.y PxIRQ.y EN Q Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y From JTAG To JTAG Port P1 (P1.4 to P1.7) pin functions -- MSP430G2x10 CONTROL BITS / SIGNALS PIN NAME (P1.X) P1.4/ X 4 5 6 I: 0; O: 1 0 0 0 1 1 0 0 P1.x (I/O) x x 1 0 I: 0; O: 1 0 0 0 1 1 0 0 P1.x (I/O) x x 1 0 I: 0; O: 1 0 0 0 1 1 0 0 TA0.1 TA0.1/ TDI/TCLK 34 CAPD.y TMS TMS TDO/TDI JTAG Mode TA0.0 TA0.0/ P1.7/ P1SEL.x TCK TCK P1.6/ P1.x (I/O) P1DIR.x SMCLK SMCLK/ P1.5/ FUNCTION 7 TDI/TCLK x x 1 0 P1.x (I/O) I: 0; O: 1 0 0 0 TDO/TDI x x 1 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt trigger -- MSP430G2x11 To Comparator from Comparator PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y ACLK 0 DVCC 1 1 0 1 Bus Keeper EN P1.0/TA0CLK/ACLK/CA0 P1.1/TA0.0/CA1 P1.2/TA0.1/CA2 P1.3/CAOUT/CA3 PRODUCT PREVIEW PxOUT.y DVSS PxIN.y To Module PxIE.y PxIRQ.y Q PxIFG.y PxSEL.y PxIES.y EN Set Interrupt Edge Select POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Port P1 (P1.0 to P1.3) pin functions -- MSP430G2x11 PIN NAME (P1.X) (P1 X) P1.0/ X 0 P1.x (I/O) P1DIR.x P1SEL.x CAPD.y I: 0; O: 1 0 0 0 TA0CLK/ TA0.TACLK 0 1 ACLK/ ACLK 1 1 0 CA0 CA0 x x 1 (y = 0) P1.1/ 1 TA0.0/ P1.2/ 2 TA0.1/ CA2 P1.3/ P1.x (I/O) I: 0; O: 1 0 0 TA0.0 1 1 0 TA0.CCI0A 0 1 0 CA1 CA1 PRODUCT PREVIEW CONTROL BITS / SIGNALS FUNCTION 3 x x 1 (y = 1) I: 0; O: 1 0 0 TA0.1 1 1 0 TA0.CCI1A 0 1 0 CA2 x x 1 (y = 2) I: 0; O: 1 0 0 P1.x (I/O) P1.x (I/O) CAOUT/ CAOUT 1 1 0 CA3 CA3 x x 1 (y = 3) 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt trigger -- MSP430G2x11 To Comparator from Comparator CAPD.y PxSEL.y PxDIR.y 1 Direction 0: Input 1: Output 0 PxREN.y PxSEL.y 0 DV CC 1 1 0 1 PRODUCT PREVIEW PxOUT.y From Module DVSS P1.4/SMCLK/CA4/TCK P1.5/TA0.0/CA5/TMS P1.6/TA0.1/CA6/TDI/TCLK P1.7/CAOUT/CA7/TDO/TDI PxIN.y To Module PxIE.y PxIRQ.y Q PxIFG.y PxSEL.y PxIES.y EN Set Interrupt Edge Select From JTAG To JTAG POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Port P1 (P1.4 to P1.7) pin functions -- MSP430G2x11 CONTROL BITS / SIGNALS PIN NAME (P1.X) X 4 P1SEL.x JTAG Mode CAPD.y 0 I: 0; O: 1 0 0 SMCLK 1 1 0 0 CA4/ CA4 x x 0 1 (y = 4) TCK TCK P1.5/ P1.x (I/O) P1DIR.x SMCLK/ P1.4/ 5 P1.x (I/O) x x 1 0 I: 0; O: 1 0 0 0 TA0.0/ TA0.0 1 1 0 0 CA5/ CA5 x x 0 1 (y = 5) TMS TMS x x 1 0 0 6 I: 0; O: 1 0 0 TA0.1/ TA0.1 1 1 0 0 CA6/ CA6 x x 0 1 (y = 6) P1.6/ TDI/TCLK P1.7/ PRODUCT PREVIEW FUNCTION 7 P1.x (I/O) TDI/TCLK x x 1 0 P1.x (I/O) I: 0; O: 1 0 0 0 CAOUT/ CAOUT 1 1 0 0 CA7/ CA7 x x 0 1 (y = 7) TDO/TDI TDO/TDI x x 1 0 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Port P2 pin schematic: P2.6, input/output with Schmitt trigger -- MSP430G2x10 and MSP430G2x11 XOUT/P2.7 LF off PxSEL.6 PxSEL.7 BCSCTL3.LFXT1Sx = 11 LFXT1CLK 0 1 PxSEL.6 1 Direction 0: Input 1: Output 0 PRODUCT PREVIEW PxDIR.y PxREN.y PxSEL.6 PxOUT.y 0 from Module 1 DV SS 0 DV CC 1 1 Bus Keeper EN XIN/P2.6/TA0.1 PxIN.y To Module PxIE.y PxIRQ.y Q EN Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y Port P2 (P2.6) pin functions -- MSP430G2x10 and MSP430G2x11 PIN NAME (P2.X) (P2 X) XIN X 6 CONTROL BITS / SIGNALS FUNCTION XIN P2.6 P2.x (I/O) TA0.1 Timer0_A3.TA1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P2DIR.x P2SEL.6 PSEL2.7 0 1 1 I: 0; O: 1 0 x 1 1 x 39 MSP430G2x01, MSP430G2x11 MIXED SIGNAL MICROCONTROLLER SLAS695B -- FEBRUARY 2010 -- REVISED MAY 2010 Port P2 pin schematic: P2.7, input/output with Schmitt trigger -- MSP430G2x10 and MSP430G2x11 XIN/P2.6/TA0.1 LF off PxSEL.6 PxSEL.7 BCSCTL3.LFXT1Sx = 11 LFXT1CLK 0 PxDIR.y 1 Direction 0: Input 1: Output 0 PRODUCT PREVIEW from P2.6/XIN 1 PxSEL.7 PxREN.y PxSEL.7 PxOUT.y 0 from Module 1 DVSS 0 DV CC 1 1 Bus Keeper EN XOUT/P2.7 PxIN.y To Module PxIE.y PxIRQ.y Q EN Set PxIFG.y Interrupt Edge Select PxSEL.y PxIES.y Port P2 (P2.7) pin functions -- MSP430G2x10 and MSP430G2x11 CONTROL BITS / SIGNALS PIN NAME (P2.X) XOUT P2.7 40 X 7 FUNCTION XOUT P2.x (I/O) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P2DIR.x P2SEL.6 P2SEL.7 P2SEL.7 1 1 1 I: 0; O: 1 0 x PACKAGE OPTION ADDENDUM www.ti.com 18-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MSP430G2001IN14 ACTIVE PDIP N 14 MSP430G2001IPW14R ACTIVE TSSOP PW 14 MSP430G2001IRSA16R ACTIVE QFN RSA MSP430G2001IRSA16T ACTIVE QFN MSP430G2101IN14 ACTIVE MSP430G2101IPW14 25 MSL Peak Temp (3) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2101IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2101IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2101IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2111IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2111IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2111IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2111IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2111IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2201IN14 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2201IPW14 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2201IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2201IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2201IRSA16T ACTIVE QFN RSA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2211IPW14R ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2211IRSA16R ACTIVE QFN RSA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2211IRSA16T ACTIVE QFN RSA 16 250 CU NIPDAU Level-2-260C-1 YEAR (1) Pb-Free (RoHS) Lead/Ball Finish Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-May-2010 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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