TI MSP430P112IDW

SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
D Low Supply Voltage Range 2.5 V to 5.5 V
D Ultralow-Power Consumption:
D
D
D
D
D Serial Onboard Programming
D Program Code Protection by Security Fuse
D Family Members Include:
− Active Mode: 330 µA at 1 MHz, 3 V
− Standby Mode: 1.5 µA
− Off Mode (RAM Retention): 0.1 µA
Wake-up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture, 200 ns Instruction
Cycle Time
Basic Clock Module Configurations:
− Various Internal Resistors
− Single External Resistor
− 32 kHz Crystal
− High Frequency Crystal
− Resonator
− External Clock Source
16-Bit Timer_A With Three
Capture/Compare Registers
D
D
D
MSP430C111: 2k Byte ROM, 128 Byte RAM
MSP430C112: 4k Byte ROM, 256 Byte RAM
MSP430P112: 4k Byte OTP, 256 Byte RAM
EPROM Version Available for Prototyping:
− PMS430E112: 4k Byte EPROM, 256 Byte
RAM
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin
Ceramic Dual-In-Line (CDIP) Package
(EPROM Only)
For Complete Module Descriptions, Refer
to the MSP430x1xx Family User’s Guide,
Literature Number SLAU049
DW PACKAGE
(TOP VIEW)
description
The Texas Instruments MSP430 family of ultralow
power microcontrollers consist of several devices
featuring different sets of peripherals targeted for
various applications. The architecture, combined
with five low power modes is optimized to achieve
extended battery life in portable measurement
applications. The device features a powerful
16-bit RISC CPU, 16-bit registers, and constant
generators that attribute to maximum code
efficiency. The digitally controlled oscillator (DCO)
allows wake-up from low-power modes to active
mode in less than 6µs.
1
2
3
4
5
6
7
8
9
10
TEST/VPP
VCC
P2.5/ROSC
VSS
XOUT/TCLK
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
20
19
18
17
16
15
14
13
12
11
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
The MSP430x11x series is an ultra low-power mixed signal microcontroller with a built in 16-bit timer and
fourteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998 − 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " " !"
&& )*' &! #"+ &" ""%* %!&"
"+ %% #""'
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SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
CDIP
20-Pin
(JL)
SOWB
20-Pin
(DW)
−40°C to 85°C
MSP430C111IDW
MSP430C112IDW
MSP430P112IDW
25°C
—
PMS430E112JL
functional block diagram
XIN
XOUT/TCLK
VCC
VSS
P1
RST/NMI
JTAG
ROSC
Oscillator
System
Clock
ACLK
SMCLK
2/4KB
ROM
256B RAM
P2
8
I/O Port 1
8 I/Os, with
Interrupt
Capability
128B RAM
4KB OTP
6
I/O Port 2
6 I/Os, with
Interrupt
Capability
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
TEST/VPP
Watchdog
Timer
Timer_A3
POR
3 CC Reg
15/16-Bit
2
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Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P1.0/TACLK
13
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
14
I/O
General-purpose digital I/O pin/Timer_A, Capture: CCI0A input, Compare: Out0 output
P1.2/TA1
15
I/O
General-purpose digital I/O pin/Timer_A, Capture: CCI1A input, Compare: Out1 output
P1.3/TA2
16
I/O
General-purpose digital I/O pin/Timer_A, Capture: CCI2A input, Compare: Out2 output
P1.4/SMCLK/TCK
17
I/O
General-purpose digital I/O pin/SMCLK signal output/Test clock, input terminal for device programming
and test
P1.5/TA0/TMS
18
I/O
General-purpose digital I/O pin/Timer_A, Compare: Out0 output/test mode select, input terminal for
device programming and test.
P1.6/TA1/TDI
19
I/O
General-purpose digital I/O pin/Timer_A, Compare: Out1 output/test data input terminal.
P1.7/TA2/TDO/TDI
20
I/O
General-purpose digital I/O pin/Timer_A, Compare: Out2 output/test data output terminal or data input
during programming.
P2.0/ACLK
8
I/O
General-purpose digital I/O pin/ACLK output
P2.1/INCLK
9
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/TA0
10
I/O
General-purpose digital I/O pin/Timer_A, Capture: CCI0B input, Compare: Out0 output
P2.3/TA1
11
I/O
General-purpose digital I/O pin/Timer_A, Capture: CCI1B input, Compare: Out1 output
P2.4/TA2
12
I/O
General-purpose digital I/O pin/Timer_A, Compare: Out2 output
P2.5/ROSC
RST/NMI
3
I/O
General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency
7
I
Reset or nonmaskable interrupt input
TEST/VPP
1
I
Selects test mode for JTAG pins on Port1/programming voltage input during EPROM programming
VCC
VSS
2
XIN
6
I
XOUT/TCLK
5
I/O
Supply voltage
4
Ground reference
Input terminal of crystal oscillator
Output terminal of crystal oscillator or test clock input
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Indirect
D
D
D
D
D
Indirect
autoincrement
Register
Indexed
Symbolic (PC relative)
Absolute
Immediate
NOTE: S = source
4
S D
D
D
D
D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
MOV EDE,TONI
M(EDE) −−> M(TONI)
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
D
MOV #X,TONI
MOV #45,TONI
D = destination
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#45
−−> M(TONI)
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE
Power-up, external reset, watchdog
NMI, oscillator fault
Watchdog Timer
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
WDTIFG (see Note1)
Reset
0FFFEh
15, highest
NMIIFG, OFIFG (see Note 1)
(non)-maskable,
(non)-maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
0FFF6h
11
WDTIFG
maskable
0FFF4h
10
Timer_A3
TACCR0 CCIFG (see Note 2)
maskable
0FFF2h
9
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 and 2)
maskable
0FFF0h
8
0FFEEh
7
0FFECh
6
0FFEAh
5
0FFE8h
4
I/O Port P2 (eight flags − see Note 3)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
maskable
0FFE6h
3
I/O Port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
maskable
0FFE4h
2
0FFE2h
1
0FFE0h
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x devices.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1
Address
7
6
5
0h
4
3
2
OFIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
1
rw-0
0
WDTIE
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
interrupt flag register 1
Address
7
02h
6
5
4
3
NMIIFG
rw-0
WDTIFG:
OFIFG:
NMIIFG:
Legend
2
1
OFIFG
rw-1
0
WDTIFG
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
Set via RST/NMI-pin
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC
Bit can be read and written. It is Reset or Set by POR
SFR bit is not present in device.
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memory organization
MSP430C111
FFFFh
FFE0h
FFDFh
Int. Vector
2 KB ROM
FFFFh
FFE0h
FFDFh
F800h
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430P112
PMS430E112
MSP430C112
Int. Vector
FFFFh
FFE0h
FFDFh
4 KB
EPROM
4 KB ROM
128B RAM
16b Per.
8b Per.
SFR
F000h
F000h
02FFh
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
256B RAM
16b Per.
8b Per.
SFR
Int. Vector
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
256B RAM
16b Per.
8b Per.
SFR
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature
number SLAU049.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of Port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for Port
P2 are implemented.
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watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
13 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
9 - P2.1
INCLK
INCLK
14 - P1.1
TA0
CCI0A
10 - P2.2
TA0
CCI0B
15 - P1.2
11 - P2.3
16 - P1.3
DVSS
DVCC
TA1
VCC
CCI1A
TA1
CCI1B
DVSS
DVCC
GND
Module Output Signal
Timer
NA
GND
TA2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
Module Block
GND
Output Pin Number
14 - P1.1
18 - P1.5
CCR0
TA0
10 - P2.2
15 - P1.2
19 - P1.6
CCR1
TA1
11 - P2.3
16 - P1.3
20 - P1.7
CCR2
TA2
12 - P2.4
VCC
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SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog/Timer Control
WDTCTL
0120h
Timer_A
Timer_A Interrupt Vector
Timer_A Control
Cap/Com Control
Cap/Com Control
Cap/Com Control
Reserved
Reserved
Reserved
Reserved
Timer_A Register
Cap/Com Register
Cap/Com Register
Cap/Com Register
Reserved
Reserved
Reserved
Reserved
TAIV
TACTL
TACCTL0
TACCTL1
TACCTL2
012Eh
0160h
0162h
0164h
0166h
0168h
016Ah
016Ch
016Eh
0170h
0172h
0174h
0176h
0178h
017Ah
017Ch
017Eh
TAR
TACCR0
TACCR1
TACCR2
PERIPHERALS WITH BYTE ACCESS
10
Basic Clock
Basic Clock Sys. Control2
Basic Clock Sys. Control1
DCO Clock Freq. Control
BCSCTL2
BCSCTL1
DCOCTL
058h
057h
056h
EPROM
EPROM Control
EPCTL
054h
Port P2
Port P2 Selection
Port P2 Interrupt Enable
Port P2 Interrupt Edge Select
Port P2 Interrupt Flag
Port P2 Direction
Port P2 Output
Port P2 Input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 Selection
Port P1 Interrupt Enable
Port P1 Interrupt Edge Select
Port P1 Interrupt Flag
Port P1 Direction
Port P1 Output
Port P1 Input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR Interrupt Flag1
SFR Interrupt Enable1
IFG1
IE1
002h
000h
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absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TEST pin when blowing the JTAG fuse.
recommended operating conditions
MIN
Supply voltage, VCC
Supply voltage during programming, VCC
NOM
MAX
UNITS
MSP430C11x
2.5
5.5
MSP430P112
2.7
5.5
PMS430E112
2.7
5.5
V
MSP430P112
4.5
5
5.5
V
MSP430E112
4.5
5
5.5
V
V
MSP430C11x
MSP430P112
Operating free-air temperature range, TA
−40
PMS430E112
85
XTAL frequency, f(XTAL),(ACLK signal)
32 768
Processor frequency f(system) (PMS430P/E112) (MCLK signal)
f(system) − Maximum Processor Frequency − MHz
Processor frequency f(system) (MCLK signal) (MSP430C11x)
°C
C
25
Hz
VCC = 3 V
dc
2
VCC = 5 V
VCC = 3 V
dc
5.35
dc
2.73
VCC = 5 V
dc
5.35
MHz
MHz
5
5.35 MHz
at 5 V
4
3
2.2 MHz
at 2.5 V
2
1
Minimum
0
0
1
2
3
4
5
6
7
VCC − Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock.
Figure 1. C Version Frequency vs Supply Voltage
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f(system) − Maximum Processor Frequency − MHz
recommended operating conditions (continued)
5
5.35 MHz
at 5 V
4
3
2
1.1 MHz
at 2.7 V
1.1
Minimum
0
0
1
2
3
4
5
6
7
VCC − Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock.
Figure 2. P/E Version Frequency vs Supply Voltage
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into VCC) excluding external current
PARAMETER
TEST CONDITIONS
NOM
MAX
TA = −40
−40°C
C +85°C,
+85 C, f(MCLK) = f(SMCLK) = 1 MHz, VCC = 3 V
f(ACLK) = 32,768 Hz
VCC = 5 V
VCC = 3 V
TA = −40
−40°C
C +85
+85°C,
C,
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz
VCC = 5 V
330
400
630
700
3.4
4
7.8
10
TA = −40°C +85°C,
fMCLK = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
VCC = 3 V
400
500
VCC = 5 V
730
900
TA = −40
−40°C
C +85
+85°C,
C,
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz
VCC = 3 V
VCC = 5 V
3.4
4
7.8
10
C11x
TA = −40
−40°C
C +85
+85°C,
C, fMCLK = 0 MHz,
f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz
VCC = 3 V
VCC = 5 V
P112
−40°C
+85°C,
TA = −40
C +85
C, f(MCLK) = 0 MHz,
f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz
VCC = 3 V
VCC = 5 V
TA = −40°C +85°C,
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0, Rsel = 3
TA = −40°C
f(MCLK) = f(SMCLK) = 0 MHz,
TA = 25°C
f(ACLK) = 32,768 Hz,
SCG0 = 1
TA = 85°C
TA = −40°C
f(MCLK) = f(SMCLK) = 0 MHz,
TA = 25°C
f(ACLK) = 32,768 Hz, SCG0 = 1
TA = 85°C
C11x
I(AM)
Active mode
P112
I(CPUOff)
I(LPM2)
I(LPM3)
I(LPM4)
Low power mode,
(LPM0)
Low power mode, (LPM2)
Low power mode, (LPM3)
Low power mode, (LPM4)
TA = −40°C
TA = 25°C
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz,
SCG0 = 1
TA = 85°C
NOTE: All inputs are tied to VSS or VCC. Outputs do not source or sink any current.
MIN
51
60
120
150
70
85
125
170
VCC = 3 V
8
22
VCC = 5 V
16
35
2
2.6
VCC = 3 V
1.5
2.2
1.85
2.2
6.3
8
5.1
7
VCC = 5 V
VCC = 3 V/
5V
5.1
7
0.1
0.8
0.1
0.8
0.4
1
UNIT
µA
µA
µA
µA
µA
µA
µA
µA
current consumption of active mode versus system frequency
IAM = IAM[1 MHz] × fsystem [MHz]
current consumption of active mode versus supply voltage
IAM = IAM[3 V] + 175 µA/V × (VCC−3 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys
Input voltage hysteresis, (VIT+ − VIT−)
MIN
NOM
MAX
VCC = 3 V
VCC = 5 V
1.2
2.1
2.3
3.4
VCC = 3 V
VCC = 5 V
VCC = 3 V
0.7
1.5
1.4
2.3
0.3
1
VCC = 5 V
0.6
1.4
UNIT
V
V
V
standard inputs RST/NMI, TCK, TMS, TDI
PARAMETER
VIL
VIH
TEST CONDITIONS
Low-level input voltage
MIN
VSS
0.7xVCC
VCC = 3 V/5 V
High-level input voltage
NOM
MAX
UNIT
VSS+0.8
VCC
V
inputs Px.x, TAx
PARAMETER
t(int)
t(cap)
External Interrupt timing
Timer_A, capture timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x,
External trigger signal for the interrupt flag, (see Note 1)
TA0, TA1, TA2. (see Note 2)
VCC
MIN
3 V/ 5 V
1.5
3V
540
5V
270
3 V/ 5 V
1.5
3V
540
5V
270
NOM
MAX
UNIT
cycle
ns
cycle
ns
NOTES: 1. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with
trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set.
2. The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A
capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure
a correct capture of the 16-bit timer value and to ensure the flag is set.
internal signals TAx, SMCLK at Timer_A
PARAMETER
TEST CONDITIONS
f(IN)
Input frequency
Internal TA0, TA1, TA2, tH = tL
f(TAint)
Timer_A clock frequency
Internally, SMCLK signal applied
VCC
MIN
NOM
MAX
3V
dc
10
5V
dc
15
3 V/5 V
dc
fSystem
UNIT
MHz
leakage current (see Note 1)
PARAMETER
Ilkg(Px.x)
TEST CONDITIONS
High-impendance leakage current
MIN
NOM
MAX
Port P1: P1.x, 0 ≤ × ≤ 7
(see Note 2)
VCC = 3 V/5 V,
±50
Port P2: P2.x, 0 ≤ × ≤ 5
(see Note 2)
VCC = 3 V/5 V,
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
outputs P2x, TAx
PARAMETER
f(P20)
f(TAx)
TEST CONDITIONS
Output frequency
t(Xdc)
MIN
P2.0/ACLK,
CL = 20 pF
3 V/5 V
TA0, TA1, TA2,
CL = 20 pF
3 V/5 V
P2.0/ACLK, CL = 20 pF
fP20 = 1.1 MHz
fP20 = fXTCLK
3 V/ 5 V
Duty cycle of O/P frequency
fP20 = fXTCLK/n
CL = 20 pF,
TA0, TA1, TA2,
Duty cycle = 50%
t(TAdc)
VCC
NOM
MAX
UNIT
1.1
dc
fSystem
60%
40%
35%
MHz
65%
50%
3 V/ 5 V
0
±50
ns
NOM
outputs Port 1 to P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
I(OH) = − 1.5 mA,
I(OH) = − 4.5 mA,
VOL
Low-level output voltage
I(OL) = 1.5 mA,
I(OL) = 4.5 mA,
MIN
VCC = 3 V/5 V,
VCC = 3 V/5 V,
See Note 1
VCC = 3 V/5 V,
VCC = 3 V/5 V,
See Note 1
See Note 2
MAX
UNIT
VCC−0.4
VCC-0.6
VCC
VCC
V
VSS
VSS
VSS+0.4
VSS+0.6
V
See Note 2
NOTES: 1. The maximum total current, IOH and IOL, or all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop
specified.
2. The maximum total current, IOH and IOL, or all outputs combined, should not exceed ±36 mA to hold the maximum voltage drop
specified.
optional resistors, individually programmable with ROM code (see Note 1)
PARAMETER
TEST CONDITIONS
R(opt1)
R(opt2)
R(opt3)
R(opt4)
R(opt5)
R(opt6)
Resistors, individually programmable with ROM code, all port pins,
values applicable for pulldown and pullup
R(opt7)
R(opt8)
R(opt9)
MIN
NOM
MAX
VCC = 3 V/5 V
VCC = 3 V/5 V
2.1
4.1
6.2
UNIT
kΩ
3.1
6.2
9.3
kΩ
VCC = 3 V/5 V
VCC = 3 V/5 V
6
12
18
kΩ
10
19
29
kΩ
VCC = 3 V/5 V
VCC = 3 V/5 V
19
37
56
kΩ
38
75
113
kΩ
VCC = 3 V/5 V
VCC = 3 V/5 V
56
112
168
kΩ
94
187
281
kΩ
VCC = 3 V/5 V
VCC = 3 V/5 V
131
261
392
kΩ
R(opt10)
167
337
506
kΩ
NOTE 1: Optional resistors Roptx for pulldown or pullup are not programmed in standard OTP or EPROM devices MSP430P112 or PMS430E112.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PUC/POR
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
150
250
µs
1.5
2.4
V
1.2
2.1
V
0.9
1.8
V
0
0.4
t(POR_Delay)
VPOR
TA = −40°C
TA = 25°C
POR
VCC = 3 V/5 V
TA = 85°C
V(min)
t(reset)
PUC/POR
Reset is accepted internally
V
µs
2
V
VCC
V
POR
No POR
POR
V
(min)
POR
t
Figure 3. Power-On Reset (POR) vs Supply Voltage
3
2.4
V POR [V]
2.5
2.1
1.8
2
1.5
1.5
1
1.2
0.9
0.5
25°C
0
−40
−20
0
20
40
Temperature [°C]
Figure 4. VPOR vs Temperature
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
60
80
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPMx)
PARAMETER
t(LPM0)/
t(LPM2)
t(LPM3)
t(LPM4)
Delay time
TEST CONDITIONS
RSel = 4, DCO = 3, MOD = 0
RSel = 4, DCO = 3, MOD = 0
MIN
NOM
MAX
UNIT
VCC = 3 V/5 V
100
ns
VCC = 3 V/5 V
VCC = 3 V/5 V
2.6
6
µs
2.8
6
µs
RAM
PARAMETER
MIN
NOM
MAX
UNIT
V(RAMh)
CPU halted (see Note 1)
1.8
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
DCO (MSP430P112)
PARAMETER
TEST CONDITIONS
MIN
NOM
f(DCO03)
Rsel = 0, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
Rsel = 1, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.19
f(DCO13)
f(DCO23)
Rsel = 2, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.31
f(DCO33)
Rsel = 3, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
f(DCO43)
Rsel = 4, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.5
0.8
1.1
0.6
0.9
1.2
f(DCO53)
Rsel = 5, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.9
1.2
1.55
1.1
1.4
1.7
f(DCO63)
Rsel = 6, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
1.7
2
2.3
2.1
2.4
2.7
f(DCO73)
Rsel = 7, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
2.8
3.1
3.5
3.8
4.2
4.5
f(DCO47)
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V/5 V
S(Rsel)
SR = fRsel+1/fRsel
VCC = 3 V/5 V
1.4
1.65
1.9
S(DCO)
SDCO = fDCO+1/fDCO
VCC = 3 V/5 V
1.07
1.12
1.16
Temperature drift, Rsel = 4, DCO = 3,
MOD = 0 (see Note 1)
VCC = 3 V
−0.31
−0.36
−0.40
Dt
VCC = 5 V
−0.33
−0.38
−0.43
DV
Drift with VCC variation, Rsel = 4, DCO = 3,
MOD = 0 (see Note 1)
0
5
10
VCC = 3 V to 5 V
0.12
MAX
VCC = 3 V
VCC = 5 V
UNIT
MHz
0.13
MHz
0.21
MHz
0.34
0.5
MHz
0.55
FDCO40 FDCO40 FDCO40
x1.8
x2.2
x2.6
MHz
MHz
MHz
MHz
MHz
ratio
%/°C
%/V
NOTE 1: These parameters are not production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO (MSP430C111, C112)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
0.07
0.10
Rsel = 0, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.04
f(DCO03)
0.04
0.07
0.10
0.13
0.18
Rsel = 1, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.08
f(DCO13)
0.08
0.13
0.18
f(DCO23)
Rsel = 2, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.15
0.22
0.30
0.15
0.22
0.30
f(DCO33)
Rsel = 3, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.26
0.36
0.47
0.26
0.36
0.47
f(DCO43)
Rsel = 4, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.4
0.6
0.8
0.4
0.6
0.8
f(DCO53)
Rsel = 5, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
0.8
1.1
1.4
0.8
1.1
1.4
f(DCO63)
Rsel = 6, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
1.3
1.7
2.1
1.5
1.9
2.3
f(DCO73)
Rsel = 7, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V
VCC = 5 V
2.4
2.9
3.4
3.1
3.8
4.5
f(DCO47)
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 3 V/5 V
S(Rsel)
SR = fRsel+1/fRsel
VCC = 3 V/5 V
1.4
1.65
1.9
S(DCO)
SDCO = fDCO+1/fDCO
VCC = 3 V/5 V
1.07
1.12
1.16
Temperature drift, Rsel = 4, DCO = 3,
MOD = 0 (see Note 1)
VCC = 3 V
−0.31
−0.36
−0.40
Dt
VCC = 5 V
−0.33
−0.38
−0.43
DV
Drift with VCC variation, Rsel = 4, DCO = 3,
MOD = 0 (see Note 1)
0
5
10
FDCO40 FDCO40 FDCO40
x1.8
x2.2
x2.6
VCC = 3 V to 5 V
f(DCOx7)
f(DCOx0)
Max
Min
Max
Min
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
3
1
f DCOCLK
Frequency Variance
NOTE 1: These parameters are not production tested.
5
0
1
VCC
3
4
5
6
DCO Steps
Figure 5. DCO Characteristics
18
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ratio
%/°C
%/V
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D Individual devices have a minimum and maximum operation frequency. The specified parameters for
f(DCOx0) to f(DCOx7) are valid for all devices.
D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.
D Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:
f average +
MOD
32 f (DCO) f (DCO)1)
f (DCO))(32*MOD) f (DCO)1)
crystal oscillator, XIN, XOUT
PARAMETER
CXIN
Capacitance at input
CXOUT
Capacitance at output
VIL
VIH
Input levels at XIN
TEST CONDITIONS
MIN
VCC = 3 V/5 V
VCC = 3 V/5 V
VCC = 3 V/5 V (see Note 2)
NOM
MAX
12
pF
12
VSS
0.8×VCC
UNIT
pF
0.2×VCC
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
EPROM Memory, P- and E- versions only (see Note 1)
TEST
CONDITIONS
PARAMETER
V(PP)
I(PP)
Programming voltage, applied to TEST/VPP
t(pps)
t(ppf)
Programming time, single pulse
P(n)
Number of pulses for successful programming
t(erase)
VCC
MIN
NOM
MAX
12
12.5
13
V
70
mA
Current from programming voltage source
5
Programming time, fast algorithm
ms
µs
100
4
Erase time:
Wave length 2537 Å at 15 Ws/cm2
(UV lamp of 12 mW/ cm2)
100
30
Write/erase cycles
Pulse
min
1000
Data retention Tj < 55°C
UNIT
cycles
10
Year
NOTES: 1. Refer to the Recommended Operating Conditions for the correct VCC during programming.
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
VCC
MIN
3V
DC
5
5V
DC
10
VCC
MIN
Fuse blow voltage, C versions (see Note 2)
3 V/ 5 V
5.5
6
Fuse blow voltage, E/P versions (see Note 2)
3 V/ 5 V
11
13
TCK input frequency
see Note 1
NOM
MAX
UNIT
MHz
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VFB
IFB
tFB
Supply current into TEST/VPP during fuse blow
Time to blow fuse
NOM
MAX
UNIT
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
2. The fuse blow voltage is applied to the TEST/VPP pin.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
VCC
P1SEL.x
0
P1DIR.x
(See Note 1)
1
Direction Control
From Module
(See Note 2)
0
P1OUT.x
Pad Logic
P1.0 − P1.3
1
Module X OUT
(See Note 2)
(See Note 1)
P1IN.x
GND
EN
D
Module X IN
P1IRQ.x
P1IE.x
P1IFG.x
Q
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P1IES.x
P1SEL.x
NOTE: x = Bit Identifier, 0 to 3 For Port P1
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
Module X
OUT
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
VSS
Out0 signal†
Out1 signal†
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
Out2 signal†
PnIN.x
P1IN.0
P1IN.3
P1IN.1
P1IN.2
Module X
IN
PnIE.x
PnIFG.x
PnIES.x
TACLK†
CCI0A†
P1IE.0
P1IFG.0
P1IES.0
P1IE.1
P1IFG.1
P1IES.1
CCI1A†
CCI2A†
P1IE.2
P1IFG.2
P1IES.2
P1IE.3
P1IFG.3
P1IES.3
† Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
VCC
(see Note 1)
(see Note 2)
(see Note 2)
(see Note 1)
GND
CMOS INPUT (RST/NMI)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
P1SEL.x
P1DIR.x
Direction Control
From Module
P1OUT.x
VCC
0
See Note 1
1
See Note 2
0
Pad Logic
P1.4−P1.7
1
Module X OUT
See Note 2
See Note 1
GND
TS
T
P1IN.x
Bus Keeper
EN
Module X IN
P1IRQ.x
D
P1IE.x
P1IFG.x
Q
Interrupt VPP_Internal
Edge
Select
EN
Set
Interrupt
Flag
TEST/VPP
TST
60 kΩ
Typical
Fuse
P1IES.x Control By JTAG
P1SEL.x
Fuse GND
Blow
TST
Control
P1.x
TDO
Controlled By JTAG
P1.7/TDI/TDO
Controlled by JTAG
NOTES:The test pin should be protected from potential EMI and
TDI
ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
TST
P1.x
P1.6/TDI
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing the
fuse, the pin TDO/TDI is used to apply the test input
for JTAG circuitry.
TST
TMS
P1.x
P1.5/TMS
TST
TCK
P1.x
P1.4/TCK
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
Module X
IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.4
P1DIR.4
P1DIR.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.4
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1OUT.5
Out0 signal†
Out1 signal†
P1IN.5
unused
P1IE.5
P1IFG.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
P1IES.5
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
P1IN.7
unused
P1IE.7
† Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
P1IFG.7
P1IES.7
Out2 signal†
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.0 to P2.4, input/output with Schmitt-trigger
P2SEL.x
VCC
0
P2DIR.x
0: Input
1
Direction Control
From Module
See Note 2
Pad Logic
0
P2OUT.x
See Note 1
1: Output
P2.0 − P2.4
1
Module X OUT
See Note 2
See Note 1
P2IN.x
EN
GND
D
Module X IN
P2IRQ.x
P2IE.x
P2IFG.x
Q
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit Identifier, 0 to 4 For Port P2
PnSel.x
PnDIR.x
Dir. Control
from module
PnOUT.x
Module X
OUT
PnIN.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2IN.0
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
P2DIR.2
P2DIR.2
P2OUT.2
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
VSS
Out0 signal†
Out1 signal†
P2IN.1
P2Sel.2
Module X
IN
PnIE.x
PnIFG.x
PnIES.x
unused
INCLK†
P2IE.0
P2IFG.0
P1IES.0
P2IE.1
P2IFG.1
P1IES.1
CCI0B†
CCI1B†
P2IE.2
P2IFG.2
P1IES.2
P2IE.3
P2IFG.3
P1IES.3
P2Sel.4
P2DIR.4
P2DIR.4
P2OUT.4
P2IN.4
unused
P2IE.4
† Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
P2IFG.4
P1IES.4
P2IN.2
P2IN.3
Out2 signal†
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module
VCC
P2SEL.5
0: Input
1: Output
0
P2DIR.5
Pad Logic
See Note 1
1
Direction Control
From Module
See Note 2
0
P2OUT.5
P2.5
1
Module X OUT
See Note 2
See Note 1
GND
Bus Keeper
P2IN.5
EN
Module X IN
D
VCC
P2IRQ.5
P2IE.5
P2IFG.5
Q
1
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
Internal to
Basic Clock
Module
0
P2IES.5
DC
Generator
DCOR
P2SEL.5
NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 is disconnected from P2.5 pad
PnSel.x
Director
Control from
module
PnOUT.x
Module X
OUT
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
VSS
P2IN.5
unused
P2IE.5
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions.
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory.
P2IFG.5
P2IES.5
POST OFFICE BOX 655303
PnIN.x
Module X
IN
PnIE.x
24
PnDIR.x
• DALLAS, TEXAS 75265
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, un-bonded bits P2.6 and P2.7
P2SEL.x
0: Input
1: Output
0
P2DIR.x
1
Direction Control
From Module
0
P2OUT.x
1
Module X OUT
P2IN.x
Node Is Reset With PUC
EN
Bus Keeper
Module X IN
P2IRQ.x
D
P2IE.x
P2IFG.x
Q
PUC
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit identifier, 6 to 7 for Port P2 without external pins
P2Sel.x
P2DIR.x
Dir. Control
from module
P2OUT.x
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
Module X
OUT
VSS
VSS
P2IN.x
Module X
IN
P2IE.x
P2IFG.x
P2IES.x
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal
other than from software. They work then as soft interrupt.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 6). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITEST
ITF
Figure 6. Fuse Check Mode Current, MSP430x11x
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°−ā 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
PINS **
16
20
24
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
DIM
4040000 / D 02/98
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLAS196D− DECEMBER 1998 − REVISED SEPTEMBER 2004
MSP430C111IDW, MSP430C112IDW, MSP430P112IDW pin out
DW PACKAGE
(TOP VIEW)
TEST/VPP
VCC
P2.5/ROSC
VSS
XOUT/TCLK
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
PMS430E112 pin out
JL PACKAGE
(TOP VIEW)
TEST/VPP
VCC
P2.5/ROSC
VSS
XOUT/TCLK
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
28
POST OFFICE BOX 655303
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/PMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
MSP-EVK430A110
OBSOLETE
MSP430C111IDW
Package
Type
Package
Drawing
OBSOLETE
SOIC
DW
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
0
TBD
Call TI
Call TI
20
TBD
Call TI
Call TI
Call TI
MSP430P112AY
OBSOLETE
DIESALE
Y
0
MSP430P112IDW
ACTIVE
SOIC
DW
20
PMS430E112JL
OBSOLETE
CDIP
JL
20
25
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
TBD
Call TI
Level-1-260C-UNLIM
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCER003A – JANUARY 1997
JL (R-GDIP-T20)
CERAMIC DUAL-IN-LINE PACKAGE
0.975 (24,76)
0.930 (23,62)
11
20
0.300 (7,62)
0.245 (6,22)
1
10
0.050 (1,27)
0.015 (0,38)
0.050 (1,27)
0.015 (0,38)
Window
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
4040109/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only
Falls within MIL-STD-1835 GDIP1-T20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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