SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 D D D SN54ALS374A, SN54AS374 . . . J PACKAGE SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE (TOP VIEW) D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs Full Parallel Access for Loading Buffered Control Inputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 1D 1Q SN54ALS374A, SN54AS374 . . . FK PACKAGE (TOP VIEW) On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. 2D 2Q 3Q 3D 4D 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. 3 OE VCC 8Q D OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 logic symbol† OE CLK 1 logic diagram (positive logic) OE EN 11 CLK C1 1 11 C1 1D 2D 3D 4D 5D 6D 7D 8D 3 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 1D 3 2 1Q 1D 2Q 3Q 4Q To Seven Other Channels 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions SN54ALS374A 2 SN74ALS374A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current –1 –2.6 mA IOL TA Low-level output current 24 mA 70 °C High-level input voltage 2 2 12 Operating free-air temperature –55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 0 V V SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –0.4 mA 5V VCC = 4 4.5 IOH = –1 mA IOH = –2.6 mA VOL VCC = 4 4.5 5V IOL = 12 mA IOL = 24 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH ICC SN54ALS374A TYP† MAX TEST CONDITIONS VCC = 5.5 V MIN SN74ALS374A TYP† MAX MIN –1.5 VCC–2 2.4 UNIT –1.5 V VCC–2 V 3.3 2.4 0.25 –20 0.4 3.2 0.25 0.4 0.35 0.5 V 20 20 µA –20 –20 µA 0.1 0.1 mA 20 20 µA –0.2 –0.2 mA –112 mA –112 –30 Outputs high 11 20 11 19 Outputs low 19 28 19 28 mA Outputs disabled 20 31 20 31 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended operating free-air temperature range (unless otherwise noted) SN54ALS374A MIN fclock tw Clock frequency Pulse duration CLK high or low tsu th Setup time Data before CLK↑ Hold time Data after CLK↑ MAX SN74ALS374A MIN 30 MAX 35 UNIT MHz 16.5 14 ns 10 10 ns 4 0 ns switching characteristics over recommended operating conditions (unless otherwise noted (see Figure 3) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) SN54ALS374A MIN MAX 30 CLK Q OE Q OE Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS374A MIN MAX 35 UNIT MHz 3 14 3 12 5 17 5 16 3 18 3 17 5 21 5 18 1 11 1 10 2 19 2 18 ns ns ns 3 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 recommended operating conditions SN54AS374 SN74AS374 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current –12 –15 mA IOL TA Low-level output current 32 48 mA 70 °C High-level input voltage 2 Operating free-air temperature 2 –55 125 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –2 mA VCC = 4 4.5 5V IOH = –12 mA IOH = –15 mA VOL VCC = 4 4.5 5V IOL = 32 mA IOL = 48 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VOH IIL OE, CLK Data IO‡ ICC VCC = 5 5.5 5V V, VI = 0 0.4 4V VCC = 5.5 V, VO = 2.25 V Outputs high VCC = 5.5 V SN54AS374 TYP† MAX MIN SN74AS374 TYP† MAX MIN –1.2 VCC–2 2.4 –1.2 UNIT V VCC–2 V 3.2 2.4 0.29 3.3 0.5 0.34 –30 0.5 V µA 50 50 –50 –50 µA 0.1 0.1 mA µA 20 20 –0.5 –0.5 –3 –2 –112 –30 –112 77 120 77 120 Outputs low 84 128 84 128 Outputs disabled 84 128 84 128 mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. timing requirements over recommended operating free-air temperature range (unless otherwise noted) SN54AS374 MIN fclock Clock frequency tw Pulse duration tsu th SN74AS374 MIN 100* CLK high MAX 125 UNIT MHz 5.5* 4 CLK low 3* 3 Setup time Data before CLK↑ 3* 2 ns Hold time Data after CLK↑ 3* 2 ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. 4 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ FROM (INPUT) TO (OUTPUT) SN54AS374 MIN MAX 100* CLK Q OE Q OE Q tPLZ * On products compliant to MIL-PRF-38535, this parameter is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AS374 MIN MAX 125 UNIT MHz 3 11 3 8 4 11.5 4 9 2 7 2 6 3 11 3 10 2 10 2 6 2 7 2 6 ns ns ns 5 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 APPLICATION INFORMATION Four SN54ALS374A, SN74ALS374A, or ’AS374 EN C 8 8 ’ALS139 A Output-Enable Select B G X/Y 1 2 0 EN 1 C 2 EN 8 8 3 A Input Clock Select B EN G C 8 Clock 8 EN C 8 8 Input Figure 1. Expandable 4-Word by 8-Bit General File Register 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8 8 Output SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 APPLICATION INFORMATION SN54ALS374A, SN74ALS374A, or ’AS374 Output Enable 1 EN Clock 1 C1 1D Bidirectional Data Bus 1 Bidirectional Data Bus 2 SN54ALS374A, SN74ALS374A, or ’AS374 EN Output Enable 2 Clock 2 C1 1D Clock 1 H Bus-Exchange Clock Clock 2 H Clock Circuit for Bus Exchange Figure 2. Bidirectional Bus Driver POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V VCC S1 500 Ω From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) CL = 50 pF (see Note A) 500 Ω 3.5 V Timing Input 500 Ω 3.5 V High-Level Pulse 1.3 V Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS 500 Ω From Output Under Test CL = 50 pF (see Note A) Test Point 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control 1.3 V 1.3 V 3.5 V 0.3 V tPZL 1.3 V Input tPLZ 1.3 V 0.3 V ≈3.5 V Waveform 1 S1 Closed (see Note B) 1.3 V tPZH Waveform 2 S1 Open (see Note B) tPLH VOL + 0.3 V VOL In-Phase Output tPHZ 1.3 V VOH VOH – 0.3 V ≈0 V 1.3 V tPHL Out-of-Phase Output (see Note C) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS tPHL VOH 1.3 V VOL tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 3. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9756201Q2A ACTIVE LCCC FK 20 1 TBD 5962-9756201QRA ACTIVE CDIP J 20 1 TBD 5962-9756201QSA ACTIVE CFP W 20 1 TBD 83020022A ACTIVE LCCC FK 20 1 TBD 8302002RA ACTIVE CDIP J 20 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type A42 N / A for Pkg Type 8302002SA ACTIVE CFP W 20 1 TBD JM38510/37204B2A ACTIVE LCCC FK 20 1 TBD JM38510/37204BRA ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SN54ALS374AJ ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SN54AS374J ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SN74ALS374ADBLE OBSOLETE SSOP DB 20 TBD Call TI SN74ALS374ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374AN ACTIVE PDIP N 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS374AN3 OBSOLETE PDIP N 20 TBD Call TI SN74ALS374ANE4 ACTIVE PDIP N 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ALS374ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALS374ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS374DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS374DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS374DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS374DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM 20 20 Addendum-Page 1 POST-PLATE N / A for Pkg Type Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AS374DWRG4 ACTIVE SOIC DW 20 SN74AS374N ACTIVE PDIP N 20 SN74AS374N3 OBSOLETE PDIP N 20 SN74AS374NE4 ACTIVE PDIP N 20 SN74AS374NSR ACTIVE SO NS 20 SN74AS374NSRE4 ACTIVE SO NS SN74AS374NSRG4 ACTIVE SO SNJ54ALS374AFK ACTIVE SNJ54ALS374AJ ACTIVE SNJ54ALS374AW ACTIVE SNJ54AS374FK ACTIVE SNJ54AS374J ACTIVE SNJ54AS374W ACTIVE Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TBD Call TI Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LCCC FK 20 1 TBD CDIP J 20 1 TBD CFP W 20 1 TBD LCCC FK 20 1 TBD CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type CFP W 20 1 TBD A42 N / A for Pkg Type 20 20 Call TI POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 19-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALS374ADBR DB 20 MLA 330 16 8.2 7.5 2.5 12 16 Q1 SN74ALS374ADWR DW 20 MLA 330 24 10.8 13.0 2.7 12 24 Q1 SN74ALS374ANSR NS 20 MLA 330 24 8.2 13.0 2.5 12 24 Q1 SN74AS374DWR DW 20 MLA 330 24 10.8 13.0 2.7 12 24 Q1 SN74AS374NSR NS 20 MLA 330 24 8.2 13.0 2.5 12 24 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74ALS374ADBR DB 20 MLA 342.9 336.6 28.58 SN74ALS374ADWR DW 20 MLA 333.2 333.2 31.75 SN74ALS374ANSR NS 20 MLA 333.2 333.2 31.75 SN74AS374DWR DW 20 MLA 333.2 333.2 31.75 SN74AS374NSR NS 20 MLA 333.2 333.2 31.75 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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