TI SN74HC573APWT

SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V
D High-Current 3-State Outputs Drive Bus
D
D
D
D
Lines Directly or Up To 15 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
SN54HC573A . . . J OR W PACKAGE
SN74HC573A . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3D
4D
5D
6D
7D
OE
VCC
1Q
20
2D
1D
1
SN54HC573A . . . FK PACKAGE
(TOP VIEW)
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
3Q
4Q
5Q
6Q
8D
GND
LE
8Q
7Q
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
Typical tpd = 21 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Bus-Structured Pinout
description/ordering information
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the
outputs are latched to retain the data that was set up.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
PDIP − N
SN74HC573AN
Tube of 40
SN74HC573ADW
Reel of 2500
SN74HC573ADWR
Reel of 2000
SN74HC573ADBR
Reel of 2000
SN74HC573APWR
Reel of 250
SN74HC573APWT
CDIP − J
Tube of 25
SNJ54HC573AJ
SNJ54HC573AJ
CFP − W
Tube of 150
SNJ54HC573AW
SNJ54HC573AW
LCCC − FK
Tube of 55
SNJ54HC573AFK
SSOP − DB
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube of 25
SOIC − DW
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SN74HC573AN
HC573A
HC573A
HC573A
SNJ54HC573AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
$'"! !$& ./0
&& $## # ##'
"&# )#+# #'( && )# $'"!
$'"!
$!#- '# #!#&, !&"'# #- && $##(
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each latch)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1
11
C1
1D
2
19
1Q
1D
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC573A
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
MIN
NOM
MAX
2
5
6
Input voltage
MAX
2
5
6
3.15
3.15
4.2
4.2
0
VCC = 6 V
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
Input transition (rise and fall) time
NOM
1.5
0
Output voltage
MIN
1.5
VCC = 4.5 V
VCC = 6 V
Low-level input voltage
SN74HC573A
0
VCC
VCC
0
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VI = VCC or 0,
MIN
MAX
SN74HC573A
MIN
MAX
UNIT
1.9
1.998
1.9
1.9
IOH = −20 µA
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = −6 mA
IOH = −7.8 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
10
10
10
pF
IOL = 6 mA
IOL = 7.8 mA
ICC
Ci
SN54HC573A
2V
VI = VIH or VIL
VI = VCC or 0
VO = VCC or 0
TA = 25°C
MIN
TYP
MAX
4.5 V
VI = VIH or VIL
II
IOZ
VCC
IO = 0
6V
2 V to 6 V
POST OFFICE BOX 655303
3
• DALLAS, TEXAS 75265
V
V
3
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
tw
Pulse duration, LE high
tsu
Setup time, data before LE↓
th
Hold time, data after LE↓
TA = 25°C
MIN
MAX
SN54HC573A
MIN
MAX
SN74HC573A
MIN
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
50
75
63
4.5 V
10
15
13
6V
9
13
11
2V
20
24
24
4.5 V
5
5
5
6V
5
5
5
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
D
ten
tdis
tt
4
OE
OE
SN54HC573A
SN74HC573A
VCC
2V
77
175
265
220
Q
4.5 V
26
35
53
44
6V
23
30
45
38
2V
87
175
265
220
4.5 V
27
35
53
44
6V
23
30
45
38
2V
68
150
225
190
4.5 V
24
30
45
38
6V
21
26
38
32
2V
47
150
225
190
4.5 V
23
30
45
38
6V
21
26
38
32
2V
28
60
90
75
4.5 V
8
12
18
15
6V
6
10
15
13
tpd
LE
TA = 25°C
MIN
TYP
MAX
TO
(OUTPUT)
Any Q
Any Q
Any Q
Any Q
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
MIN
MAX
UNIT
ns
ns
ns
ns
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
SN54HC573A
SN74HC573A
TO
(OUTPUT)
VCC
2V
95
200
300
250
D
Q
4.5 V
33
40
60
50
6V
21
34
51
43
2V
103
225
335
285
4.5 V
33
45
67
57
6V
29
38
57
48
tpd
LE
ten
TA = 25°C
TYP
MAX
FROM
(INPUT)
Any Q
OE
Any Q
tt
Any Q
MIN
MIN
MAX
MIN
MAX
2V
85
200
300
250
4.5 V
29
40
60
50
6V
26
34
51
43
2V
60
210
315
265
4.5 V
17
42
63
53
6V
14
36
53
45
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per latch
No load
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
50
UNIT
pF
5
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
PARAMETER
S1
Test
Point
From Output
Under Test
ten
RL
tPZH
RL
CL
50 pF
or
150 pF
1 kΩ
tPZL
tdis
S2
tPLZ
1 kΩ
50 pF
−−
50 pF
or
150 pF
tpd or tt
LOAD CIRCUIT
50%
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
50%
0V
50%
tsu
0V
tw
Data
50%
Input 10%
VCC
Low-Level
Pulse
50%
50%
50%
0V
tPLH
50%
10%
tPHL
90%
90%
tr
tPHL
90%
tf
50%
10%
Output
Control
(Low-Level
Enabling)
50%
10% V
OL
tf
tPZL
Output
Waveform 1
(See Note B)
VOH
tPZH
VOH
tPLH
50%
10%
90%
90%
VCC
50%
10% 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VCC
50%
th
tr
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Out-ofPhase
Output
Open
VCC
Reference
Input
VCC
High-Level
Pulse
In-Phase
Output
S2
tPHZ
CL
(see Note A)
Input
S1
90%
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
50%
Output
Waveform 2
(See Note B)
50%
0V
tPLZ
≈VCC
50%
10%
≈VCC
VOL
tPHZ
50%
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
(1)
Orderable Device
Status (1)
Package
Type
5962-8512801VRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
5962-8512801VSA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
85128012A
ACTIVE
LCCC
FK
20
1
TBD
8512801RA
ACTIVE
CDIP
J
20
1
TBD
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
8512801SA
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
JM38510/65406BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
SN54HC573AJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
SN74HC573ADBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573ADWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573AN
ACTIVE
PDIP
N
20
CU NIPDAU
N / A for Pkg Type
20
Pb-Free
(RoHS)
TBD
Call TI
20
Pb-Free
(RoHS)
CU NIPDAU
SN74HC573AN3
OBSOLETE
PDIP
N
20
SN74HC573ANE4
ACTIVE
PDIP
N
20
SN74HC573APWLE
OBSOLETE
TSSOP
PW
20
SN74HC573APWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573APWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573APWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573APWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC573APWTG4
ACTIVE
TSSOP
PW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54HC573AFK
ACTIVE
LCCC
FK
20
1
TBD
SNJ54HC573AJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
SNJ54HC573AW
ACTIVE
CFP
W
20
1
TBD
Call TI
N / A for Pkg Type
TBD
The marketing status values are defined as follows:
Addendum-Page 1
Call TI
Call TI
N / A for Pkg Type
Call TI
POST-PLATE N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC573A, SN54HC573A-SP, SN74HC573A :
• Automotive: SN74HC573A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74HC573ADBR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SSOP
DB
20
2000
330.0
16.4
8.2
7.5
2.5
12.0
16.0
Q1
SN74HC573ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
SN74HC573APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC573ADBR
SSOP
DB
20
2000
346.0
346.0
33.0
SN74HC573ADWR
SOIC
DW
20
2000
346.0
346.0
41.0
SN74HC573APWR
TSSOP
PW
20
2000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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