TI CDCE18005RGZR

CDCE18005
www.ti.com........................................................................................................................................................................................... SCAS863 – NOVEMBER 2008
Five/Ten Output Clock Generator/Buffer
FEATURES
APPLICATIONS
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Universal Input Buffers That Accept LVPECL,
LVDS, or LVCMOS Level Signaling
Fully Configurable Outputs Including
Frequency, Output Format, and Output Skew
Output Multiplexer That Serves as a Clock
Switch Between the Three Reference Inputs
and the Outputs
Clock Generation Via AT-Cut Crystal
Integrated EEPROM Determines Device
Configuration at Power-up
Low Additive Jitter Performance
Universal Output Blocks Support up to 5
Differential, 10 Single-ended, or Combinations
of Differential or Single-ended:
– Low Additive Jitter
– Output Frequency up to 1.5 GHz
– LVPECL, LVDS, LVCMOS, and Special High
Output Swing Modes
– Independent Output Dividers Support
Divide Ratios from 1–80
– Independent limited Coarse Skew Control
on all Outputs
Flexible Inputs:
– Two Universal Differential Inputs Accept
Frequencies up to 1500 MHz (LVPECL), 800
MHz (LVDS), or 250 MHz (LVCMOS).
– One Auxiliary Input Accepts Single Ended
Clock Source or Crystal. Auxiliary Input
Accepts Crystals in the Range of 2 MHz–42
MHz or an LVCMOS Input up to 75 MHz.
– Clock Generator Mode Using Crystal Input.
Typical Power Consumption 1.0W at 3.3V (see
Table 27)
Integrated EEPROM Stores Default Settings;
Therefore, The Device Powers up in a Known,
Predefined State.
Offered in QFN-48 Package
ESD Protection Exceeds 2kV HBM
Industrial Temperature Range –40°C to 85°C
Data Converter and Data Aggregation Clocking
Wireless Infrastructure
Switches and Routers
Medical Electronics
Military and Aerospace
Industrial
Clock Fan-out
DESCRIPTION
The CDCE18005 is a high performance clock
generator and distributor featuring a high degree of
configurability via a SPI interface, and programmable
start up modes determined by on-board EEPROM.
Specifically tailored for buffering clocks for data
converters and high-speed digital signals, the
CDCE18005 achieves low additive jitter in the 50 fs
RMS (1) range. The clock distribution block includes
five individually programmable outputs that can be
configured to provide different combinations of output
formats (LVPECL, LVDS, LVCMOS). Each output can
also be programmed to a unique output frequency
(up to 1.5 GHz (2) ) and skew relationship via a
programmable delay block. If all outputs are
configured in single-ended mode (e.g. LVCMOS), the
CDCE18005 supports up to ten outputs. Each output
can select one of three clock input sources. The input
block includes two universal differential inputs which
support frequencies up to 1500 MHz and an auxiliary
single ended input that can be connected to a CMOS
level clock or configured to connect to an external
crystal via an on board oscillator block.
LVCMOS 25MHz
LVCMOS 25MHz
LVPECL 1.5GHz / LVDS 800MHz
LVPECL 800MHz
CDCE18005
Crystal 25MHz
LVDS 750MHz
LVDS 800MHz
LVPECL 1.5GHz
Figure 1. CDCE18005 Application Example
(1)
(2)
12 kHz to 20 MHz integration bandwidth.
Maximum output frequency depends on the output format
selected
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
CDCE18005
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DEVICE INFORMATION
PACKAGE
The CDCE18005 is packaged in a 48-Pin Plastic Quad Flatpack Package with enhanced bottom thermal pad for
heat dissipation. The Texas Instruments Package Designator is: RGZ (S-PQFP-N48)
36
25
37
24
Top View
Not up to Scale
48
13
1
12
Figure 2. 48-Pin QFN Package Outline
2
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PIN FUNCTIONS
PIN
NAME
QFN
TYPE
DESCRIPTION
VCC_OUT
8, 11,
15, 18,
21, 26,
29, 32
Power
3.3V Supply for the Output Buffers
VCC_CORE
5, 39,
42, 34,
35
Power
3.3V Core Voltage Circuitry
VCC_IN_PRI
47
A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.
VCC_IN_SEC
1
A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.
VCC_IN_AUX
44
A. Power 3.3V Crystal Oscillator Input Circuitry.
GND
36
Ground
Ground (All internal Ground Pins are connected to the PAD)
GND
PAD
Ground
Ground is on Thermal PAD. See Layout recommendation
SPI_MISO
22
OD
SPI_LE
25
I
LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in
SPI Mode. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to
logic level "1".
SPI_CLK
24
I
LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has
an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level "1".
SPI_MOSI
23
I
LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE18005 for the SPI bus
interface. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic
level "1".
TEST_MODE
33
I
Pull High or leave unconnected
TEST_MODE2
31
I
Pull High or leave unconnected
Power_Down
12
I
Active Low. Power down mode can be activated via this pin. See Table 13 for more details. The
input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level "1".
SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load the EEPROM.
SYNC
14
I
Active Low. Sync mode can be activated via this pin. See Table 13 for more details. The input has
an internal 150-kΩ, pull-up resistor if left unconnected it will default to logic level “1”.
AUX IN
43
I
Auxiliary Input is a single ended input including an on-board oscillator circuit so that a crystal may
be connected.
AUX OUT
13
O
Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by Output 2
or Output 3.
PRI REF+
45
I
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference Clock,
PRI REF–
46
I
Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In case of
LVCMOS signaling Ground this pin.
SEC REF+
3
I
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary Reference
Clock,
SEC REF–
2
I
Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. In
case of LVCMOS signaling Ground this pin.
TESTOUTA
30
Analog
NC
4
This Pin is not used
NC
38
This Pin is not used
VBB
48
NC
40
This Pin is not used
NC
41
This Pin is not used
NC
37
U0P:U0N
U1P:U1N:
U2P:U2N
U3P:U3N
U4P:U4N
27, 28
19, 20
16,17
9, 10
6, 7
Analog
In SPI Mode it is an Open Drain Output and it functions as a Master In Slave Out as a serial
Control Data Output to CDCE18005 .
Analog Test Point for Use for TI Internal Testing. Pull Down to GND Via a 1kΩ Resistor.
Capacitor for the internal termination Voltage. Connect to a 1µF Capacitor (Y5V)
This Pin is not used
O
The Main outputs of CDCE18005 are user definable and can be any combination of up to 5
LVPECL outputs, 5 LVDS outputs or up to 10 LVCMOS outputs. The outputs are selectable via
SPI interface. The power-up setting is EEPROM configurable.
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FUNCTIONAL DESCRIPTION
PRI_IN
Output
Divider 0
SEC_IN
XTAL /
AUX_IN
Output
Divider 1
Output
Divider 2
Output
Divider 3
Output
Divider 4
/Power_Down
U0P
U0N
U1P
U1N
U2P
U2N
U3P
U3N
U4P
U4N
/SYNC
SPI_LE
SPI_CLK
SPI_MISO
SPI_MOSI
Interface
&
Control
EEPROM
AUX
OUT
Figure 3. CDCE18005 Block Diagram
The CDCE18005 comprises three primary blocks: the interface and control block, the input block and the output
block. In order to determine which settings are appropriate for any specific combination of input/output
frequencies, a basic understanding of these blocks is required. The interface and control block determines the
state of the CDCE18005 at power-up based on the contents of the
on-board EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE18005 by writing
directly to the device registers after power-up. The input block buffers three clock signals, converts them to
differential signals, and drives them onto an internal clock distribution bus. The output block provides five
separate clock channels that are fully programmable and configurable to select and condition one of four internal
clock sources
NOTE:
This Section of the data sheet provides a high-level description of the features of the
CDCE18005 for purpose of understanding its capabilities. For a complete description
of device registers and I/O, please refer to the Device Configuration Section.
4
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Interface and Control Block
The CDCE18005 is a highly flexible and configurable architecture and as such contains a number of registers so
that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM
determine device configuration at all times. The CDCE18005 implements the SPI Interface Mode. SPI Interface
Mode is used to access the device RAM and EEPROM either during normal operation (if the host system
provides a native SPI interface) or during device configuration (i.e. device programming). During power up the
EEPROM content gets copied into the registers after the detection of a valid device power-up. The EEPROM can
be locked enabling the designer to implement a fault tolerant design.
Static RAM (Device Registers)
Register 8
Register 7
Register 6
/Power_Down
/SYNC
SPI_LE
SPI_CLK
SPI_MISO
SPI_MOSI
Register 5
Interface
&
Control
Device
Hardware
Register 4
Register 3
Register 2
Register 1
Register 0
EEPROM (Default Configuration)
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Figure 4. CDCE18005 Interface and Control Block
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Input Block
The Input Block includes a pair of Universal Input Buffers and an Auxiliary Input. The Input Block buffers the
incoming signals and facilitates signal routing to the Internal Clock Distribution bus. The Internal Clock
Distribution Bus connects to all output blocks discussed in the next section. Therefore, a clock signal present on
the Internal Clock Distribution bus can appear on any or all of the device outputs.
1500 MHz
LVPECL : 1500 MHz
LVDS : 800 MHz
LVCMOS : 250 MHz
SEC_IN
Crystal : 2MHz – 42MHz
Single Ended : 2MHz – 75MHz
1500 MHz
XTAL /
AUX_IN
Internal Clock Distribution Bus
PRI_IN
Figure 5. CDCE18005 Input Block
6
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Output Block
Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a
universal output array as shown.
Internal Clock Distribution Bus
Output
MUX
Control
Sync
Pulse
Digital Phase Adjust
PRI_IN
Output Buffer Control
Enable
(7 -bits )
UxP
SEC_IN
/1,2,3,4,5Clock Divider
/1 - /8 Module 0/2- 4
SMART_MUX
LVDS
UxN
SYNTH
LVPECL
Figure 6. CDCE18005 Output Block (1 of 5)
Clock Divider Module 0–4
The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel
is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device
power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each
output.
Enable
Sync Pulse
(internally generated)
From
Output
MUX
Digital Phase Adjust (7-bits)
To
Output
Buffer
/1 - /80
Figure 7. CDCE18005 Output Divider Module (1 of 5)
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage range (2)
VI
Input voltage range (3)
VO
Output voltage range
(3)
V
–0.5 to VCC + 0.5
V
–0.5 to VCC + 0.5
V
±20
mA
Output current for LVPECL/LVCMOS Outputs (0 < VO < VCC)
±50
mA
125
°C
–65 to 150
°C
Maximum junction temperature
Tstg
Storage temperature range
(2)
(3)
UNIT
Input Current (VI < 0, VI > VCC)
TJ
(1)
VALUE
-0.5 to 4.6
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All supply voltages have to be supplied simultaneously.
The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
THERMAL CHARACTERISTICS
Package Thermal Resistance for QFN (RGZ) Package
(1) (2)
AIRFLOW (LFM)
(1)
(2)
(3)
8
θJP (°C/W) (3)
θJA (°C/W)
0
JEDEC Compliant Board (6X6 VIAs on PAD)
2
28.9
100
JEDEC Compliant Board (6X6 VIAs on PAD)
2
20.4
0
Recommended Layout (7X7 VIAs on PAD)
2
27.3
100
Recommended Layout (7X7 VIAs on PAD)
2
20.3
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0,3 mm diameter).
θJP (Junction – Pad) is used for the QFN Package, because the main heat flow is from the Junction to the GND-Pad of the QFN.
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VCC
Supply voltage
3
3.3
3.6
VCC_IN &
VCore
Analog supply voltage
3
3.3
3.6
PLVPECL
REF at 491.52 MHz, Outputs are
LVPECL
PLVDS
REF at 491.52 MHz, Outputs are LVDS
PLVCMOS
REF at 491.52 MHz, Outputs are
LVCMOS
POFF
REF at 491.52 MHz
Output
MHz)
Output
Output
Output
Output
1 = 491.52 MHz (LVCMOS = 245
2
3
4
5
= 245.76 MHz
= 122.88 MHz
= 61.44 MHz
= 30.72 MHz
Dividers are disabled.
Outputs are disabled.
PPD
Device is powered down
V
1.6
W
1.3
W
1.5
W
0.45
W
20
mW
DIFFERENTIAL INPUT MODE (PRI_IN, SEC_IN)
VINPP
Input amplitude (VIN – VIN)
0.1
1.3
V
VIC
Common-mode input voltage
1.0
VCC–0.3
V
IIH
Differential input current high (no internal
termination)
VI = VCC, VCC = 3.6 V
20
µA
IIL
Differential input current low (no internal
termination)
VI = 0 V, VCC = 3.6 V
20
µA
–20
Input Capacitance on PRI_IN, SEC_IN
3
pF
LVCMOS INPUT MODE (AUX_IN)
VIL
Low-level input voltage LVCMOS
VIH
High-level input voltage LVCMOS
0
0.7 VCC
VIK LVCMOS input clamp voltage
VCC = 3 V, II = –18 mA
IIH
LVCMOS input current
VI = VCC, VCC = 3.6 V
IIL
LVCMOS input
VI = 0 V, VCC = 3.6 V
CI
Input capacitance (LVCMOS signals)
VI = 0 V or VCC
0.3 VCC
V
VCC
V
–1.2
–10
V
µA
300
10
8
µA
pF
CRYSTAL INPUT SPECIFICATIONS
Crystal shunt capacitance
20
pF
Equivalent series resistance (ESR)
50
Ω
0.3 VCC
V
VCC
V
LVCMOS INPUT MODE (SPI_CLK,SPI_MOSI,SPI_LE,PD,SYNC,REF_SEL, PRI_IN, SEC_IN )
Low-level input voltage LVCMOS,
0
High-level input voltage LVCMOS
0.7 VCC
VIK
LVCMOS input clamp voltage
VCC = 3 V, II = –18 mA
–1.2
IIH
LVCMOS input current
VI = VCC, VCC = 3.6 V
IIL
LVCMOS input (Except PRI_IN and
SEC_IN)
VI = 0 V, VCC = 3.6 V
–10
IIL
LVCMOS input (PRI_IN and SEC_IN)
VI = 0 V, VCC = 3.6 V
–10
CI
Input capacitance (LVCMOS signals)
VI = 0 V or VCC
–40
µA
10
µA
3
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V
µA
pF
9
CDCE18005
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued)
recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1) MAX
UNIT
SPI OUTPUT (MISO)
IOH
High-level output current
VCC = 3.3 V,
VO = 1.65 V
–30
mA
IOL
Low-level output current
VCC = 3.3 V,
VO = 1.65 V
33
mA
VOH
High-level output voltage for LVCMOS outputs
VCC = 3 V,
IOH = −100 µA
VOL
Low-level output voltage for LVCMOS outputs
VCC = 3 V,
IOL = 100 µA
CO
Output capacitance on MISO
VCC = 3.3 V; VO = 0 V or VCC
3-state output current
VO = VCC , VO = 0 V
Termination voltage for reference inputs.
IBB = –0.2 mA, Depending on the
setting.
IOZH
IOZL
VCC–0.5
V
0.3
3
V
pF
5
µA
–5
VBB
VBB
0.9
1.9
V
INPUT BUFFERS INTERNAL TERMINATION RESISTORS (PRI_IN and SEC_IN)
Termination resistance
(1)
10
Single ended
50
Ω
All typical values are at VCC = 3.3 V, temperature = 25 °C
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued)
recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1) MAX
UNIT
250
MHz
0.3
V
LVCMOS OUTPUT OR AUXILIARY OUTPUT
fclk
Output frequency, see Figure Below
Load = 5 pF to GND
VOH
High-level output voltage for LVCMOS
outputs
VCC = min to max
IOH = –100 µA
VOL
Low-level output voltage for LVCMOS
outputs
VCC = min to max
IOL =100 A
IOH
High-level output current
VCC = 3.3 V
VO = 1.65 V
–30
mA
IOL
Low-level output current
VCC = 3.3 V
VO = 1.65 V
33
mA
tpd(LH)/
tpd(HL)
Propagation delay from PRI_IN or SEC_IN
to Outputs (LVCMOS to LVCMOS)
VCC/2 to VCC/2
4
ns
tsk(o)
Skew, output to output For Y0 to Y4
All Outputs set at 200 MHz,
Reference = 200 MHz
75
ps
CO
Output capacitance on Y0 to Y4
VCC = 3.3 V; VO = 0 V or VCC
5
pF
VO = VCC
5
µA
VO = 0 V
–5
µA
IOZH
3-State LVCMOS output current
IOZL
IOPDH
IOPDL
Power Down output current
Duty cycle LVCMOS
tslew-rate
(1)
VCC –0.5
VO = VCC
25
µA
VO = 0 V
5
µA
50% to 50%
45%
Output rise/fall slew rate
3.6
55%
5.2
V/ns
All typical values are at VCC = 3.3 V, temperature = 25°C
LVCMOS
5 pF
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued) (1) (2) (3) (4)
recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
MIN TYP (5)
TEST CONDITIONS
MAX
UNIT
0
800
MHz
270
550
mV
50
mV
LVDS OUTPUT
fclk
Output frequency
Configuration Load (100 Ω)
|VOD|
Differential output voltage
RL = 100 Ω
ΔVOD
LVDS VOD magnitude change
VOS
Offset Voltage
ΔVOS
VOS magnitude change
–40°C to 85°C
1.24
V
40
mV
Short circuit Vout+ to ground
VOUT = 0
27
mA
Short circuit Vout– to ground
VOUT = 0
27
mA
tpd(LH)/tpd(HL) Propagation delay from PRI_IN or SEC_IN to
outputs (LVDS to LVDS)
Crosspoint to Crosspoint
3.1
ns
tsk(o) (6)
Skew, output to output For Y0 to Y4
All Outputs set at 200 MHz
Reference = 200 MHz
25
ps
CO
Output capacitance on Y0 to Y4
VCC = 3.3 V; VO = 0 V or VCC
IOPDH
Power down output current
VO = VCC
25
µA
IOPDL
Power down output current
VO = 0 V
5
µA
Duty cycle
50% input
Rise and fall time
20% to 80% of VOUT(PP)
110
160
190
ps
Crosspoint to VCC/2
0.9
1.4
1.9
ns
tr / tf
5
45%
pF
55%
LVCMOS-TO-LVDS
tskP_c
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Output skew between LVCMOS and LVDS
outputs (7)
This is valid only for same REF_IN clock and Y output clock frequency
VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of
100mV.
Lock output has a 80 kΩ pull-down resistor.
The phase of LVCMOS is lagging in reference to the phase of LVDS.
All typical values are at VCC = 3.3 V, temperature = 25°C
The tsk(o) specification is only valid for equal loading of all outputs.
Operating the LVCMOS or LVDS output above the maximum frequency will not cause a malfunction to the device, but the output signal
swing might no longer meet the output specification
LVDS DC Termination Test
100 Ω
12
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued)
recommended operating conditions for the CDCE18005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
MHz
LVPECL OUTPUT
fclk
Output frequency
0
1500
VOH
LVPECL high-level output voltage load
VCC –1.06
VCC –0.88
VOL
LVPECL low-level output voltage load
VCC –2.02
VCC –1.58
|VOD|
Differential output voltage
610
970
tpd(LH)/
tpd(HL)
Propagation delay from PRI_IN or SEC_IN to outputs
(LVPECL to LVPECL)
Crosspoint to Crosspoint
3.4
ns
tsk(o)
Skew, output to output For Y0 to Y4
All Outputs set at 200 MHz
Reference = 200MHz
25
ps
CO
Output capacitance on Y0 to Y4
VCC = 3.3 V; VO = 0 V or VCC
IOPDH
IOPDL
tr / tf
Configuration load (Figures below)
5
VO = VCC
Power Down output current
VO = 0 V
45%
V
V
mV
pF
25
µA
5
µA
Duty Cycle
50% input
55%
Rise and fall time
20% to 80% of Voutpp
55
75
135
ps
Crosspoint to Crosspoint
0.9
1.1
1.3
ns
–150
260
700
ps
V
LVDS-TO-LVPECL
tskP_C
Output skew between LVDS and LVPECL outputs
LVCMOS-TO-LVPECL
tskP_C
Output skew between LVCMOS and LVPECL outputs
VCC/2 to crosspoint
LVPECL HI-PERFORMANCE OUTPUT
VOH
LVPECL high-level output voltage load
VCC –1.11
VCC –0.87
VOL
LVPECL low-level output voltage load
VCC –2.06
VCC –1.73
|VOD|
Differential output voltage
760
1160
mV
tr / tf
Rise and fall time
135
ps
(1)
20% to 80% of Voutpp
55
75
V
All typical values are at VCC = 3.3 V, temperature = 25°C
LVPECL AC Termination Test
LVPECL DC Termination Test
50 Ω
Oscilloscope
50 Ω
150 Ω
150 Ω
50 Ω
Oscilloscope
50 Ω
Vcc-2
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LVPECL OUTPUT SWING
vs
FREQUENCY
HI SWING LVPECL OUTPUT SWING
vs
FREQUENCY
V
14
Figure 8.
Figure 9.
LVDS OUTPUT SWING
vs
FREQUENCY
LVCMOS OUTPUT SWING
vs
FREQUENCY
Figure 10.
Figure 11.
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TIMING REQUIREMENTS
over recommended ranges of supply voltage, load and operating free air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
250
MHz
1500
MHz
PRI_IN/SEC_IN_IN REQUIREMENTS
fmax
For Single ended Inputs ( LVCMOS) on PRI_IN and SEC_IN
For Differential Inputs on PRI_IN & SEC_IN
Single ended clock duty cycle of PRI_IN or SEC_IN at VCC / 2
40%
60%
Differential clock duty cycle of PRI_IN or SEC_IN at VCC / 2
40%
60%
AUXILARY_IN REQUIREMENTS
fREF
Single ended Inputs (LVCMOS) on AUX_IN
2
75
MHz
fREF
Crystal single ended Inputs (AT-Cut Crystal Input)
2
42
MHz
4
ns
Power_Down, SYNC, REF_SEL REQUIREMENTS
tr/ tf
Rise and fall time of the PD, SYNC, REF_SEL signal from 20% to 80% of VCC
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PHASE NOISE ANALYSIS
Table 1. Output Phase Noise for a 491.52 MHz External Reference
Phase Noise Specifications under following configuration: REF = 491.52 MHz Diff, LVPECL
Phase Noise
Reference
491.52 MHz
LVPECL
491.52 MHz
LVDS
245.52 MHz
LVCMOS
122.88 MHz
Unit
10 Hz
-86
-84
-90
-96
dBc/Hz
100 Hz
-100
-100
-105
-111
dBc/Hz
1 kHz
-108
-109
-115
-121
dBc/Hz
10 kHz
-130
-130
-136
-140
dBc/Hz
100 kHz
-135
-135
-140
-145
dBc/Hz
1 MHz
-138
-142
-143
-148
dBc/Hz
10 MHz
-150
-148
-150
-153
dBc/Hz
20 MHz
-150
-148
-150
-152
dBc/Hz
84
93
150
206
fs
Jitter(RMS)
10k~20Mhz
Table 2. Output Phase Noise for a 25 MHz Crystal Reference
Phase Noise Specifications under following configuration: REF = 25 MHz, SE:LVCMOS
Phase Noise
Reference
25.00 MHz
LVPECL
25 MHz
LVDS
25 MHz
LVCMOS
25 MHz
Unit
10 Hz
-
-83
-82
-82
dBc/Hz
100 Hz
-
-115
-116
-115
dBc/Hz
1 kHz
-
-142
-142
-141
dBc/Hz
10 kHz
-
-152
-149
-151
dBc/Hz
100 kHz
-
-155
-151
-155
dBc/Hz
1 MHz
-
-157
-151
-158
dBc/Hz
5 MHz
-
-157
-151
-158
dBc/Hz
Jitter(RMS)
10k~20 MHz
-
275
345
249
fs
SPI CONTROL INTERFACE TIMING
t1
t4
t5
SPI _ CLK
t2
SPI _ MOSI
Bit0
t3
Bit1
Bit29
Bit30
Bit31
t7
SPI _ LE
t6
Figure 12. Timing Diagram for SPI Write Command
16
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t4
t5
SPI _ CLK
t2
SPI _ MOSI
Bit30
t3
Bit31
t9
Bit0
SPI _ MISO
Bit1
Bit2
t7
SPI _ LE
t6
t8
Figure 13. Timing Diagram for SPI Read Command
SPI Bus Timing Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
20
MHz
fClock
Clock Frequency for the SPI_CLK
t1
SPI_LE to SPI_CLK setup time
10
ns
t2
SPI_MOSI to SPI_CLK setup time
10
ns
t3
SPI_MOSI to SPI_CLK hold time
10
ns
t4
SPI_CLK high duration
25
ns
t5
SPI_CLK low duration
25
ns
t6
SPI_CLK to SPI_LE Setup time
10
ns
t7
SPI_LE Pulse Width
20
ns
t8
SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE)
10
ns
DEVICE CONFIGURATION
The Functional Description Section described three different functional blocks contained within the CDCE18005.
Figure 14 depicts these blocks along with a high-level functional block diagram of the circuit elements comprising
each block. The balance of this section focuses on a detailed discussion of each functional block from the
perspective of how to configure them.
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Output Blocks
Output
Channel 0
Output
Channel 1
Input
Block
Interface
&
Control
Device
Registers
Output
Channel 2
Interface
&
Control
Block
Output
Channel 3
Output
Channel 4
EEPROM
Figure 14. CDCE18005 Circuit Blocks
Throughout this section, references to Device Register memory locations follow the following convention:
Register 5
5
Register Number (s)
4
3
RAM Bit Number (s)
2
5.2
Figure 15. Device Register Reference Convention
INTERFACE AND CONTROL BLOCK
The Interface & Control Block includes a SPI interface, four control pins, a non-volatile memory array in which
the device stores default configuration data, and an array of device registers implemented in Static RAM. This
RAM, also called the device registers, configures all hardware within the CDCE18005.
18
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Static RAM (Device Registers)
Register 8
Register 7
Register 6
/Power_Down
/SYNC
SPI_LE
SPI_CLK
SPI_MISO
SPI_MOSI
Register 5
Interface
&
Control
Device
Hardware
Register 4
Register 3
Register 2
Register 1
Register 0
EEPROM (Default Configuration)
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Figure 16. CDCE18005 Interface and Control Block
SPI (Serial Peripheral Interface)
The serial interface of CDCE18005 is a simple bidirectional SPI interface for writing and reading to and from the
device registers. It implements a low speed serial communications link in a master/slave topology in which the
CDCE18005 is a slave. The SPI consists of four signals:
• SPI_CLK: Serial Clock (Output from Master) – the CDCE18005 clocks data in and out on the rising edge of
SPI_CLK. Data transitions therefore occur on the falling edge of the clock.
• SPI_MOSI: Master Output Slave Input (Output from Master).
• SPI_MISO: Master Input Slave Output (Output from Slave).
• SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high,
no data transfer can take place.
The CDCE18005 implements data fields that are 28-bits wide. In addition, it contains 9 registers, each
comprising a 28 bit data field. Therefore, accessing the CDCE18005 requires that the host program append a
4-bit address field to the front of the data field as follows:
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Device Register N
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SPI Register
Address
Bits
(4)
Data Bits (28)
Last in /
Last out
SPI Master (Host)
First In /
First Out
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
3
2
1
0
SPI Slave (CDCE62005)
SPI_CLK
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MOSI
SPI_MISO
SPI_MISO
SPI_LE
SPI_LE
SPI_CLK
SPI_MOSI
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3
2
1
0
SPI_MISO
Figure 17. CDCE18005 SPI Communications Format
CDCE18005 SPI Command Structure
The CDCE18005 supports four commands issued by the Master via the SPI:
• Write to RAM
• Read Command
• Copy RAM to EEPROM – unlock
• Copy RAM to EEPROM – lock
Table 3 provides a summary of the CDCE18005 SPI command structure. The host (master) constructs a Write to
RAM command by specifying the appropriate register address in the address field and appends this value to the
beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. The
host must issue a Read Command to initiate a data transfer from the CDCE18005 back to the host. This
command specifies the address of the register of interest in the data field.
Table 3. CDCE18005 SPI Command Structure
Data Field (28 Bits)
Register
Addr Field
(4 Bits)
Operation
NVM
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
3
2
1
0
0
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
2
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
3
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
4
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
5
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
6
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
0
7
Write to RAM
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
8
Status/Control
No
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
Instruction
Read Command
No
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
A
A
A
1
1
1
0
Instruction
RAM EEPROM
Unlock (1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Instruction
RAM EEPROM
Lock
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
(1)
20
CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can
only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed
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The CDCE18005 on-board EEPROM has been factory preset to the default settings listed in the table below.
REGISTER
DEFAULT SETTING
REG0000
8140000
REG0001
8140000
REG0002
8140000
REG0003
8140000
REG0004
8140000
REG0005
0000096
REG0006
0000000
REG0007
9400000
REG0008 (RAM)
8000580
The default configurations programmed in the device is set to: PRI_REF (set to LVPECL) feeding all outputs.
Output dividers are set to DIVIDE by 1. All output dividers are set to LVPECL
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Writing to the CDCE18005
Figure 18 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit
0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE18005,
data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE18005 that
the transmission of the last bit in the stream (Bit 31) has occurred.
SPI_CLK
SPI_MOSI
Bit0
Bit1
Bit29
Bit30
Bit31
SPI_LE
Figure 18. CDCE18005 SPI Write Operation
Reading from the CDCE18005
Figure 19 shows how the CDCE18005 executes a Read Command. The SPI master first issues a Read
Command to initiate a data transfer from the CDCE18005 back to the host (see Table 6). This command
specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE18005
resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the
CDCE18005 presents the data present in the register specified in the Read Command on SPI_MISO.
SPI_ CLK
SPI_ MOSI
Bit30
SPI_ MISO
Bit31
Bit0
Bit1
Bit2
SPI_LE
Figure 19. CDCE18005 Read Operation
Writing to EEPROM
After the CDCE18005 detects a power-up and completes a reset cycle, it copies the contents of the on-board
EEPROM into the Device Registers. Therefore, the CDCE18005 initializes into a known state pre-defined by the
user. The host issues one of two special commands shown in Table 6 to copy the contents of Device Registers 0
through 7 (a total of 184 bits) into EERPOM. They include:
• Copy RAM to EEPROM – Unlock, Execution of this command can happen many times.
• Copy RAM to EEPROM – Lock: Execution of this command can happen only once; after which the EEPROM
is permanently locked.
After either command is initiated, power must remain stable and the host must not access the CDCE18005 for at
least 50 ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption.
22
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Device Registers: Register 0
Table 4. CDCE18005 Register 0 Bit Definitions
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
0
4
0
RESERVED
5
1
RESERVED
6
2
RESERVED
7
3
RESERVED
8
4
OUTMUX0SELX
Output 0
9
5
OUTMUX0SELY
Output 0
10
6
PH0ADJC0
Output 0
EEPROM
11
7
PH0ADJC1
Output 0
EEPROM
12
8
PH0ADJC2
Output 0
13
9
PH0ADJC3
Output 0
14
10
PH0ADJC4
Output 0
EEPROM
15
11
PH0ADJC5
Output 0
EEPROM
16
12
PH0ADJC6
Output 0
EEPROM
17
13
OUT0DIVRSEL0
Output 0
EEPROM
18
14
OUT0DIVRSEL1
Output 0
EEPROM
19
15
OUT0DIVRSEL2
Output 0
20
16
OUT0DIVRSEL3
Output 0
21
17
OUT0DIVRSEL4
Output 0
EEPROM
22
18
OUT0DIVRSEL5
Output 0
EEPROM
23
19
OUT0DIVRSEL6
Output 0
24
20
OUT0DIVSEL
EEPROM
EEPROM
EEPROM
EEPROM
Coarse phase adjust select for output divider “0”
EEPROM
EEPROM
OUTPUT DIVIDER “0” Ratio Select
EEPROM
EEPROM
Output 0
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
EEPROM
HiSWINGLVPECL0
Output 0
26
22
CMOSMODE0PX
Output 0
27
23
CMOSMODE0PY
Output 0
28
24
CMOSMODE0NX
Output 0
29
25
CMOSMODE0NY
Output 0
30
26
OUTBUFSEL0X
Output 0
OUTBUFSEL0Y
OUTPUT MUX “0” Select. Selects the Signal driving Output Divider ”0”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:Reserved
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
21
27
EEPROM
EEPROM
25
31
EEPROM
Always Set to "0" for Proper Operation
Output 0
LVCMOS mode select for OUTPUT “0” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
LVCMOS mode select for OUTPUT “0” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
OUTPUT TYPE
EEPROM
EEPROM
RAM BITS
EEPROM
22
23
24
25
26
27
LVPECL
0
0
0
0
0
1
LVDS
0
1
0
1
1
1
LVCMOS
See Settings Above*
0
0
Output Disabled
0
1
0
1
0
1
EEPROM
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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Device Registers: Register 1
Table 5. CDCE18005 Register 1 Bit Definitions
SPI
BIT
RA
M
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
0
4
0
RESERVED
5
1
RESERVED
6
2
RESERVED
7
3
RESERVED
8
4
OUTMUX1SELX
Output 1
9
5
OUTMUX1SELY
Output 1
10
6
PH1ADJC0
Output 1
EEPROM
11
7
PH1ADJC1
Output 1
EEPROM
12
8
PH1ADJC2
Output 1
13
9
PH1ADJC3
Output 1
14
10
PH1ADJC4
Output 1
EEPROM
15
11
PH1ADJC5
Output 1
EEPROM
16
12
PH1ADJC6
Output 1
EEPROM
17
13
OUT1DIVRSEL0
Output 1
EEPROM
18
14
OUT1DIVRSEL1
Output 1
EEPROM
19
15
OUT1DIVRSEL2
Output 1
20
16
OUT1DIVRSEL3
Output 1
21
17
OUT1DIVRSEL4
Output 1
EEPROM
22
18
OUT1DIVRSEL5
Output 1
EEPROM
23
19
OUT1DIVRSEL6
Output 1
24
20
OUT1DIVSEL
EEPROM
EEPROM
EEPROM
EEPROM
Coarse phase adjust select for output divider “1”
EEPROM
EEPROM
OUTPUT DIVIDER “1” Ratio Select
EEPROM
EEPROM
Output 1
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
EEPROM
HiSWINGLVPECL1
Output 1
26
22
CMOSMODE1PX
Output 1
27
23
CMOSMODE1PY
Output 1
28
24
CMOSMODE1NX
Output 1
29
25
CMOSMODE1NY
Output 1
30
26
OUTBUFSEL1X
Output 1
OUTBUFSEL1Y
OUTPUT MUX “1” Select. Selects the Signal driving Output Divider ”1”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:Reserved
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
21
27
EEPROM
EEPROM
25
31
EEPROM
Always St "0" for Proper Operation
Output 1
LVCMOS mode select for OUTPUT “1” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
LVCMOS mode select for OUTPUT “1” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
OUTPUT TYPE
EEPROM
EEPROM
RAM BITS
EEPROM
22
23
24
25
26
27
LVPECL
0
0
0
0
0
1
LVDS
0
1
0
1
1
1
LVCMOS
See Settings Above*
0
0
Output Disabled
0
1
0
1
0
1
EEPROM
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
24
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Device Registers: Register 2
Table 6. CDCE18005 Register 2 Bit Definitions
SPI
BIT
RA
M
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
0
4
0
RESERVED
5
1
RESERVED
6
2
RESERVED
7
3
RESERVED
8
4
OUTMUX2SELX
Output 2
9
5
OUTMUX2SELY
Output 2
10
6
PH2ADJC0
Output 2
EEPROM
11
7
PH2ADJC1
Output 2
EEPROM
12
8
PH2ADJC2
Output 2
13
9
PH2ADJC3
Output 2
14
10
PH2ADJC4
Output 2
EEPROM
15
11
PH2ADJC5
Output 2
EEPROM
16
12
PH2ADJC6
Output 2
EEPROM
17
13
OUT2DIVRSEL0
Output 2
EEPROM
18
14
OUT2DIVRSEL1
Output 2
EEPROM
19
15
OUT2DIVRSEL2
Output 2
20
16
OUT2DIVRSEL3
Output 2
21
17
OUT2DIVRSEL4
Output 2
EEPROM
22
18
OUT2DIVRSEL5
Output 2
EEPROM
23
19
OUT2DIVRSEL6
Output 2
24
20
OUT2DIVSEL
EEPROM
EEPROM
EEPROM
EEPROM
Coarse phase adjust select for output divider “2”
EEPROM
EEPROM
OUTPUT DIVIDER “2” Ratio Select
EEPROM
EEPROM
Output 2
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
EEPROM
HiSWINGLVPEC2
Output 2
26
22
CMOSMODE2PX
Output 2
27
23
CMOSMODE2PY
Output 2
28
24
CMOSMODE2NX
Output 2
29
25
CMOSMODE2NY
Output 2
30
26
OUTBUFSEL2X
Output 2
OUTBUFSEL2Y
OUTPUT MUX “2” Select. Selects the Signal driving Output Divider ”2”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:Reserved
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
21
27
EEPROM
EEPROM
25
31
EEPROM
Always Set to "0" for Proper Operation
LVCMOS mode select for OUTPUT “2” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
LVCMOS mode select for OUTPUT “2” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
Output 2
OUTPUT TYPE
EEPROM
EEPROM
RAM BITS
EEPROM
22
23
24
25
26
27
LVPECL
0
0
0
0
0
1
LVDS
0
1
0
1
1
1
0
0
1
0
LVCMOS
Output Disabled
See Settings Above*
0
1
0
1
EEPROM
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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Device Registers: Register 3
Table 7. CDCE18005 Register 3 Bit Definitions
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
0
4
0
RESERVED
5
1
RESERVED
6
2
RESERVED
7
3
RESERVED
8
4
OUTMUX3SELX
Output 3
9
5
OUTMUX3SELY
Output 3
10
6
PH3ADJC0
Output 3
EEPROM
11
7
PH3ADJC1
Output 3
EEPROM
12
8
PH3ADJC2
Output 3
13
9
PH3ADJC3
Output 3
14
10
PH3ADJC4
Output 3
EEPROM
15
11
PH3ADJC5
Output 3
EEPROM
16
12
PH3ADJC6
Output 3
EEPROM
17
13
OUT3DIVRSEL0
Output 3
EEPROM
18
14
OUT3DIVRSEL1
Output 3
EEPROM
19
15
OUT3DIVRSEL2
Output 3
20
16
OUT3DIVRSEL3
Output 3
21
17
OUT3DIVRSEL4
Output 3
EEPROM
22
18
OUT3DIVRSEL5
Output 3
EEPROM
23
19
OUT3DIVRSEL6
Output 3
24
20
OUT3DIVSEL
EEPROM
EEPROM
EEPROM
EEPROM
Coarse phase adjust select for output divider “3”
EEPROM
EEPROM
OUTPUT DIVIDER “3” Ratio Select
EEPROM
EEPROM
Output 3
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
EEPROM
HiSWINGLVPEC3
Output 3
26
22
CMOSMODE3PX
Output 3
27
23
CMOSMODE3PY
Output 3
28
24
CMOSMODE3NX
Output 3
29
25
CMOSMODE3NY
Output 3
30
26
OUTBUFSEL3X
Output 3
OUTBUFSEL3Y
OUTPUT MUX “3” Select. Selects the Signal driving Output Divider ”3”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:Reserved
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
21
27
EEPROM
EEPROM
25
31
EEPROM
Always Set to "0" for Proper Operation
Output 3
LVCMOS mode select for OUTPUT “3” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
LVCMOS mode select for OUTPUT “3” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
OUTPUT TYPE
EEPROM
EEPROM
RAM BITS
EEPROM
22
23
24
25
26
27
LVPECL
0
0
0
0
0
1
LVDS
0
1
0
1
1
1
0
0
1
0
LVCMOS
Output Disabled
See Settings Above*
0
1
0
1
EEPROM
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
26
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Device Registers: Register 4
Table 8. CDCE18005 Register 4 Bit Definitions
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
0
4
0
RESERVED
5
1
RESERVED
6
2
RESERVED
7
3
RESERVED
8
4
OUTMUX4SELX
Output 4
9
5
OUTMUX4SELY
Output 4
10
6
PH4ADJC0
Output 4
EEPROM
11
7
PH4ADJC1
Output 4
EEPROM
12
8
PH4ADJC2
Output 4
13
9
PH4ADJC3
Output 4
14
10
PH4ADJC4
Output 4
EEPROM
15
11
PH4ADJC5
Output 4
EEPROM
16
12
PH4ADJC6
Output 4
EEPROM
17
13
OUT4DIVRSEL0
Output 4
EEPROM
18
14
OUT4DIVRSEL1
Output 4
EEPROM
19
15
OUT4DIVRSEL2
Output 4
20
16
OUT4DIVRSEL3
Output 4
21
17
OUT4DIVRSEL4
Output 4
EEPROM
22
18
OUT4DIVRSEL5
Output 4
EEPROM
23
19
OUT4DIVRSEL6
Output 4
24
20
OUT4DIVSEL
EEPROM
EEPROM
EEPROM
EEPROM
Coarse phase adjust select for output divider “4”
EEPROM
EEPROM
OUTPUT DIVIDER “4” Ratio Select
EEPROM
EEPROM
Output 4
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
EEPROM
HiSWINGLVPEC4
Output 4
26
22
CMOSMODE4PX
Output 4
27
23
CMOSMODE4PY
Output 4
28
24
CMOSMODE4NX
Output 4
29
25
CMOSMODE4NY
Output 4
30
26
OUTBUFSEL4X
Output 4
OUTBUFSEL4Y
OUTPUT MUX “4” Select. Selects the Signal driving Output Divider ”4”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:Reserved
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
21
27
EEPROM
EEPROM
25
31
EEPROM
Must be set to "0" for proper operation
Output 4
LVCMOS mode select for OUTPUT “4” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
LVCMOS mode select for OUTPUT “3” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
OUTPUT TYPE
EEPROM
EEPROM
RAM BITS
EEPROM
22
23
24
25
26
27
LVPECL
0
0
0
0
0
1
LVDS
0
1
0
1
1
1
0
0
1
0
LVCMOS
Output Disabled
See Settings Above*
0
1
0
1
EEPROM
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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Device Registers: Register 5
Table 9. CDCE18005 Register 5 Bit Definitions
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
4
0
INBUFSELX
INBUFSELX
5
1
INBUFSELY
INBUFSELY
6
2
SYNCSEL1
7
3
SYNCSEL2
Output
Divider
Synchronizati
on
8
4
9
5
10
6
ACDCSEL
0
Input Buffer Select (LVPECL,LVDS or LVCMOS)
XY(01 ) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin
EEPROM
SYNCSEL(1,2)= 10 :Output divider sync to Primary input
SYNCSEL(1,2)= 01 :Output divider sync to Secondary input
SYNCSEL(1,2)= 00 :Output divider sync to Auxiliary input
EEPROM
RESERVED
Always Set to "1" for Proper Operation
EEPROM
RESERVED
Always Set to "0" for Proper Operation
EEPROM
Input Buffers
If Set to “1” DC Termination, If set to “0” AC Termination
EEPROM
EEPROM
EEPROM
EEPROM
11
7
HYSTEN
Input Buffers
If Set to “1” Input Buffers Hysteresis Enabled. It is not recommended that Hysteresis be
disabled.
12
8
PRI_TERMSEL
Input Buffers
If Set to “0” Primary Input Buffer Internal Termination Enabled
If set to “1” Primary Internal Termination circuitry Disabled
EEPROM
13
9
PRIINVBB
Input Buffers
If Set to “1” Primary Input Negative Pin Biased with Internal VBB Voltage.
EEPROM
14
10
SECINVBB
Input Buffers
If Set to “1” Secondary Input Negative Pin Biased with Internal VBB Voltage
EEPROM
Input Buffers
If Set to “1” Fail Safe is Enabled for all Input Buffers configured as LVDS, DC Coupling
only.
EEPROM
15
11
FAILSAFE
16
12
RESERVED
EEPROM
17
13
RESERVED
EEPROM
18
14
RESERVED
EEPROM
19
15
RESERVED
EEPROM
20
16
RESERVED
EEPROM
21
17
RESERVED
EEPROM
22
18
RESERVED
EEPROM
23
19
RESERVED
24
20
RESERVED
25
21
RESERVED
EEPROM
26
22
RESERVED
EEPROM
27
23
RESERVED
EEPROM
28
24
RESERVED
EEPROM
29
25
RESERVED
EEPROM
30
26
RESERVED
EEPROM
31
27
RESERVED
EEPROM
28
----
Must be set to "0" for proper operation
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EEPROM
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Device Registers: Register 6
Table 10. CDCE18005 Register 6 Bit Definitions
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
1
3
A3
Address 3
0
4
0
RESERVED
EEPROM
5
1
RESERVED
EEPROM
6
2
RESERVED
EEPROM
7
3
RESERVED
EEPROM
8
4
RESERVED
EEPROM
9
5
RESERVED
10
6
RESERVED
11
7
RESERVED
EEPROM
12
8
RESERVED
EEPROM
13
9
RESERVED
EEPROM
14
10
RESERVED
EEPROM
15
11
RESERVED
EEPROM
Must be set to "0"
EEPROM
EEPROM
Input Buffers
If Set to “0” Secondary Input Buffer Internal Termination Enabled
If set to “1” Secondary Internal Termination circuitry Disabled
16
12
SEC_TERMSEL
EEPROM
17
13
RESERVED
EEPROM
18
14
RESERVED
EEPROM
19
15
RESERVED
EEPROM
20
16
RESERVED
EEPROM
21
17
RESERVED
22
18
RESERVED
23
19
RESERVED
EEPROM
24
20
RESERVED
EEPROM
25
21
RESERVED
EEPROM
26
22
RESERVED
EEPROM
27
23
RESERVED
28
24
AUXOUTEN
Output AUX
Enable Auxiliary Output when set to “1”
EEPROM
29
25
AUXFEEDSEL
Output AUX
Select the Output that will driving the AUX Output;
Low for Selecting Output Divider “2” and High for Selecting Output Divider “3”
EEPROM
30
26
RESERVED
Must be set to "0"
EEPROM
31
27
RESERVED
Must be set to "0"
EEPROM
EEPROM
Must be set to "0"
EEPROM
EEPROM
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Device Registers: Register 7
Table 11. CDCE18005 Register 7 Bit Definitions
SPI
BIT
RAM BIT NAME
BIT
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
1
3
A3
Address 3
0
4
0
RESERVED
EEPROM
5
1
RESERVED
EEPROM
6
2
RESERVED
EEPROM
7
3
RESERVED
EEPROM
8
4
RESERVED
EEPROM
9
5
RESERVED
EEPROM
10
6
RESERVED
EEPROM
11
7
RESERVED
EEPROM
12
8
RESERVED
EEPROM
13
9
RESERVED
EEPROM
14
10
RESERVED
15
11
RESERVED
16
12
RESERVED
EEPROM
17
13
RESERVED
EEPROM
18
14
RESERVED
EEPROM
19
15
RESERVED
EEPROM
20
16
RESERVED
EEPROM
21
17
RESERVED
EEPROM
22
18
RESERVED
EEPROM
23
19
RESERVED
EEPROM
24
20
RESERVED
EEPROM
25
21
RESERVED
26
22
TESTMUX1
27
23
RESERVED
28
24
TEXTMUX2
29
25
RESERVED
30
26
EPUNLOCK
Status
EEPROM Unlock
RAM
31
27
EPSTATUS
Status
EEPROM Status
RAM
30
Always Set to "0" for Proper Operation
EEPROM
EEPROM
EEPROM
Diagnostics Set to “1”
Always Set to "0" for Proper Operation
Diagnostics Set to “1”
Always Set to "0" for Proper Operation
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EEPROM
EEPROM
EEPROM
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Device Registers: Register 8
Table 12. CDCE18005 Register 8 Bit Definitions
SPI
BIT
RAM BIT NAME
BIT
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
1
4
0
RESERVED
RAM
5
1
RESERVED
RAM
6
2
RESERVED
RAM
7
3
RESERVED
8
4
RESERVED
RAM
9
5
RESERVED
RAM
10
6
RESERVED
11
7
SLEEP
12
TI Test Registers. For TI Use Only
RAM
RAM
Status
Set Device Sleep mode On when set to “0”, Normal Mode when set to “1”
RAM
Status
If set to “0” this bit forces “/SYNC ; Set to “1” to exit the Synchronization
State.
RAM
8
SYNC
13
9
RESERVED
14
10
VERSION0
Tie off
Silicon Revision
RAM
15
11
VERSION1
Tie off
Silicon Revision
RAM
16
12
VERSION2
Tie off
Silicon Revision
RAM
17
13
RESERVED
RAM
18
14
RESERVED
RAM
19
15
RESERVED
RAM
20
16
RESERVED
RAM
21
17
RESERVED
RAM
22
18
RESERVED
RAM
23
19
RESERVED
24
20
RESERVED
25
21
RESERVED
RAM
26
22
RESERVED
RAM
27
23
RESERVED
RAM
28
24
RESERVED
RAM
29
25
RESERVED
RAM
30
26
RESERVED
RAM
31
27
RESERVED
RAM
RAM
RAM
TI Test Registers. For TI Use Only
RAM
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Device Control
Figure 20 provides a conceptual explanation of the CDCE18005 Device operation. Table 13 defines how the
device behaves in each of the operational states.
Device
OFF
Power
Applied
Power ON
Reset
Sleep
Sleep = OFF
Power Down = OFF
Power Down = ON
Delay Finished
Sleep = ON
Sync = ON
Power Down = ON
Power Down
Sync
Active Mode
Sync = OFF
Figure 20. CDCE18005 Device State Control Diagram
Table 13. CDCE18005 Device State Definitions
Status
State
Device Behavior
Power-On
Reset
After device power supply reaches
approximately 2.35V, the contents of
EEPROM are copied into the Device
Registers, thereby initializing the device
hardware .
Active Mode
Normal Operation
Entered Via
Exited Via
SPI Port
Output
Divider
Output
Buffer
Power applied to the device or upon exit
from Power Down State via the
Power_Down pin set HIGH.
Power On Reset and EEPROM loading
delays are finished OR the Power_Down pin
is set LOW.
OFF
Disabled
OFF
Sync = OFF (from Sync State).
Sync, Power Down, Sleep, or Manual
Recalibration activated.
ON
Disabled
or Enabled
Disabled or
Enabled
Power_Down pin is pulled LOW.
Power_Down pin is pulled HIGH.
ON
Disabled
Disabled
Power Down
Used to shut down all hardware and
Resets the device after exiting the
Power Down State. Therefore, the
EEPROM contents will eventually be
copied into RAM after the Power Down
State is exited.
Identical to the Power Down State
except the EEPROM contents are not
copied into RAM.
SLEEP bit in device register 8 bit 7 is set
LOW.
SLEEP bit in device register 8 bit 7 is set
HIGH.
ON
Disabled
Disabled
Sleep
32
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Table 13. CDCE18005 Device State Definitions (continued)
Status
State
Sync
Device Behavior
Sync synchronizes all output dividers
so that they begin counting at the same
time. Note: this operation is performed
automatically each time a divider
register is accessed.
Entered Via
SYNC Bit in device register 8 bit 8 is set
LOW or SYNC pin is pulled LOW
Exited Via
SYNC Bit in device register 8 bit 8 is set
HIGH or SYNC pin is pulled HIGH
SPI Port
Output
Divider
Output
Buffer
ON
Disabled
Disabled
External Control Pins
Power_Down
The Power_Down pin places the CDCE18005 into the power down state. Additionally, the CDCE18005 loads the
contents of the EEPROM into RAM after the Power_Down pin is de-asserted; therefore, it is used to initialize the
device after power is applied. SPI_LE signal has to be HIGH in order for EEPROM to load correctly during the
rising edge of Power_Down.
SYNC
The SYNC pin (Active LOW) has a complementary register location located in Device Register 8 bit 8. When
enabled, Sync synchronizes all output dividers so that they begin counting simultaneously. Further, SYNC
disables all outputs when in the active. State.
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INPUT BLOCK
The Input Block includes two Universal Input Buffers, an Auxiliary Input. The Input Block drives three different
clock signals onto the Internal Clock Distribution Bus.
Internal Clock Distribution Bus
1500 MHz
PRI_IN
LVPECL : 1500 MHz
LVDS : 800 MHz
LVCMOS : 250 MHz
1500 MHz
SEC_IN
Crystal : 2 MHz – 42 MHz
Single Ended : 2 MHz to 75 MHz
XTAL /
AUX_IN
Figure 21. CDCE18005 Input Block With References to Registers
Universal Input Buffers (UIB)
Figure 22 shows the key elements of a universal input buffer. A UIB supports multiple formats along with different
termination and coupling schemes. The CDCE18005 implements the UIB by including on board switched
termination, a programmable bias voltage generator, and an output multiplexer. The CDCE18005 provides a high
degree of configurability on the UIB to facilitate most existing clock input formats.
PRI_IN
PINV
PN
PP
50 Ω
50 Ω
50 Ω
50 Ω
SN
SP
Register 6
12
Vbb
1 mF
Settings
5.1
5.0
5.6
Nominal
INBUFSELY INBUFSELX ACDCSEL
Vbb
1
0
0
1.9V
1
0
1
1.2V
1
1
0
1.2V
1
1
1
1.2V
Universal Input Control
Vbb
Register 5
10 9 8
7
6
1
0
SINV
5.0
INBUFSELX
0
X
X
X
SEC_IN
Settings
5.1
5.8, 6.12
INBUFSELY
TERMSEL
0
X
X
1
1
0
1
0
SWITCH Status
5.9,5.10
INVBB
X
X
0
1
P
OFF
OFF
ON
ON
N
OFF
OFF
ON
ON
INV
OFF
OFF
ON
OFF
Figure 22. CDCE18005 Universal Input Buffer
34
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Table 14 lists several settings for many possible clock input scenarios. Note that the two universal input buffers
share the Vbb generator. Therefore, if both inputs use internal termination, they must use the same configuration
mode (LVDS, LVPECL, or LVCMOS). If the application requires different modes (e.g. LVDS and LVPECL) then
one of the two inputs must implement external termination.
Table 14. CDCE18005 Universal Input Buffer Configuration Matrix
PRI_IN CONFIGURATION MATRIX
SETTINGS
Register.Bit →
Bit Name →
CONFIGURATION
5.7
5.1
5.0
5.8
5.9
5.6
HYSTEN
INBUFSELY
INBUFSELX
PRI_TERMSEL
PRIINVBB
ACDCSEL
Hysteresis
Mode
Coupling
Termination
1
0
0
X
X
X
ENABLED
LVCMOS
DC
N/A
—
1
1
0
0
0
0
ENABLED
LVPECL
AC
Internal
1.9V
1
1
0
0
0
1
ENABLED
LVPECL
DC
Internal
1.2V
1
1
0
1
X
X
ENABLED
LVPECL
—
External
—
1
1
1
0
0
0
ENABLED
LVDS
AC
Internal
1.2V
1
1
1
0
0
1
ENABLED
LVDS
DC
Internal
1.2V
1
1
1
1
X
X
ENABLED
LVDS
—
External
—
0
X
X
X
X
X
OFF
—
—
—
—
1
X
X
X
X
X
ENABLED
—
—
—
—
5.7
5.1
5.0
6.12
5.10
5.6
HYSTEN
INBUFSELY
INBUFSELX
SEC_TERMSEL
SECINVBB
ACDCSEL
Hysteresis
Mode
Coupling
Termination
Vbb
1
0
0
X
X
X
ENABLED
LVCMOS
DC
N/A
—
1
1
0
0
0
0
ENABLED
LVPECL
AC
Internal
1.9V
1
1
0
0
0
1
ENABLED
LVPECL
DC
Internal
1.2V
1
1
0
1
X
X
ENABLED
LVPECL
—
External
—
1
1
1
0
0
0
ENABLED
LVDS
AC
Internal
1.2V
1
1
1
0
0
1
ENABLED
LVDS
DC
Internal
1.2V
1
1
1
1
X
X
ENABLED
LVDS
—
External
—
0
X
X
X
X
X
OFF
—
—
—
—
1
X
X
X
X
X
ENABLED
—
—
—
—
Vbb
SEC_IN CONFIGURATION MATRIX
SETTINGS
Register.Bit →
Bit Name →
CONFIGURATION
LVDS Fail Safe Mode
Differential data line receivers can switch on noise in the absence of an input signal. This occurs when the bus
driver is turned off or the interconnect is damaged or missing. Traditionally the solution to this problem involves
incorporating an external resistor network on the receiver input. This network applies a steady-state bias voltage
to the input pins. The additional cost of the external components notwithstanding, the use of such a network
lowers input signal magnitude and thus reduces the differential noise margin. The CDCE18005 provides internal
failsafe circuitry on all LVDS inputs if enabled as shown in Table 15 for DC termination only.
Table 15. LVDS Failsafe Settings
Bit Name →
Register.Bit →
FAILSAFE
5.11
LVDS Failsafe
0
Disabled for all inputs
1
Enabled for all inputs
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Auxiliary Input Port
The auxiliary input on the CDCE18005 is designed to connect to an AT-Cut Crystal with a total load capacitance
(CL) of 0 to 10 pF. One side of the crystal connects to Ground while the other side connects to the Auxiliary input
of the device. The circuit works optimally between 20 to 40 MHz but it can accept crystals from 2 to 42 MHz.
Since the Auxiliary input operates between 0 and 2 V with a crystal, it can accept single-ended signals (e.g.
LVCMOS). Electrically, it is equivalent to an LVCMOS input buffer with 10 pF of input capacitance.
8 pF
CL
Figure 23. CDCE18005 Auxiliary Input Port
OUTPUT BLOCK
The output block includes five identical output channels. Each output channel comprises an output multiplexer, a
clock divider module, and a universal output buffer as shown in Figure 24.
Registers 0 - 4
5
4
Output
MUX
Control
Internal Clock Distribution Bus
Registers 0 - 4
27 26 25 24 23 22 21
Sync
Pulse
Output Buffer Control
Enable
PRI_IN
UxP
SEC_IN
SMART _MUX
Clock Divider Module 0 - 4
LVDS
UxN
SYNTH
LVPECL
Figure 24. CDCE18005 Output Channel
36
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Output Multiplexer Control
The output multiplexer selects which of the four clock sources available on the Internal Clock Distribution Bus will
be presented to the Clock Divider Module. For a description of these clock sources, see Figure 21.
Table 16. CDCE18005 Output Multiplexer Control Settings
OUTPUT MULTIPLEXER CONTROL
Register n (n = 0,1,2,3,4)
OUTMUXnSELX
n.4
OUTMUXnSELY
n.5
CLOCK SOURCE SELECTED
0
0
PRI_IN
0
1
SEC_IN
1
0
AUX_IN
1
1
Reserved
Output Buffer Control
Each of the five output channels includes a programmable output buffer; supporting LVPECL, LVDS, and
LVCMOS modes. Table 17 lists the settings required to configure the CDCE18005 for each output type.
Registers 0 through 4 correspond to Output Channels 0 through 4 respectively.
Table 17. CDCE18005 Output Buffer Control Settings
OUTPUT BUFFER CONTROL
Register n (n = 0,1,2,3,4)
OUTPUT TYPE
CMOSMODEnPX
CMOSMODEnPY
CMOSMODEnNX
CMOSMODEnNY
OUTBUFSELnX
OUTBUFSELnY
n.22
n.23
n.24
n.25
n.26
n.27
0
0
0
0
0
1
0
1
0
1
1
1
LVDS
0
0
LVCMOS
1
0
OFF
See LVCMOS Output Buffer Configuration Settings
0
1
0
1
LVPECL
Output Buffer Control – LVCMOS Configurations
A LVCMOS output configuration requires additional configuration data. In the single ended configuration, each
Output Channel provides a pair of outputs. The CDCE18005 supports four modes of operation for single ended
outputs as listed in Table 18.
Table 18. LVCMOS Output Buffer Configuration Settings
OUTPUT BUFFER CONTROL – LVCMOS CONFIGURATION
Register n (n = 0,1,2,3,4)
Output
Type
Pin
0
LVCMOS
Negative
Active – Non-inverted
0
LVCMOS
Negative
Hi-Z
0
0
LVCMOS
Negative
Active – Non-inverted
1
0
0
LVCMOS
Negative
Low
X
X
0
0
LVCMOS
Positive
Active – Non-inverted
1
X
X
0
0
LVCMOS
Positive
Hi-Z
1
0
X
X
0
0
LVCMOS
Positive
Active – Non-inverted
1
1
X
X
0
0
LVCMOS
Positive
Low
CMOSMODEnPX
CMOSMODEnPY
CMOSMODEnNX
CMOSMODEnNY
OUTBUFSELnX
OUTBUFSELnY
n.22
n.23
n.24
n.25
n.26
n.27
X
X
0
0
0
X
X
0
1
0
X
X
1
0
X
X
1
0
0
0
Output Mode
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Output Dividers
Figure 25 shows that each output channel provides a 7-bit divider and digital phase adjust block. Table 19 lists
the divide ratios supported by the output divider for each output channel. The output divider’s maximum input
frequency is limited to 1.175GHz. If the divider is bypassed (divide ratio = 1) then the maximum frequency of the
output channel is 1.5GHz.
Registers 0 - 4
Register 5
3
12 11 10 9
2
8
7
6
Select
Divider
Sync
PRI_IN
SEC_IN
AUX_IN
From
Output
MUX
Digital Phase Adjust (7-bits)
To
Output
Buffer
Output Divider (7-bits)
Registers 0 - 4
19 18 17 16 15 14 13
Figure 25. CDCE18005 Output Divider and Phase Adjust
38
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Table19. CDCE18005 Output Divider Settings
OUTPUT DIVIDER n SETTINGSRegister n (n = 0,1,2,3,4)
Output Phase*
n.19
n.18
n.17
n.16
n.15
X
X
X
X
X
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
Integer Divider Setting
OUTnDIVSEL2
OUTnDIVSEL3
Integer Divider
OUTnDIVSEL4
OUTnDIVSEL5
OUTnDIVSEL6
Multiplexer
Output Divide Ratio
Output
Channels
Auxiliary
Cycles
Degree
0-4
Output
OFF
OFF
OFF
OFF
–
0
0
1
4
0
–
0.5
180
2**
4
0
–
0
0
3**
6
0
0
–
0.5
180
4
8
0
0
0
–
0
0
5
10
0
0
0
0
2
21
7560
6
6
0
0
0
0
2
28.5
10260
8
8
0
0
0
0
0
2
35
12500
10
10
0
0
0
0
1
4
24
8640
12
12
0
0
0
0
1
4
32.5
11700
16
16
0
0
0
0
1
4
40
14400
20
20
0
0
0
1
0
6
27
9720
18
18
0
0
0
1
0
6
36.5
13140
24
24
0
0
0
1
0
6
45
16200
30
30
0
0
0
1
1
8
40.5
14580
32
32
0
0
0
1
1
8
50
18000
40
40
0
0
1
0
0
10
55
19800
50
50
0
0
1
0
1
12
36
12960
36
36
0
0
1
0
1
12
48.5
17460
48
48
0
0
1
0
1
12
60
21600
60
60
0
0
1
1
0
14
25.5
9540
28
28
0
0
1
1
0
14
39
14040
42
42
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OUTPUT DIVIDER n SETTINGSRegister n (n = 0,1,2,3,4)
Output Phase*
n.19
n.18
n.17
n.16
n.15
Integer Divider Setting
OUTnDIVSEL2
OUTnDIVSEL3
Integer Divider
OUTnDIVSEL4
OUTnDIVSEL5
OUTnDIVSEL6
Multiplexer
Output Divide Ratio
Cycles
Degree
0-4
Output
0
0
1
1
0
14
52.5
18900
56
56
0
0
1
1
0
14
65
23400
70
70
0
0
1
1
1
16
56.5
20340
64
64
0
0
1
1
1
16
70
25200
80
80
Output
Channels
Auxiliary
*These columns show that the output divider generates a unique phase lag in the output clock (relative to the clock from the output multiplexer) determined by the
divide ratio used.
**Output channel 2 or 3 determine the auxiliary output divide ratio. For example, if the auxiliary output is programmed to drive via output 2 and output 2 divider is
programmed to divide by 3, then the divide ratio for the auxiliary output will be 6.
40
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Digital Phase Adjust
Figure 26 provides an overview of the Digital Phase Adjust feature. The output divider includes a coarse phase
adjust that shifts the divided clock signal that drives the output buffer. Essentially, the Digital Phase Adjust timer
delays when the output divider starts dividing; thereby shifting the phase of the output clock. The phase adjust
resolution is a function of the divide function. Coarse phase adjust parameters include:
• Number of Phase Delay Steps – the number of phase delay steps available is equal to the divide ratio
selected. For example, if a Divide by 4 is selected, then the Digital Phase Adjust can be programmed to
select when the output divider changes state based upon selecting one of the four counts on the input.
Figure 26 shows an example of divide by 16 in which there are 16 rising edges of Clock IN at which the
output divider changes state (this particular example shows the fourth edge shifting the output by one fourth
of the period of the output).
• Phase Delay Step Size – the step size is determined by the number of phase delay steps according to the
following equations:
360 degrees
Stepsize(deg) =
OutputDivideRatio
(1)
1
f ClockIN
Stepsize (sec ) =
OutputDivideRatio
Clock
IN
(from Smart MUX )
(2)
Digital Phase Adjust (7-bits)
Start Divider
To Output Buffer
/1 - /80
Clock IN
Output Divider (no adjust )
Output Divider (phase adjust )
Figure 26. CDCE18005 Phase Adjust
Phase Adjust example
Given:
Output Frequency: 30.72 MHz
Input Frequency: 491.52 MHz
Output Divider Setting: 16
360
Stepsize(deg) =
= 11.25° / Step
32
(3)
The tables that follow provide a list of valid register settings for the digital phase adjust blocks.
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42
18
20
24
Phase Delay
(radian)
0
0
(2π/2)
0
(2π/3)
2(2π/3)
0
(2π/4)
2(2π/4)
3(2π/4)
0
(2π/5)
2(2π/5)
3(2π/5)
4(2π/5)
0
(2π/6)
2(2π/6)
3(2π/6)
4(2π/6)
5(2π/6)
0
(2π/8)
2(2π/8)
3(2π/8)
4(2π/8)
5(2π/8)
6(2π/8)
7(2π/8)
0
(2π/10)
2(2π/10)
3(2π/10)
4(2π/10)
5(2π/10)
6(2π/10)
7(2π/10)
8(2π/10)
9(2π/10)
0
(2π/12)
2(2π/12)
3(2π/12)
4(2π/12)
5(2π/12)
6(2π/12)
7(2π/12)
8(2π/12)
9(2π/12)
10(2π/12)
11(2π/12)
0
(2π/16)
2(2π/16)
3(2π/16)
4(2π/16)
5(2π/16)
6(2π/16)
7(2π/16)
8(2π/16)
9(2π/16)
10(2π/16)
11(2π/16)
12(2π/16)
13(2π/16)
14(2π/16)
15(2π/16)
PHnADGC0
n.6
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PHnADGC1
n.7
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
PHnADGC2
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PHnADGC3
n.9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PHnADGC4
n.10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Divide Ratio
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PHnADGC5
16
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PHnADGC6
12
Phase Delay
10
PHnADGC0
8
PHnADGC1
6
PHnADGC2
5
PHnADGC3
4
PHnADGC4
3
PHnADGC5
1
2
PHnADGC6
Divide Ratio
Table 20. CDCE18005 Output Coarse Phase Adjust Settings (1)
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.11
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
n.10
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
n.9
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(radian)
0
(2π/18)
2(2π/18)
3(2π/18)
4(2π/18)
5(2π/18)
6(2π/18)
7(2π/18)
8(2π/18)
9(2π/18)
10(2π/18)
11(2π/18)
12(2π/18)
13(2π/18)
14(2π/18)
15(2π/18)
16(2π/18)
17(2π/18)
0
(2π/20)
2(2π/20)
3(2π/20)
4(2π/20)
5(2π/20)
6(2π/20)
7(2π/20)
8(2π/20)
9(2π/20)
10(2π/20)
11(2π/20)
12(2π/20)
13(2π/20)
14(2π/20)
15(2π/20)
16(2π/20)
17(2π/20)
18(2π/20)
19(2π/20)
0
(2π/24)
2(2π/24)
3(2π/24)
4(2π/24)
5(2π/24)
6(2π/24)
7(2π/24)
8(2π/24)
9(2π/24)
10(2π/24)
11(2π/24)
12(2π/24)
13(2π/24)
14(2π/24)
15(2π/24)
16(2π/24)
17(2π/24)
18(2π/24)
19(2π/24)
20(2π/24)
21(2π/24)
22(2π/24)
23(2π/24)
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CDCE18005
www.ti.com........................................................................................................................................................................................... SCAS863 – NOVEMBER 2008
32
36
Phase Delay
(radian)
0
(2π/28)
2(2π/28)
3(2π/28)
4(2π/28)
5(2π/28)
6(2π/28)
7(2π/28)
8(2π/28)
9(2π/28)
10(2π/28)
11(2π/28)
12(2π/28)
13(2π/28)
14(2π/28)
15(2π/28)
16(2π/28)
17(2π/28)
18(2π/28)
19(2π/28)
20(2π/28)
21(2π/28)
22(2π/28)
23(2π/28)
24(2π/28)
25(2π/28)
26(2π/28)
27(2π/28)
0
(2π/30)
2(2π/30)
3(2π/30)
4(2π/30)
5(2π/30)
6(2π/30)
7(2π/30)
8(2π/30)
9(2π/30)
10(2π/30)
11(2π/30)
12(2π/30)
13(2π/30)
14(2π/30)
15(2π/30)
16(2π/30)
17(2π/30)
18(2π/30)
19(2π/30)
20(2π/30)
21(2π/30)
22(2π/30)
23(2π/30)
24(2π/30)
25(2π/30)
26(2π/30)
27(2π/30)
28(2π/30)
29(2π/30)
PHnADGC0
n.6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
PHnADGC1
n.7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
PHnADGC2
Phase Delay
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
PHnADGC3
PHnADGC0
n.9
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
PHnADGC4
PHnADGC1
n.10
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
PHnADGC5
PHnADGC2
n.11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
PHnADGC6
PHnADGC3
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Divide Ratio
PHnADGC4
30
PHnADGC5
28
PHnADGC6
Divide Ratio
Table 21. CDCE18005 Output Coarse Phase Adjust Settings (2)
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
n.10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
n.9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
n.6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
(radian)
0
(2π/32)
2(2π/32)
3(2π/32)
4(2π/32)
5(2π/32)
6(2π/32)
7(2π/32)
8(2π/32)
9(2π/32)
10(2π/32)
11(2π/32)
12(2π/32)
13(2π/32)
14(2π/32)
15(2π/32)
16(2π/32)
17(2π/32)
18(2π/32)
19(2π/32)
20(2π/32)
21(2π/32)
22(2π/32)
23(2π/32)
24(2π/32)
25(2π/32)
26(2π/32)
27(2π/32)
28(2π/32)
29(2π/32)
30(2π/32)
31(2π/32)
0
(2π/36)
2(2π/36)
3(2π/36)
4(2π/36)
5(2π/36)
6(2π/36)
7(2π/36)
8(2π/36)
9(2π/36)
10(2π/36)
11(2π/36)
12(2π/36)
13(2π/36)
14(2π/36)
15(2π/36)
16(2π/36)
17(2π/36)
18(2π/36)
19(2π/36)
20(2π/36)
21(2π/36)
22(2π/36)
23(2π/36)
24(2π/36)
25(2π/36)
26(2π/36)
27(2π/36)
28(2π/36)
29(2π/36)
30(2π/36)
31(2π/36)
32(2π/36)
33(2π/36)
34(2π/36)
35(2π/36)
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Product Folder Link(s) :CDCE18005
43
CDCE18005
SCAS863 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
44
48
Phase Delay
(radian)
0
(2π/40)
2(2π/40)
3(2π/40)
4(2π/40)
5(2π/40)
6(2π/40)
7(2π/40)
8(2π/40)
9(2π/40)
10(2π/40)
11(2π/40)
12(2π/40)
13(2π/40)
14(2π/40)
15(2π/40)
16(2π/40)
17(2π/40)
18(2π/40)
19(2π/40)
20(2π/40)
21(2π/40)
22(2π/40)
23(2π/40)
24(2π/40)
25(2π/40)
26(2π/40)
27(2π/40)
28(2π/40)
29(2π/40)
30(2π/40)
31(2π/40)
32(2π/40)
33(2π/40)
34(2π/40)
35(2π/40)
36(2π/40)
37(2π/40)
38(2π/40)
39(2π/40)
0
(2π/42)
2(2π/42)
3(2π/42)
4(2π/42)
5(2π/42)
6(2π/42)
7(2π/42)
8(2π/42)
9(2π/42)
10(2π/42)
11(2π/42)
12(2π/42)
13(2π/42)
14(2π/42)
15(2π/42)
16(2π/42)
17(2π/42)
18(2π/42)
19(2π/42)
20(2π/42)
21(2π/42)
22(2π/42)
23(2π/42)
24(2π/42)
25(2π/42)
26(2π/42)
27(2π/42)
28(2π/42)
29(2π/42)
30(2π/42)
31(2π/42)
32(2π/42)
33(2π/42)
34(2π/42)
35(2π/42)
36(2π/42)
37(2π/42)
38(2π/42)
39(2π/42)
40(2π/42)
41(2π/42)
PHnADGC0
n.6
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
PHnADGC1
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
PHnADGC2
Phase Delay
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PHnADGC3
PHnADGC0
n.9
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
PHnADGC4
PHnADGC1
n.10
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
PHnADGC5
PHnADGC2
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PHnADGC6
PHnADGC3
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide Ratio
PHnADGC4
42
PHnADGC5
40
PHnADGC6
Divide Ratio
Table 22. CDCE18005 Output Coarse Phase Adjust Settings (3)
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
n.10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
n.9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(radian)
0
(2π/48)
2(2π/48)
3(2π/48)
4(2π/48)
5(2π/48)
6(2π/48)
7(2π/48)
8(2π/48)
9(2π/48)
10(2π/48)
11(2π/48)
12(2π/48)
13(2π/48)
14(2π/48)
15(2π/48)
16(2π/48)
17(2π/48)
18(2π/48)
19(2π/48)
20(2π/48)
21(2π/48)
22(2π/48)
23(2π/48)
24(2π/48)
25(2π/48)
26(2π/48)
27(2π/48)
28(2π/48)
29(2π/48)
30(2π/48)
31(2π/48)
32(2π/48)
33(2π/48)
34(2π/48)
35(2π/48)
36(2π/48)
37(2π/48)
38(2π/48)
39(2π/48)
40(2π/48)
41(2π/48)
42(2π/48)
43(2π/48)
44(2π/48)
45(2π/48)
46(2π/48)
47(2π/48)
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Product Folder Link(s) :CDCE18005
CDCE18005
www.ti.com........................................................................................................................................................................................... SCAS863 – NOVEMBER 2008
56
Phase Delay
(radian)
0
(2π/50)
2(2π/50)
3(2π/50)
4(2π/50)
5(2π/50)
6(2π/50)
7(2π/50)
8(2π/50)
9(2π/50)
10(2π/50)
11(2π/50)
12(2π/50)
13(2π/50)
14(2π/50)
15(2π/50)
16(2π/50)
17(2π/50)
18(2π/50)
19(2π/50)
20(2π/50)
21(2π/50)
22(2π/50)
23(2π/50)
24(2π/50)
25(2π/50)
26(2π/50)
27(2π/50)
28(2π/50)
29(2π/50)
30(2π/50)
31(2π/50)
32(2π/50)
33(2π/50)
34(2π/50)
35(2π/50)
36(2π/50)
37(2π/50)
38(2π/50)
39(2π/50)
40(2π/50)
41(2π/50)
42(2π/50)
43(2π/50)
44(2π/50)
45(2π/50)
46(2π/50)
47(2π/50)
48(2π/50)
49(2π/50)
PHnADGC0
n.6
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
PHnADGC1
Phase Delay
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
PHnADGC2
PHnADGC0
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
PHnADGC3
PHnADGC1
n.9
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
PHnADGC4
PHnADGC2
n.10
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
PHnADGC5
PHnADGC3
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
PHnADGC6
PHnADGC4
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide Ratio
PHnADGC5
50
PHnADGC6
Divide Ratio
Table 23. CDCE18005 Output Coarse Phase Adjust Settings (4)
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
n.10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
n.9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(radian)
0
(2π/56)
2(2π/56)
3(2π/56)
4(2π/56)
5(2π/56)
6(2π/56)
7(2π/56)
8(2π/56)
9(2π/56)
10(2π/56)
11(2π/56)
12(2π/56)
13(2π/56)
14(2π/56)
15(2π/56)
16(2π/56)
17(2π/56)
18(2π/56)
19(2π/56)
20(2π/56)
21(2π/56)
22(2π/56)
23(2π/56)
24(2π/56)
25(2π/56)
26(2π/56)
27(2π/56)
28(2π/56)
29(2π/56)
30(2π/56)
31(2π/56)
32(2π/56)
33(2π/56)
34(2π/56)
35(2π/56)
36(2π/56)
37(2π/56)
38(2π/56)
39(2π/56)
40(2π/56)
41(2π/56)
42(2π/56)
43(2π/56)
44(2π/56)
45(2π/56)
46(2π/56)
47(2π/56)
48(2π/56)
49(2π/56)
50(2π/56)
51(2π/56)
52(2π/56)
53(2π/56)
54(2π/56)
55(2π/56)
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE18005
45
CDCE18005
SCAS863 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
46
64
Phase Delay
(radian)
0
(2π/60)
2(2π/60)
3(2π/60)
4(2π/60)
5(2π/60)
6(2π/60)
7(2π/60)
8(2π/60)
9(2π/60)
10(2π/60)
11(2π/60)
12(2π/60)
13(2π/60)
14(2π/60)
15(2π/60)
16(2π/60)
17(2π/60)
18(2π/60)
19(2π/60)
20(2π/60)
21(2π/60)
22(2π/60)
23(2π/60)
24(2π/60)
25(2π/60)
26(2π/60)
27(2π/60)
28(2π/60)
29(2π/60)
30(2π/60)
31(2π/60)
32(2π/60)
33(2π/60)
34(2π/60)
35(2π/60)
36(2π/60)
37(2π/60)
38(2π/60)
39(2π/60)
40(2π/60)
41(2π/60)
42(2π/60)
43(2π/60)
44(2π/60)
45(2π/60)
46(2π/60)
47(2π/60)
48(2π/60)
49(2π/60)
50(2π/60)
51(2π/60)
52(2π/60)
53(2π/60)
54(2π/60)
55(2π/60)
56(2π/60)
57(2π/60)
58(2π/60)
59(2π/60)
PHnADGC0
n.6
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
PHnADGC1
Phase Delay
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
PHnADGC2
PHnADGC0
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
PHnADGC3
PHnADGC1
n.9
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
PHnADGC4
PHnADGC2
n.10
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
PHnADGC5
PHnADGC3
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
PHnADGC6
PHnADGC4
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide Ratio
PHnADGC5
60
PHnADGC6
Divide Ratio
Table 24. CDCE18005 Output Coarse Phase Adjust Settings (5)
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
n.10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
n.9
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(radian)
0
(2π/64)
2(2π/64)
3(2π/64)
4(2π/64)
5(2π/64)
6(2π/64)
7(2π/64)
8(2π/64)
9(2π/64)
10(2π/64)
11(2π/64)
12(2π/64)
13(2π/64)
14(2π/64)
15(2π/64)
16(2π/64)
17(2π/64)
18(2π/64)
19(2π/64)
20(2π/64)
21(2π/64)
22(2π/64)
23(2π/64)
24(2π/64)
25(2π/64)
26(2π/64)
27(2π/64)
28(2π/64)
29(2π/64)
30(2π/64)
31(2π/64)
32(2π/64)
33(2π/64)
34(2π/64)
35(2π/64)
36(2π/64)
37(2π/64)
38(2π/64)
39(2π/64)
40(2π/64)
41(2π/64)
42(2π/64)
43(2π/64)
44(2π/64)
45(2π/64)
46(2π/64)
47(2π/64)
48(2π/64)
49(2π/64)
50(2π/64)
51(2π/64)
52(2π/64)
53(2π/64)
54(2π/64)
55(2π/64)
56(2π/64)
57(2π/64)
58(2π/64)
59(2π/64)
60(2π/64)
61(2π/64)
62(2π/64)
63(2π/64)
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80
Phase Delay
(radian)
0
(2π/70)
2(2π/70)
3(2π/70)
4(2π/70)
5(2π/70)
6(2π/70)
7(2π/70)
8(2π/70)
9(2π/70)
10(2π/70)
11(2π/70)
12(2π/70)
13(2π/70)
14(2π/70)
15(2π/70)
16(2π/70)
17(2π/70)
18(2π/70)
19(2π/70)
20(2π/70)
21(2π/70)
22(2π/70)
23(2π/70)
24(2π/70)
25(2π/70)
26(2π/70)
27(2π/70)
28(2π/70)
29(2π/70)
30(2π/70)
31(2π/70)
32(2π/70)
33(2π/70)
34(2π/70)
35(2π/70)
36(2π/70)
37(2π/70)
38(2π/70)
39(2π/70)
40(2π/70)
41(2π/70)
42(2π/70)
43(2π/70)
44(2π/70)
45(2π/70)
46(2π/70)
47(2π/70)
48(2π/70)
49(2π/70)
50(2π/70)
51(2π/70)
52(2π/70)
53(2π/70)
54(2π/70)
55(2π/70)
56(2π/70)
57(2π/70)
58(2π/70)
59(2π/70)
60(2π/70)
61(2π/70)
62(2π/70)
63(2π/70)
64(2π/70)
65(2π/70)
66(2π/70)
67(2π/70)
68(2π/70)
69(2π/70)
PHnADGC0
n.6
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
PHnADGC1
Phase Delay
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
PHnADGC2
PHnADGC0
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
PHnADGC3
PHnADGC1
n.9
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
PHnADGC4
PHnADGC2
n.10
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
PHnADGC5
PHnADGC3
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PHnADGC6
PHnADGC4
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide Ratio
PHnADGC5
70
PHnADGC6
Divide Ratio
Table 25. CDCE18005 Output Coarse Phase Adjust Settings (6)
n.12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
n.11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
n.10
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
n.9
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
n.6
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
(radian)
0
(2π/80)
2(2π/80)
3(2π/80)
4(2π/80)
5(2π/80)
6(2π/80)
7(2π/80)
8(2π/80)
9(2π/80)
10(2π/80)
11(2π/80)
12(2π/80)
13(2π/80)
14(2π/80)
15(2π/80)
16(2π/80)
17(2π/80)
18(2π/80)
19(2π/80)
20(2π/80)
21(2π/80)
22(2π/80)
23(2π/80)
24(2π/80)
25(2π/80)
26(2π/80)
27(2π/80)
28(2π/80)
29(2π/80)
30(2π/80)
31(2π/80)
32(2π/80)
33(2π/80)
34(2π/80)
35(2π/80)
36(2π/80)
37(2π/80)
38(2π/80)
39(2π/80)
40(2π/80)
41(2π/80)
42(2π/80)
43(2π/80)
44(2π/80)
45(2π/80)
46(2π/80)
47(2π/80)
48(2π/80)
49(2π/80)
50(2π/80)
51(2π/80)
52(2π/80)
53(2π/80)
54(2π/80)
55(2π/80)
56(2π/80)
57(2π/80)
58(2π/80)
59(2π/80)
60(2π/80)
61(2π/80)
62(2π/80)
63(2π/80)
64(2π/80)
65(2π/80)
66(2π/80)
67(2π/80)
68(2π/80)
69(2π/80)
70(2π/80)
71(2π/80)
72(2π/80)
73(2π/80)
74(2π/80)
75(2π/80)
76(2π/80)
77(2π/80)
78(2π/80)
79(2π/80)
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CDCE18005
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Auxiliary Output
Figure 27 shows the auxiliary output port. Table 26 lists how the auxiliary output port is controlled. The output
buffer supports a maximum output frequency of 250 MHz and drives at LVCMOS levels. Refer to Table 19 for the
list of divider settings that establishes the output frequency.
Output Divider 2
AUX
OUT
Output Divider 3
Register 6
25
Register 6
24
Figure 27. CDCE18005 Auxiliary Output
Table 26. CDCE18005 Auxiliary Output Settings
Bit Name →
AUXFEEDSEL
AUXOUTEN
Register.Bit →
6.25
6.24
X
0
OFF
0
1
Divider 2
1
1
Divider 3
AUX OUTPUT SOURCE
DEVICE POWER CALCULATION AND THERMAL MANAGEMENT
The CDCE18005 is a high performance device, therefore careful attention must be paid to device configuration
and printed circuit board layout with respect to power consumption. Table 27 provides the power consumption for
the individual blocks within the CDCE18005. To estimate total power consumption, calculate the sum of the
products of the number of blocks used and the power dissipated of each corresponding block.
Provide Sample Calculation Here after numbers become available.
Table 27. CDCE18005 Power Consumption
Internal Block (Power at 3.3V)
Power Dissipated per Block (Typical)
Number of Blocks per Device
Input Circuit
18 mW
1
Output Divider
185 mW
5
Output Buffer ( LVPECL)
116 mW
5
Output Buffer (LVDS)
76 mW
5
Output Buffer (LVCMOS)
86 mW
10
This power estimate determines the degree of thermal management required for a specific design. Employing the
thermally enhanced printed circuit board layout shown in Figure 29 insures that the thermal performance curves
shown in Figure 28 apply. Observing good thermal layout practices enables the thermal pad on the backside of
the QFN-48 package to provide a good thermal path between the die contained within the package and the
ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance
connection to the ground plane is essential.
Figure 29 shows a layout optimized for good thermal performance and a good power supply connection as well.
The 7×7 filled via patter facilitates both considerations. Finally, the recommended layout achieves θJA =
27.3°C/W in still air and 20.3°C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant
thermal test board.
48
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Die Temperature vs Total Device Power
RL 0 LFM 85 C
125
JEDEC 0 LFM 25 C
JEDEC 100 LFM 25 C
RL 0 LFM 25 C
JDEC 0 LFM 85 C
JEDEC 0 LFM 25 C
100
JEDEC 100 LFM 25 C
Die Temp (C)
RL 100 LFM 85 C
RL 0 LFM 25 C
75
JEDEC 100 LFM 85 C
RL 100 LFM 25 C
RL 100 LFM 25 C
JEDEC 0 LFM 85 C
50
JEDEC 100 LFM 85 C
RL 0 LFM 85 C
25
RL 100 LFM 85 C
0
0
1
2
3
4
Power (W)
Figure 28. CDCE18005 Die Temperature vs Device Power
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CDCE18005
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Component Side
QFN-48
Solder Mask
Thermal Slug
(package bottom)
Internal
Ground
Plane
Internal
Power
Plane
Thermal
Dissipation
Pad (back side)
Thermal Vias
No Solder Mask
Back Side
Figure 29. CDCE18005 Recommended PCB Layout
50
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CDCE18005 Power Supply Bypassing – Recommended Layout
Figure 30 shows two conceptual layouts detailing recommended placement of power supply bypass capacitors. If
the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to the
Thermal Dissipation Pad can be difficult. For component side mounting, use 0201 body size capacitors to
facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the
device as short as possible.
Component Side
Back Side
Figure 30. CDCE18005 Power Supply Bypassing
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CDCE18005
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APPLICATION INFORMATION AND GENERAL USAGE HINTS
Fan-out Buffer
Each output of the CDCE18005 can be configured as a fan-out buffer (divider bypassed) or fan-out buffer with
divide and skew control functionality.
PRI_IN
Divide by 1: Up to 1500 MHz
Otherwise : Up to 1175 MHz
U0P
/1 - /80
U0N
SEC_IN
Up to 5 Outputs :
LVPECL or LVDS
Up to 10 Outputs:
LVCMOS
U4P
/1 - /80
U4N
Figure 31. CDCE18005 Fan-out Buffer Mode
Clock Generator
The CDCE18005 can generate 5–10 low noise clocks from a single crystal or crystal oscillator as follows:
XTAL /
AUX_IN
U0P
Output
Divider 0
U0N
U4P
Output
Divider 4
U4N
Figure 32. CDCE18005 Clock Generator Mode
Clock Distribution – Mixed Mode
The following table presents a common scenario where the CDCE18005 can function as a clock switch that
accepts LVDS and crystal inputs and drives LVDS, LVPECL and LVCMOS outputs.
CLOCK FREQUENCY
INPUT/OUTPUT
FORMAT
NUMBER
CDCE18005 PORT
COMMENT
491.52 MHz
Input
LVDS
1
SEC_IN
Reference
125 MHz
Input
LVDS
1
PRI_IN
Reference from backplane
10 MHz
Input
AT-Cut
1
AUX_IN
Low end crystal oscillator
122.88 MHz
Output
LVDS
1
U0
SerDes Clock
491.52 MHz
Output
LVPECL
1
U1
ASIC
125 MHz
Output
LVPECL
1
U2
FPGA
30.72 MHz
Outputs
LVCMOS
2
U3
ASIC
10 MHz
Outputs
LVCMOS
2
U4
CPU, DSP
52
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491.52 MHz
Output
Divider 0
122.88 MHz
Output
Divider 1
491.52 MHz
Output
Divider 2
125.00 MHz
125.00 MHz
Xtal
10MHz
30.72 MHz
Output
Divider 3
Output
Divider 4
30.72 MHz
10 MHz
10 MHz
Figure 33. CDCE18005 Mixed Mode Clock Distribution Example
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCE18005RGZR
ACTIVE
QFN
RGZ
48
2500
TBD
Call TI
Call TI
CDCE18005RGZT
ACTIVE
QFN
RGZ
48
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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dsp.ti.com
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logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
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