CHERRY CS5124

CS5124/6
CS5124/6
High Performance, Integrated Current Mode
PWM Controllers
Features
Description
The CS5124/6 is a fixed frequency
current mode controller designed
specifically for DC-DC converters
found in the telecommunications
industry. The CS5124/6 integrates
many commonly required current
mode power supply features and
allows the power supply designer to
realize substantial cost and board
space savings. The product matrix is
as follows:
CS5124: 400kHz w/VBIAS Pin,
195mV first current sense threshold
CS5126: 200kHz w/SYNC Pin,
335mV first current sense threshold
The CS5124/6 integrates the following features: Internal Oscillator, Slope
Compensation, Sleep On/Off, Under
Voltage Lock Out, Thermal
Shutdown, Soft Start Timer, Low
Voltage Current Sense for Resistive
Sensing, Second Current Threshold
for Pulse by Pulse Over Current
Protection, a Direct Optocoupler
Interface and Leading Edge Current
Blanking.
The CS5124/6 has supply range of
7.7V to 20V and is available in 8 pin
SO narrow package.
■ Line UVLO Monitoring
■ Low Current Sense
Voltage for Resistive
Current Sensing
■ External Synchronization
to Higher or Lower
Frequency Oscillator
(CS5126 Only)
■ Bias for Start up Circuitry
(CS5124 Only)
■ Thermal Shutdown
■ Sleep On/Off Pin
■ Soft Start Timer
■ Leading Edge Blanking
■ Direct Optocoupler
Interface
■ 90ns Propagation Delay
Applications Diagram
■ 35ns Driver Rise and Fall
Times
■ Sleep Mode
36-75VIN
L1
10µH
R1
510k
R2
200k
C1
0.1µF,
100V
D1
CTX15-14514
T1
C2
1.5µF,
100V
Q1
ZVN3310A
R4
10Ω
R5
17.4k
MBRD360CT
D4
VCC
Gnd
BIAS
GATE
UVLO
Q2
IRFR220
C3
.022µF
R6
1k
R8
0.39Ω
VCC
R7
30.1k
C5
47µF,
10V
C6
C9
1000pF
C7
0.1µF
1
Gnd
BIAS
GATE
ISENSE
UVLO
U2
.01µF
IS
VFB
SS
CS5124
SS
Package Options
8 Lead SO Narrow
CS5124
R3
47Ω
BAS16LT1
C4
0.47µF,
25V
ENABLE
5VOUT
VFB
C8
1000pF
CS5126
TPS5908
R9
10.0k
VCC
ISOLATED
RTN
48VRTN
1
Gnd
UVLO
GATE
SYNC
ISENSE
VFB
SS
48V to 5V, 1A flyback converter using the CS5124
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 3/12/99
1
A
®
Company
CS5124/6
Absolute Maximum Ratings
Pin Symbol
Lead Name
VMAX
VMIN
ISOURCE
ISINK
1.5A Peak
200mA DC
1mA
1mA
1mA
2mA
20mA
1mA
1mA
VCC
VCC Power Input
20V
-0.3V
1mA
SYNC (CS5126)
VBIAS (CS5124)
UVLO
SS
VFB
ISENSE
GROUND
Clock Synchronization Input
VCC Clamp Output
UVLO Shutdown Input
Soft Start Capacitor Input
Voltage Feed Back Input
Current Sense Input
Ground
20V
20V
6V
6V
6V
6V
0V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
0V
GATE
Gate Drive Output
20V
-0.3V
1mA
1mA
1mA
1mA
3mA
1mA
1.5A peak
200mA DC
1.5A Peak
200mA DC
1.5A Peak
200mA DC
Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to 135°C
Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to 150°C
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
ESD (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak
Electrical Characteristics: -40°C ≤ TJ ≤ 125°C, -40°C ≤ TA ≤ 105°C, 7.60V ≤ VCC ≤ 20V, UVLO = 3.0V, ISENSE = 0V,
CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10Ω), CSS = 470pF CV(FB) = 100pF, unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
500
210
13
750
275
mA
µA
µA
7.2
6.8
350
7.7
7.3
425
8.3
7.8
500
V
V
mV
1.5
(Note 1)
35
2.3
1.8
1.88
85
2.45
2.3
2.45
150
2.6
V
V
mV
V
(Note 1)
2.50
2.63
2.76
V
Turn-on – Turnoff (-40°C ≤ TJ ≤ 100°C)
(Note 1)
Turn-on – Turnoff (100°C ≤ TJ ≤ 125°C)
(Note 1)
170
185
200
mV
50
185
400
mV
-1
5
7.5
1
12
µA
V
■ General
ICC Operating - VGATE not switching.
ICC at VCC Low
VCC = 6V
ICC Sleep
VUVL = 1V
■ Low VCC Lockout
VCC Turn-on Threshold Voltage
VCC Turn-off Threshold Voltage
VCC Hysteresis
■ UVLO
Sleep Threshold Voltage
Sleep Threshold Voltage
Sleep Hysteresis
UVLO Turn-off
Threshold Voltage
UVLO Turn-on
Threshold Voltage
UVLO Hysteresis
UVLO Hysteresis
UVLO Input Bias Current
UVLO Clamp
UVLO decreasing
UVLO increasing
With UVLO sinking 1mA.
2
UNIT
CS5124/6
Electrical Characteristics: -40°C ≤ TJ ≤ 125°C, -40°C ≤ TA ≤ 105°C, 7.60V ≤ VCC ≤ 20V, UVLO = 3.0V, ISENSE = 0V,
CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10Ω), CSS = 470pF CV(FB) = 100pF, unless otherwise stated.
PARAMETER
■ VCC Clamp and BIAS Pin
VCC Clamp Voltage
BIAS Minimum Voltage
BIAS Clamp
TEST CONDITIONS
TYP
MAX
CS5124 Only. Connect an NFET as follows: BIAS = G, VCC = S, VIN = D.
36V ≤ VIN ≤ 60V, 220nF ≤
7.275
7.9
8.625
CSS ≤ 500nF, R = 500k
Measure Voltage on BIAS with:
1.6
2.8
4
10V ≤ VCC ≤ 20V and 50µA ≤ IBIAS ≤ 1mA
With BIAS pin sinking 1mA
12
15
20
■ 200kHz Oscillator
CS5126 Only
Operating Frequency
Max Duty Cycle Clamp
Slope Compensation
(Normal operation)
Slope Compensation
(Synchronized operation)
(Note 1)
SYNC Input Threshold Voltage
SYNC Input Impedance
Measured with SYNC = 1V &10V
■ 400kHz Oscillator
Operating Frequency
Max Duty Cycle Clamp
Slope Compensation
MIN
UNIT
V
V
V
175
78
12
200
82.5
18
225
85
23
kHz
%
mV/µs
7
1
50
12
2
120
16
3
230
mV/µs
V
kΩ
360
80.0
15
400
82.5
21
440
85.0
26
kHz
%
mV/µs
7
0.5
10
10.0
13
µA
mA
1.40
1.62
1.80
V
4.7
200
4.9
275
400
V
mV
170
250
60
195
275
90
215
315
130
mV
mV
ns
90
130
60
180
ns
mV
300
485
335
525
360
575
mV
mV
60
90
130
ns
110
175
125
210
ns
mV
CS5124 Only
■ Soft Start
Soft Start Charge Current
Soft Start Discharge Current
VSS Voltage when VFB
VFB = 300mV
Begins to Rise
Peak Soft Start Charge Voltage
Valley Soft Start Discharge Voltage
■ Current Sense
CS5124 Only
First Current Sense Threshold
At max duty cycle.
Second Current Sense Threshold
ISENSE to GATE Prop. Delay
0 to 700mV pulse into ISENSE
(after blanking time)
Leading Edge Blanking Time
0 to 400mV pulse into ISENSE
Internal Offset
(Note 1)
■ Current Sense
First Current Sense Threshold
Second Current Sense
Threshold
ISENSE to GATE Prop. Delay
CS5126 Only
At max duty cycle
Leading Edge Blanking Time
0 to 800mV pulse into ISENSE
(after blanking time)
0 to 550mV pulse into ISENSE
Internal Offset
(Note 1)
3
CS5124/6
Electrical Characteristics: -40°C ≤ TJ ≤ 125°C, -40°C ≤ TA ≤ 105°C, 7.60V ≤ VCC ≤ 20V, UVLO = 3.0V, ISENSE = 0V,
CV(CC) = 0.33µF, CGATE = 1nF (ESR = 10Ω), CSS = 470pF CV(FB) = 100pF, unless otherwise stated.
PARAMETER
TEST CONDITIONS
■ Voltage Feedback
VFB Pull-up Res.
VFB Clamp Voltage
VFB Clamp Voltage
VFB Fault Voltage Threshold
CS5124 Only
CS5126 Only
■ Output Gate Drive
Maximum Sleep
Pull-down Voltage
GATE High (AC)
GATE Low (AC)
GATE High Clamp Voltage
Rise Time
MIN
TYP
MAX
2.9
4.3
8.1
kΩ
2.63
2.40
2.90
2.65
3.15
2.90
V
V
460
490
520
mV
1.2
2.0
V
VCC-0.5
0.0
13.5
45
0.5
16.0
65
V
V
V
ns
25
55
ns
150
125
25
165
150
35
°C
°C
°C
VCC = 6.0V, IOUT = 1mA
Series resistance < 1Ω (Note 1)
Series resistance < 1Ω (Note 1)
VCC = 20V
Measure GATE rise time,
1V < GATE < 9V; VCC =12V
Measure GATE fall time,
9V > GATE > 1V; VCC = 12V
Fall Time
■ Thermal Shutdown
Thermal Shutdown Temperature (Note 1) (GATE low)
Thermal Enable Temperature
(Note 1) (GATE switching)
Thermal Hysteresis
(Note 1)
Notes
1. Not tested in production. Specification is guaranteed by design.
VCC-1
11.0
135
100
15
UNIT
Package Lead Description
PACKAGE LEAD #
LEAD SYMBOL
8 Lead SO Narrow
CS5124
CS5126
1
1
2
-
VCC
BIAS
-
3
SYNC
3
2
UVLO
4
4
SS
5
5
VFB
6
6
ISENSE
7
7
GATE
8
8
Gnd
FUNCTION
VCC Power Input Pin.
VCC Clamp Output Pin. This pin will control the gate of an N-channel MOSFET that in turn regulates VCC. This pin is internally clamped at 15V when
the IC is in sleep mode.
Clock Synchronization Pin. A positive edge will terminate the current PWM
cycle. Ground this pin when it is not used.
Sleep and under voltage lockout pin. A voltage greater than 1.8V causes the
chip to "wake up" however the GATE remains low. A voltage greater than
2.6V on this pin allows the output to switch.
Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is
charged with 10µA and discharged with 10mA. The Soft Start capacitor controls both soft-start time and hiccup mode frequency.
Voltage Feedback Pin. The collector of an optocoupler is typically tied to this
pin. This pin is pulled up internally by a 4.3kΩ resistor to 5V and is clamped
internally at 2.9V(2.65V). If VFB is pulled > 4V, the oscillator is disabled and
GATE will stay high. If the VFB pin is pulled < 0.49V, GATE will stay low.
Current Sense Pin. This pin is connected to the current sense resistor on the
primary side. If VFB is floating, the GATE will go low if ISENSE = 195mV
(335mV). If ISENSE > 275mV (525mV), Soft Start will be initiated.
Gate Drive Output Pin. Capable of driving a 3nF load. GATE is nominally
clamped to 13.5V.
Ground Pin.
4
CS5124/6
Block Diagram
{CS5126 ONLY}
SYNC
VCC
VCC UVLO COMP
VCC
VREF = 5V
G2
+
F3
OSC
DIS
+
Q
R
F1
RAMP
-
TSHUT
{85 mV/us}
170mV us
+
V 490mV
+
+
V 1.91 V/1.83V
÷
+
SOFT START LATCH
2.9 R
G5
S
2ND ICOMP
R
SS COMP
1000Ω
ISENSE
V
BLANKING
BLANK
R
+
+
Q
SET DOMAIN
-
LINE AMP -
VFB
{525mV}
275mV
-
F2
VCC
{1/5}
1/10
V
{125mV}
60mV
+
2.0V V
+
PWM COMP -
-
+
+
VFB COMP
10µA
(CS5124 ONLY)
4500Ω
-
REMOTE
(SLEEP) COMP
+
BIAS
V5REF
G3
V5REF
V 2.62 V/2.45V
UVLO
GATE
R
G7
+
150°C/125°C +
DRIVER
Q
RESET DOMAIN
V5REF
V+REFOK
V
S
S
ENABLE
V 7.7 V/7.275V
LINE UVLO COMP
-
G1
G6
{2.65V}
2.90V
V5REF
+
+
V
+
SS AMP
-
+
275mV V
1.32V
+
SS
Gnd
V
Theory of Operation
Powering the IC
10µA. As the capacitor charges, a buffered version of the
capacitor voltage appears on the VFB pin and the VFB voltage begins to rise. As VFB rises the duty cycle increases
until the supply comes into regulation.
VCC can be powered directly from a regulated supply
and requires 500µA of start-up current. The CS5124/6
includes a line bias pin (BIAS) that can be used to control a
series pass transistor for operation over a wide input voltage. The BIAS pin will control the gate voltage of an Nchannel MOSFET placed between VIN and VCC to regulate
VCC at 8V.
Soft Start
Soft Start is accomplished by clamping the VFB pin 1.32V
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124/6 starts, the Soft
Start capacitor is charged from a 10µA source from 0V to
4.9V. The VFB pin follows the Soft Start pin offset by –1.32V
until the supply comes into regulation or until the Soft
Start error amp is clamped at 2.9V (2.65V for the CS5126).
During fault conditions the Soft Start capacitor is discharged at 10mA.
VCC and UVLO Pins
The UVLO pin has three different modes; low power shutdown, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that VIN, as shown in
the application schematic, is ramped up starting at 0V with
the UVLO pin open. The SS and ISENSE pins also start at 0V.
While the UVLO is below 1.8V, the IC will remain in a low
current sleep mode and the BIAS pin of the CS5124 is internally clamped to a maximum of 15V. When the voltage on
the UVLO pin rises to between 1.8V and 2.6V the reference
for the VCC UVLO is enabled and VCC is regulated to 8V by
the BIAS pin (CS5124 only), but the IC remains in a UVLO
state and the output driver does not switch. When the
UVLO pin exceeds 2.6V and the VCC pin exceeds 7.7V, the
GATE pin is released from a low state and can begin
switching based on the comparison of the ISENSE and VFB
pins. The Soft Start capacitor begins charging from 0V at
Fault Conditions
The CS5124/6 recognizes the following faults: UVLO off,
Thermal Shutdown, VREF(OK), and Second Current
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft Start capacitor. Soft Start will begin
only after all faults have been removed and the Soft Start
capacitor has been discharged to less than 0.275V. Each
fault will be explained in the following sections.
5
CS5124/6
Theory of Operation: continued
Under Voltage Lockout (UVLO)
for the CS5126) threshold. If the ISENSE voltage exceeds the
second threshold, F2 is set, the driver turns off, and the
soft-start capacitor discharges. After the Soft Start capacitor
has discharged to less than 0.275V Soft Start will begin. If
the fault condition has been removed the supply will operate normally. If the fault remains the supply will operate in
hiccup mode until the fault condition is removed.
The UVLO pin is tied to typically the midpoint of a resistive divider between VIN and GROUND. During a start up
sequence, this pin must be above 2.6V in order for the IC to
begin normal operation. If the IC is running and this pin is
pulled below 1.8V, F2 shuts down the output driver and
discharges the Soft Start capacitor in order to insure proper
start-up. If the UVLO pin is pulled high again before the
Soft Start capacitor discharges, the IC will complete the
Soft Start discharge and, if no other faults are present, will
immediately restart the power supply. If the UVLO pin
stays low, then it will enter either the low current sleep
mode or the UVLO state depending on the level of the
UVLO pin.
VFB Comparator
The VFB comparator detects when the output voltage is too
high. When the regulated output voltage is too high, the
feedback loop will drive VFB low. If VFB is less than 0.49V
the output of the VFB comparator will go high and shut the
output driver off.
Oscillator
Thermal Shutdown
The internally trimmed, 400kHz (CS5124) or 200kHz
(CS5126) provides the slope compensation ramp as well as
the pulse for enabling the output driver.
If the IC junction temperature exceeds approximately
150°C the thermal shutdown circuit sets F2, which shuts
down the output driver and discharges the Soft Start
capacitor. If no other faults are present the IC will initiate
Soft Start when the IC junction temperature has been
reduced by 25°C.
PWM Comparator and Slope Compensation
The CS5124/6 provides a fixed internal slope compensation ramp that is subtracted from the feedback signal. The
pwm comparator compares peak primary current to a portion of the difference of the feedback voltage and slope
compensation ramp. The 170mV/µs (85mV/µs for the
CS5126) slope compensation ramp is subtracted from the
voltage feedback signal internally. The difference signal is
then divided by ten (five for the CS5126) before the PWM
comparator to provide high noise rejection with a low voltage across the current sense network. (The effective ramp
is 21mV/µs for the CS5124, and 18mV/µs for the CS5126).
A 60mV (125mV for the CS5126) nominal offset on the positive input to the PWM comparator allows for operation
with the ISENSE pin at, or even slightly below Gnd.
VREF(OK)
VREF(OK) is an internal monitor that insures the internal
regulator is running before any switching occurs. This
function does not trip the fault comparator like the other
fault functions. To insure that Soft Start will occur at low
line conditions the UVLO divider should be set up so that
the VCC UVLO comparator turns on before the LINE
UVLO comparator.
Second Threshold Comparator
Since the maximum dynamic range of the ISENSE signal in
normal operation is 195mV (335mV for the CS5126), any
voltage exceeding this threshold on the ISENSE pin is considered a fault and the PWM cycle is terminated. The 2nd
ICOMP compares the ISENSE signal with a 275mV (525mV
A 4.3kΩ pull-up resistor internally connected to a 5V nominal reference provides the bias current to for an opto-coupler connection to the VFB pin.
Application Information
UVLO and Thermal Shutdown Interaction
BIAS Pin (CS5124 Only)
The UVLO pin and thermal shutdown circuit share the
same internal comparator. During high temperature operation (TJ >100°C) the UVLO pin will interact with the thermal shutdown circuit. This interaction increases the turnon threshold (and hysteresis) of the UVLO circuit. If the
UVLO pin shuts down the IC during high temperature
operation, higher hysteresis (see hysteresis specification)
might be required to enable the IC.
The bias pin can be used to control VCC as shown in the
main application diagram. In order to provide adequate
phase margin for the bias control loop, the pole created by
the series pass transistor and the VCC bypass capacitor
should be kept above 10kHz. The frequency of this pole
can be calculated by Formula (1).
Pole
Transconductance of pass Transistor
Frequency =
2 × π × CV(CC)
6
(1)
The Line BIAS pin shows a significant change in the regulated VCC voltage when sinking large currents. This will
show up as poor line regulation with a low value pull-up
resistor. Typical regulated VCC vs BIAS pin sink current is
shown in Figure 1.
the rising edge of the Gate is shown in Figure 4. When this
pin is held high or low the internal clock determines the
oscillator frequency.
SYNC
8.3
OSC
GATE
VCC
8.2
Figure 3. Synchronized Operation
8.1
8
140
7.9
130
5µ
10µA
20µA
50µA
100µA
200µA
Phase Lag°
Bias Current (IBIAS)
Figure 1. Regulated VCC vs BIAS Sink Current
Clock Synchronization Pin (CS5126 Only)
120
110
100
90
The CS5126 can be synchronized to signals ranging from
30% slower to several times faster than the internal oscillator frequency. If the part is synchronized to a fast signal,
maximum duty cycle will be reduced as the frequency
increases as shown in Figure 2.
80
70
200kHz
300kHz
400kHz
500kHz
600kHz
Figure 4 : Typical Phase Lag between SYNC and GATE on.
0.82
Rail to rail gate driver operation can be obtained (up to
13.5V) over a range of MOSFET input capacitance if the
gate resistor value is kept low. Figure 5 shows the high
gate drive level vs. the series gate resistance with VCC = 8V
driving an IRF220.
125°C
25°C
0.77
0.72
200kHz
-40°C
300kHz
400kHz
Frequency
500kHz
8.5
600kHz
8
Peak Voltage
Maximum Duty Cycle
Gate Drive
Figure 2: CS5126 Maximum Duty Cycle vs Frequency (Synchronized
Operation)
7.5
7
6.5
If the converter is initially free running and a sync signal is
applied, the current oscillator cycle will terminate and the
oscillator will lock on to the sync signal. The SYNC pin
works with a positive edge triggered signal. When the sync
signal transitions high the current PWM cycle terminates
and a new cycle begins as shown in Figure 3. The typical
phase lag between the rising edge of the SYNC signal and
6
0
0.3
0.5
2.5
5
11
Gate Resistor Value
Figure 5. Gate Drive vs Gate Resistor Driving an IRF220 (VCC = 8V)
7
CS5124/6
Application Information: continued
CS5124/6
Application Information: continued
after a second threshold over-current condition will primarily be determined by the time required to charge the
Soft Start cap from 0.275V nominal to 1.32V.
A large negative dv/dt on the power MOSFET drain will
couple current into the gate driver through the gate to
drain capacitance. If this current is kept within absolute
maximum ratings for the GATE pin it will not damage the
IC. However if a high negative dv/dt coincides with the
start of a PWM duty cycle, there will be small variations in
oscillator frequency due to current in the controller substrate. If required, this can be avoided by choosing the
transformer ratio and reset circuit so that a high dv/dt
does not coincide with the start of a PWM cycle, or by
clamping the negative voltage on the GATE pin with a
schottky diode
The second threshold will only be reached when a high
dv/dt is present at the current sense pin. The signal must
be fast enough to reach the second threshold before the
first threshold turns off the driver. This will normally happen if the forward inductor saturates or when there is a
shorted load.
Excessive filtering of the current sense signal, a low value
current sense resistor, or even an inductor that does not
saturate during heavy output currents can prevent the second threshold from being reached. In this case the first current sense threshold will trip during each cycle of high output current conditions. The first threshold will limit output
current but some components, especially the output rectifier, can overheat due to higher than normal average output
current.
First Current Sense Threshold
During normal operation the peak primary current is controlled by the level of the VFB pin (as determined by the
control loop) and the current sense network. Once the signal on the ISENSE pin exceeds the level determined by VFB
pin the pwm cycle terminates. During high output currents
the VFB pin will rise until it reaches the VFB clamp. The first
current sense threshold determines the maximum signal
allowed on the ISENSE pin before the PWM cycle is terminated. Under this condition the maximum peak current is
determined by the VFB Clamp, the slope compensation
ramp, the PWM comparator offset voltage and the PWM
on time. The nominal first current threshold varies with on
time and can be calculated from Formulas (2) & (3) below.
CS5124
2.9V – 170mV/µs × TON
1st Threshold =
– 60mV
10
Slope Compensation
Current mode converters operating at duty cycles in excess
of 50% require an artificial ramp to be added to the current
waveform or subtracted from the feedback waveform. For
the current loop to be stable the artificial ramp must be
equivalent to at least 50% of the inductor current down
slope and is typically chosen between 75 % to 100% of the
inductor down current down slope.
To choose an inductor value such that the internal slope
compensation ramp will be equal to a certain fraction of
the inductor down current slope use the Formula (4).
(2)
NSECONDARY
1
× (VOUT + VRECTIFIER) ×
×
NPRIMARY
Internal Ramp
CS5126
2.65V – 85mV/µs × TON
1st Threshold =
– 125mV
5
RI(SENSE) × Slope Value Factor = Inductor Value (H)
(3)
(4)
Calculating the nominal inductor value for an artificial
ramp equivalent to 100% of the current inductor down
slope at CS5126 nominal conditions, a 5V output, a 200mΩ
current sense resistor and a 4:1 transformer ratio yields
When the output current is high enough for the ISENSE pin
to exceed the first threshold, the pwm cycle terminates
early and the converter begins to function more like a current source. The current sense network must be chosen so
that the peak current during normal operation does not
exceed the first current sense threshold.
1
20mV/µs
× (5V + 0.3V) ×
1
× 0.2Ω × 1 = 13.2 µH
4
To check that the slope compensation ramp will be greater
than 50% of the inductor down under all conditions, substitute the minimum internal slope compensation value
and use 0.5 for the slope compensation value. Then check
that the actual inductor value will always be greater than
the inductor value calculated.
Second Current Sense Threshold
The second threshold is intended to protect the converter
from over-heating by switching to a low duty cycle mode
when there are abnormally high fast rise currents in the
converter. If the second current sense threshold is tripped,
the converter will shut off and restart in Soft Start mode
until the high current condition is removed. The dead time
During synchronized operation of the CS5126 the slope
compensation ramp is reduced by 33%. If the CS5126 will
8
be used in synchronized operation, the inductor value
should be recalculated to work with the slope compensation ramp reduced to 67% of the normal value.
converter and performs the same function as the flyback
winding above.
A flyback winding from a forward transformer can also be
used to power VCC. Ideally the transformer volt-second
product of a forward converter would be constant over the
range of line voltages and load currents; and the transformer inductance could be chosen to store the required
level of energy during each cycle to power VCC. Even
though the flyback energy is not directly regulated it
would remain constant. Unfortunately in a real converter
there are many non-ideal effects that degrade regulation.
Transformer inductance varies, converter frequency varies,
energy stored in primary leakage inductance varies with
output current, stray transformer capacitances and various
parasitics all effect the level of energy available for VCC. If
too little energy is provided to VCC, the bootstrapping circuit must provide power and efficiency will be reduced. If
too much energy is provided VCC rises and may damage
the controller. If this approach is taken the circuit must be
carefully designed and component values must be controlled for good regulation.
Powering the CS5124/6 from a Transformer Winding
There are numerous ways to power the CS5124/6 from a
transformer winding to enable the converter to be operated
at high efficiency over a wide input range. Two ways are
shown in the application circuits.
The CS5124 application circuit (main application diagram)
is a flyback converter that uses a second flyback winding
to power VCC. R4 improves VCC regulation with load
changes by snubbing the turn off spike. Once the turn off
spike has subsided the voltage of this winding is voltage
proportional to the voltage on the main flyback winding.
This voltage is regulated because the main winding is
clamped by the regulated output voltage.
In the CS5126 application circuit (below) an extra winding
is added to the forward inductor to power VCC. This winding is phased to conduct during the off time of the forward
Additional Application Diagram
36-75VIN
CTX15-14526
L1
T1
CTX15-14527
10µH
C3
0.2µF, 100V
R2
200k
C2
1.5µF,
100V
5VOUT
R1
39k
T2
Q1
F2T493
C1
1.5µF,
100V
R6
17.4k
D3
11V
C5
1µF,
25V
ENABLE
10k
C4
1000pF
R10
10k
C11
0.1µF
R4
0.2Ω
1/4W
C6
390pF
MMBD6100L
VCC
Gnd
UVLO
GATE
IS
SYNC
SS
R9
SYNC
MBRB2060CT
Q2
IRF634
D2
C12
.01µF
R7
2k
R3
30.1k
C8
47µF
C7
47µF
C9
U2
.01µF
VFB
CS5126
C10
1000pF
TPS5908
R8
10.0k
ISOLATED
RTN
48VRTN
48V to 5V, 5A forward converter using the CS5126
9
CS5124/6
Application Information: continued
CS5124/6
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
Thermal Data
RΘJC
typ
RΘJA
typ
D
Lead Count
8 Lead SO Narrow
Metric
Max
Min
5.00
4.80
English
Max Min
.197 .189
8L SO Narrow
45
165
˚C/W
C/W
Surface Mount Narrow Body (D); 150 mil wide
4.00 (.157)
3.80 (.150)
6.20 (.244)
5.80 (.228)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
1.75 (.069) MAX
1.57 (.062)
1.37 (.054)
1.27 (.050)
0.40 (.016)
0.25 (.010)
0.19 (.008)
D
0.25 (0.10)
0.10 (.004)
REF: JEDEC MS-012
Ordering Information
Part Number
CS5124XD8
CS5124XDR8
CS5126XD8
CS5126XDR8
Rev. 3/12/99
Description
8 Lead SO Narrow
8 Lead SO Narrow (tape & reel)
8 Lead SO Narrow
8 Lead SO Narrow (tape & reel)
Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.
10
© 1999 Cherry Semiconductor Corporation