SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
FEATURES
D Low Output Jitter
D “Soft Stop” shut down of MAIN and AUX
D 110-V Input Startup Function
D Ideal for Active Clamp/Reset Forward,
DESCRIPTION
The UCC2897A PWM controller simplifies
implementation of the various active clamp/reset
and synchronous rectifier switching power
topologies.
Flyback and Synchronous Rectifier Uses
The UCC2897A is a peak current-mode, fixedfrequency, high-performance pulse width modulator.
It includes the logic and the drive capability for the
P-channel auxiliary switch along with a simple
method of programming the critical delays for
proper active clamp operation.
D Provides Complementary Auxiliary Driver
D
D
D
D
D
D
D
D
with Programmable Deadtime (Turn-On
Delay) between AUX and MAIN Switches
Peak Current-Mode Control with 0.5-V
Cycle-by-Cycle Current Limiting
Hiccup Mode 0.75-V Current Limit
TrueDrivet 2-A Sink, 2-A Source Outputs
Trimmed Internal Bandgap Reference for
Accurate Line UV and Line OV Threshold
Programmable Slope Compensation
High-Performance 1.0-MHz Synchronizable
Oscillator with Internal Timing Capacitor
Precise Programmable Maximum Duty Cycle
PB-Free Lead Finish Package
Features include an internal programmable slope
compensation circuit, precise DMAX limit, and a
synchronizable oscillator with an internal timing
capacitor. An accurate line monitoring function
also programs the converter’s ON and OFF
transitions with regard to the bulk input voltage,
VIN.
The UCC2897A adds a second level hiccup mode
current
sense
threshold,
bi-directional
synchronization and input overvoltage protection
functionalities. The UCC2897A is offered in 20-pin
TSSOP (PW) and 20-pin QFN (RGP) package.
APPLICATIONS
D High-Efficiency DC/DC Power Supplies
D Server Power, 48-V Telecom, Datacom, and
42-V Automotive Applications
TYPICAL APPLICATION DIAGRAM
R DEL
3
1
LINEOV
19
R ON
4
R OFF
C VREF
BIAS
WINDING
UCC2897A
VIN
RDEL
RON
5
ROFF
6
VREF
LINEUV
18
VDD
17
PVDD
16
OUT
15
AUX
14
10
RSLOPE PGND
13
12
SS/SD
FB
11
7
SYNC
8
GND
9
CS
R SLOPE
Q4
LO
D3
D4
CO
LOAD
Q3
CBIAS
ROUT
CAUX
CF
+VIN
Q1
DAUX
D1
SR
DRIVE
Q2
SECONDARY
SIDE E/A
C SS
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
Copyright 2008, Texas Instruments Incorporated
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1
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Line input voltage, VIN
Supply voltage, VDD
Analog inputs
Output source current (peak), IO_SOURCE
Output sink current (peak), IO_SINK
(IDD < 10 mA)
FB, CS, SYNC, LINEOV, LINEUV
120
V
16.5
V
−0.3 to (VREF + 0.3)
V
2.5
OUT, AUX
Operating junction temperature range, TJ
−55 to 150
Storage temperature, Tstg
−65 to 150
ESD rating
A
−2.5
Human body model, (HBM)
2000
Charged device model (CDM)
500
°C
V
Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds
300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into and negative out of, the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
Line input voltage, VIN
18
Supply voltage, VDD
8.5
Supply bypass capacitance, VDD (2)
12.0
MAX
UNIT
110
V
14.5
75
Operating junction temperature, TJ
−40
Reference bypass capacitance, CREF
0.1
(1) Supply bypass capacitance should be greater than VREF capacitance by at least 10 times.
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V
µF
1
Timing resistance, RON = ROFF (for 250-kHz
operation)
2
NOM
kΩ
125
°C
µF
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
ORDERING INFORMATION
PART
NUMBERS{
TA
APPLICATION
AUX
OUTPUT
POLARITY
CYCLE-BYCYCLE CS
THRESHOLD
HICCUP
MODE CS
THRESHOLD
110-V HV JFET
START-UP
CIRCUIT
TSSOP−20
(PW)}
QFN−20
(RGP)}
−40°C to 125°C
DC/DC
P-Channel
0.5 V
0.75 V
Yes
UCC2897APW UCC2897ARGP
† The PW package is available taped and reeled. Add R suffix to device type (e.g. UCC2897APWR) to order quantities of 2,000 devices per
reel. Bulk quantities are 70 units per tube. The RGP package is available in two options of tape and reel. The RGPT is orderable in small
reels of 250 (e.g. UCC2897ARGPT); the RGPR contains 3000 pieces per reel (e.g. UCC2897ARGPR).
‡ The TSSOP-20 (PW) and QFN−20 (RGP) package uses Pb-free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C
peak reflow temperature and compatible with either lead free or Sn/Pb soldering operations.
THERMAL RESISTANCE INFORMATION
THERMAL RESISTANCE(1)
PACKAGE
UNITS
36.6 to 35.0
TSSOP−20 (PW)
θjc
θja
108.4 to 147.0
θjc
TBD
QFN−20 (RGP)
θja
TBD
°C/W
°C/W
(1) Thermal resistance is measured in accordance with JEDEC JESD 51 test conditions and is useful for thermal performance comparison of
different packages. Performance in any specific use is a function of board layout, board construction, air flow and other parameters.
PIN ASSIGNMENTS
QFN PACKAGE
(BOTTOM VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
N/C
LINEOV
LINEUV
VDD
PVDD
OUT
AUX
PGND
SS/SD
FB
1
RDEL
NC
VIN
NC
LINEOV
2
3
4
5
20
6
19
7
18
8
17
9
16
10
15 14 13 12 11
CS
RSLOPE
FB
SS/SD
PGND
LINEUV
VDD
PVDD
OUT
AUX
VIN
N/C
RDEL
RON
ROFF
VREF
SYNC
GND
CS
RSLOPE
RON
ROFF
VREF
SYNC
GND
PW PACKAGE
(TOP VIEW)
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3
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
ELECTRICAL CHARACTERISTICS
VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,
RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
ISTARTUP
Start-up current
IDD
Operating supply current(1)(2)
VDD < VUVLO
VFB = 0 V,
VCS = 0 V,
Outputs not switching
300
500
µA
2
3
mA
HIGH-VOLTAGE BIAS SECTION
IDD−ST
VDD startup current
IVIN
JFET leakage current
UNDERVOLTAGE LOCKOUT
UVLO
Current available from VDD during startup(3)
4
11
VIN = 120 V; VDD = 14 V
Start threshold voltage
mA
75
µA
12.2
12.7
13.2
Minimum operating voltage after start
7.6
8.0
8.4
Hysteresis
4.4
4.7
5.0
1.243
1.268
1.294
V
V
LINE MONITOR
VLINEUV
ILINEUVHYS
Line UV voltage threshold
Line UV hysteresis current
−11.5
−13.0
−14.5
µA
VLINEOV
ILINEOVHYS
Line OV voltage threshold
1.243
1.268
1.294
V
Line OV hysteresis current
−11.5
−13.0
−14.5
µA
−10.5
−14.5
−18.5
10.5
14.5
18.5
0.4
0.5
0.6
V
4.85
5.00
5.15
V
4.75
5.00
5.25
V
−20
−11
−8
SOFT-START
ISSC
ISSD
SS charge current
SS discharge current
RON = 75 kΩ (4)
RON = 75 kΩ (4)
VSS/SD
Discharge/shutdown threshold voltage
VOLTAGE REFERENCE
VREF
VREF
Reference voltage
Reference voltage
TJ = 25°C
0 A < IREF < 5 mA,
ISC
Short circuit current
INTERNAL SLOPE COMPENSATION
REF = 0 V,
m
FB = High
Slope
over temperature
TJ = 25°C
-10%
R CS
R SLOPE
A
µA
mA
+10%
OSCILLATOR
fOSC
Oscillator frequency
TJ = 25°C
−40°C < TJ < 125°C; 8.5V < VDD < 14.5V
237
225
250
265
270
kHz
VP_P
Oscillator amplitude (peak-to-peak)
2
V
(1) Set VDD above the start threshold before setting at 12 V.
(2) Does not include current of the external oscillator network.
(3) The power supply starts with IDD−ST load on VDD. For more information see the Detailed Pin Description section for VIN and VDD.
(4) ISSC and ISS/SD are directly proportional to IRON. See equation 7.
4
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SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
ELECTRICAL CHARACTERISTICS
VDD = 12 V(1), 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, RON = ROFF = 75 kΩ, RDEL = 10 kΩ,
RSLOPE = 50 kΩ, −40 °C ≤ TA = TJ ≤ 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYNCHRONIZATION
SYNC input high voltage
3.0
V
SYNC input low voltage
1.6
SYNC pull down output current
SYNC pull up output current
SYNC output pulse width
tDEL
PWM
SYNC-to-output delay
DMAX
Maximum duty cycle
V
600
µA
−600
µA
150
ns
50
ns
66%
70%
74%
0.43
0.50
0.61
0.40
0.50
0.60
Minimum duty cycle
0%
PWM offset
CS = 0 V
V
CURRENT SENSE
VLVL
VERR(max)
Current sense level shift voltage
Maximum voltage error (clamped)
5.0
VCS
Current sense threshold
cycle−by−cycle
0.43
0.48
0.53
VCS
Current sense threshold
hiccup mode
0.71
0.76
0.81
19
28
14
23
V
OUTPUT (OUT AND AUX)
tR
tF
Rise time
CLOAD = 2 nF
Fall time
CLOAD = 2 nF
tDEL1
tDEL2
Delay time (AUX to OUT)
CLOAD = 2 nF,
RDEL = 10 kΩ
110
Delay time (OUT to AUX)
CLOAD = 2 nF,
RDEL = 10 kΩ
115
IOUT(src)
IOUT(sink)
Output source current
ns
−2
Output sink current
2
A
VOUT(low) Low-level output voltage
IOUT = 150 mA
0.4
V
VOUT(high) High-level output voltage
IOUT = −150 mA
0.9
(1) Set VDD above the start threshold before setting at 12 V.
(2) Maximum pulse width needs to be less than DMAX, which is a function of RON and ROFF. For more information on DMAX, see detailed pin
description for ROFF.
50%
50%
t
OUT
AUX
50%
50%
(P−channel)
tDEL1
t
tDEL2
Figure 1. Output Timing Diagram
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5
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
FUNCTIONAL BLOCK DIAGRAM
VIN
N/C
1
2
2.5V
VREF
IRDEL
RDEL
VREF
3
2.5V
0.05 y IRDEL
CLOCK
Start
ICHG
20
N/C
19
LINEOV
18
LINEUV
17
VDD
0.05 y IRDEL
LineOV
1.27 V
RON
End
4
LineUV
1.27 V
1−DMAX
2.5V
IDSCHG
13V / 8V
VDD
CT
ROFF
5
OUT
SYNC
VDD
VREF
PWM
OFF
16 PVDD
IRDEL
OUT
VREF
SYNC
6
REF
GEN
Q
R
Q
Turn−on Delay
IRDEL
13
PGND
0.43 y ICHG
9
12
CT
4yR
1−DMAX
VDD
VREF
LineUV
LineOV
UVLO & SS
SS/SD
0.43 y ICHG
Restart
Enable
R
11
Note: Pin numbers shown are for PW (TSSOP−20) package.
6
AUX
VREF
0.75V
5 y ISLOPE
RSLOPE 10
14
Turn−on Delay
8
ISLOPE
OUT
+
VREF
CS
15
VREF
7
0.5V
GND
S
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FB
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
TERMINAL FUNCTIONS
TERMINAL
UCC2897A
TSSOP−20
(PW)
UCC2897A
QFN−20
(RGP)
I/O
AUX
14
11
O
This output drives the auxiliary clamp MOSFET which is turned on when the main
PWM switching device is turned off. The AUX pin can directly drive the auxiliary
switch with 2-A source turn-on current and 2-A sink turn-off current.
CS
9
6
I
This pin is used to sense the peak current utilized for current mode control and for
current limiting functions. The peak signal which can be applied to this pin before
pulse−by−pulse current limiting activates is approximately 0.5 V.
FB
11
8
I
This pin is used to bring the error signal from an external optocoupler or error amplifier into the PWM control circuitry. Often, there is a resistor tied from FB to VREF, and
an optocoupler is used to pull the control pin closer to GND to reduce the pulse width
of the OUT output driving the main power switch of the converter.
GND
8
5
−
This pin serves as the fundamental analog ground for the PWM control circuitry. This
pin should be connected to PGND directly at the device.
LINEOV
19
16
I
This is an input pin of voltage comparator with programmable hysteresis and 1.27−V
threshold, providing LINE overvoltage or other functions.
NAME
DESCRIPTION
LINEUV
18
15
I
This pin provides a means to accurately enable/disable the power converter stage by
monitoring the bulk input voltage or another parameter. When the circuit initially starts
(or restarts from a disabled condition), a rising input on LINEUV enables the outputs
when the threshold of 1.27 V is crossed. After the circuit is enabled, then a falling
LINEUV signal disables the outputs when the same threshold is reached. The hysteresis between the two levels is programmed using an internal current source.
OUT
15
12
O
This output pin drives the main PWM switching element MOSFET in an active clamp
controller. It can directly drive an N−channel device with 2−A source turn−on current
and 2−A sink turn−off current.
PGND
13
10
−
The PGND should serve as the current return for the high−current output drivers OUT
and AUX. Ideally, the current path from the outputs to the switching devices, and back
would be as short as possible, and enclose a minimal loop area.
PVDD
16
13
I
This is the supply pin for the power devices. It is separated internally from the VDD
pin.
RSLOPE
10
7
I
A resistor connected from this pin to GND programs an internal current source that
sets the slope compensation ramp for the current mode control circuitry.
RTDEL
3
20
I
A resistor from this pin to GND programs the turn−on delay of the two gate drive outputs to accommodate the resonant transitions of the active clamp power converter.
ROFF
5
2
I
A resistor connected from this pin to GND programs an internal current source that
discharges the internal timing capacitor.
RON
4
1
I
A resistor connected from this pin to GND programs an internal current source that
charges the internal timing capacitor.
SS/SD
12
9
I
SYNC
7
4
I
VDD
17
14
I
This is the power supply for the device. There should be a 1.0−µF capacitor directly
from VDD to PGND. The capacitor value should be minimum 10 times bigger than
that on VREF. PGND and GND should be connected externally and directly from
PGND pin to GND pin.
VIN
1
18
I
This pin is connected to the input power rail directly. Inside the device, a high−voltage
start−up device is utilized to provide the start−up current for the controller until a bootstrap type bias rail becomes available.
VREF
6
3
O
This is the 5−V reference voltage that can be utilized for an external load of up to 5
mA. Since this reference provides the supply rail for internal logic, it should be bypassed to AGND as close as possible to the device. The VREF bias profile may not
be monotonic before VDD reaches 5 V.
A capacitor from SS/SD to ground is charged by an internal current source of IRON to
program the soft−start interval for the controller. During a fault condition this capacitor
is discharged by a current source equal to IRON.
The SYNC pin serves as a bidirectional synchronization input for the internal oscillator. The synchronization function is implemented such that the user programmable
maximum duty cycle (set by RON and ROFF) remains accurate during synchronized
operation. Thiis pin should be left open if not used. Its external capacitance should be
minimized. No capacitors should be connected to this pin.
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SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
DETAILED PIN DESCRIPTIONS
RDEL
This pin is internally connected to an approximately 2.5-V DC source. A resistor (RDEL) to GND sets the turn-on
delay for both gate drive signals of the UCC2987A controller. The delay time is identical for both switching
transitions, between OUT is turning off and AUX is turning on as well as when AUX is turning off and OUT is
turning on. The delay time is defined as:
t DEL1 + 1.1
ǒWSǓ
R DEL
10 *11 ) 70
10 *9
t DEL2 + 1.1
ǒWSǓ
R DEL
10 *11 ) 50
10 *9
(1)
(2)
For proper selection of the delay time refer to the various references describing the design of active clamp power
converters.
RON
This pin is internally connected to an approximately 2.5-V DC source. A resistor (RON) to GND (pin 6) sets the
charge current of the internal timing capacitor. The RON pin, in conjunction with the ROFF pin (pin 3) are used
to set the operating frequency and maximum operating duty cycle.
ROFF
This pin is internally connected to an approximately 2.5-V DC source. A resistor (ROFF) to GND (pin 6) sets the
discharge current of the internal timing capacitor. The RON and ROFF pins are used to set the switching period
(TSW) and maximum operating duty cycle (DMAX) according to the following equations:
t ON + 37.33
t OFF + 16
10 *12
10 *12
R ON
R OFF
ǒWSǓ
(3)
ǒWSǓ
(4)
T SW + t ON ) t OFF
D MAX +
8
(5)
t ON
T SW
(6)
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SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
DETAILED PIN DESCRIPTIONS (continued)
VREF
The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a high quality
ceramic bypass capacitor (CVREF) to GND for noise filtering and to provide compensation to the regulator
circuitry. The recommended CVREF value is 0.22-µF and X7R capacitors are recommended. The minimum
bypass capacitor value is 0.022-µF limited by stability considerations of the bias regulator, while the maximum
is approximately 22-µF. The capacitance on VREF and VDD should be in a minimum ratio of 1:10.
The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias
is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC2897A controller.
The VREF bias profile may not be monotonic before VDD reaches 5.0 V.
For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional
Description section of this datasheet.
SYNC
This pin is a bi-directional synchonization terminal. This pin should be left open if not used.
This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator
of the UCC2897A controller. The synchronizing frequency must be higher than the free running frequency of
the onboard oscillator ǒT SYNC t T SWǓ. The acceptable minimum pulse width of the synchronization signal is
approximately 50 ns (positive logic), and it should remain shorter than ǒ1 * D MAXǓ T SYNC where DMAX is set
by RON and ROFF. If the pulse width of the synchronization signal stays within these limits, the maximum
operating duty ratio remains valid as defined by the ratio of RON and ROFF, and DMAX is the same in free running
and in synchronized modes of operation. If the pulse width of the synchronization signal would exceed the
ǒ1 * DMAXǓ T SYNC limit, the maximum operating duty cycle is defined by the synchronization pulse width.
In the stand-alone mode, the sync pin is driven by the internal oscillator which provides output pulses. The pulse
width from SYNC output does not vary with the duty cycle. That signal can be use to synchronize other PWM
controllers or circuits needing a constant frequency time base.
External capacitance should be minimized on this pin layout. There should be no capacitors connected between
this pin and GND or PGND. For more information on synchronization of the UCC2897A refer to the Functional
Description section of this datasheet.
GND
This pin provides a reference potential for all small signal control and programming circuitry inside the
UCC2897A. Ground layout is critical for correct operation. High current surges from the MOSFET drivers
conduct through PVDD, OUT, AUX, and PGND. To localize these surges, PVDD must be bypassed directly to
PGND. PGND current must be electrically, capacitively, and inductively isolated from GND with only one short
trace connecting PGND to GND, located to best minimize noise into GND.
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SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
DETAILED PIN DESCRIPTIONS (continued)
CS
This is a direct input to the PWM and current limit comparators of the UCC2897A controller. The CS pin should
never be connected directly across the current sense resistor (RCS) of the power converter. A small, customary
R−C filter between the current sense resistor and the CS pin is necessary to accommodate the proper operation
of the onboard slope compensation circuit and in order to protect the internal discharge transistor connected
to the CS pin (RF, CF).
Slope compensation is achieved across RF by a linearly increasing current flowing out of the CS pin. The slope
compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT)
of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the
timing capacitor. This time interval is ǒ1 * D MAXǓ T SW long and represents the guaranteed off time of the
main power switch.
RSLOPE
A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation
current. During the on time of the main gate drive output (OUT) the voltage across RSLOPE is a representation
of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across RSLOPE
also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope
compensation is proportional to this current flowing through RSLOPE.
Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and
inductance of the external circuit components connected to the RSLOPE pin should be carefully minimized.
For more information on how to program the internal slope compensation refer to the Setup Guide section of
this datasheet.
FB
FB and SS/SD interact. The one with the lower voltage value takes control on the duty cycle, refer to SS/SD
description. This pin is an input for the control voltage of the pulse width modulator of the UCC2897A. The control
voltage is generated by an external error amplifier by comparing the converters output voltage to a voltage
reference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is located
on the secondary side of the isolated power converter and its output voltage is sent across the isolation
boundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistor
to the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry.
The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to
make it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin is
between approximately 2.5 V and 4.5 V. Control voltages below the 2.5-V threshold result in zero duty cycle
(pulse skipping) while voltages above 4.5 V result in full duty cycle (DMAX) operation.
10
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SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
DETAILED PIN DESCRIPTIONS (continued)
SS/SD
A capacitor (CSS) connected between this pin and GND (pin 6) programs the soft start time of the power
converter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed by
the RON resistor connected to pin 2. The soft-start current is defined as:
I SS + 0.43
I RON + 0.43
V REF
2
1
R ON
(7)
This DC current charges CSS from 0 V to approximately 5 V. Internal to the UCC2897A, the soft−start capacitor
voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lower of the two voltages
manipulates the controller’s PWM engine through the voltage divider described with regards to the FB pin.
Accordingly, the useful control range on the SS pin is similar to the control range of the FB pin and it is between
2.5 V and 4.5 V approximately. During line undervoltage protection, the PWM follows this pin capacitor
discharge to achieve soft stop funtion.
PGND
This pin serves as a dedicated connection to all high-current circuits inside the UCC2897A. The high-current
portion of the controller consists of the two high-current gate drivers, and the various bias connections except
VREF (pin 4). The PGND (pin 11) and GND (pin 6) pins are not connected internally, a low-impedance, external
connection between the two ground pins is also required. It is recommended to form a separate ground plane
for the low current setup components (RDEL, RON, ROFF, CVREF, CF, RSLOPE, CSS and the emitter of the
opto-coupler in the feedback circuit). This separate ground plane (GND) should have a single connection to the
rest of the ground of the power converter (PGND) and this connection should be between pin 6 and pin 11 of
the controller.
AUX
This is a high-current gate drive output for the auxiliary switch to implement the active clamp operation for the
power stage. The auxiliary output (AUX) of the UCC2897A drives a P-channel device as the clamp switch
therefore it requires an active low operation (the switch is ON when the output is low).
OUT
This high-current output drives an external N-channel MOSFET. The UCC2897A controller uses an active high
drive signal for the main switch of the converter.
Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance
of the external circuit components connected to these pins should be carefully minimized. A potential way of
avoiding unnecessary parasitic inductances in the gate drive circuit is to place the controller in close proximity
to the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices are
connected by wide, overlapping traces.
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DETAILED PIN DESCRIPTIONS (continued)
VDD
The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator and
for parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramic
capacitor (CHF) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate
filtering. The recommended CHF value is 1-µF for most applications but its value might be affected by the
properties of the external MOSFET transistors used in the power stage.
In addition to the low-impedance, high-frequency filtering, the controller’s bias rail requires a larger value energy
storage capacitor (CBIAS) connected parallel to CHF. The energy storage capacitor must provide the hold up time
to operate the UCC2897A (including gate drive power requirements) during start up. In steady state operation
the controller must be powered from a bootstrap winding off the power transformer or by an auxiliary bias supply.
In case of an independent auxiliary bias supply, the energy storage is provided by the output capacitance of the
bias supply. The capacitor values are also determined by the capacitor values connected to VREF. The
capacitance on VREF and VDD should be in a minimum ratio of 1:10.
LINEUV
This input monitors the incoming power source to provide an accurate undervoltage lockout function with user
programmable hysteresis for the power supply controlled by the UCC2897A. The unique property of the
UCC2897A is to use only one pin to implement these functions without sacrificing on performance. The input
voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage lockout comparator
by an external resistor divider (RIN1, RIN2 in Figure 7). Once the line monitor’s input threshold is exceeded, an
internal current source gets connected to the LINEUV pin. The current generator is programmed by the RDEL
resistor connected to pin 1 of the controller. The actual current level is given as:
I HYST +
V REF
2
1
R DEL
0.05
(8)
As this current flows through RIN2 of the input divider, the undervoltage lockout hysteresis is a function of IHYST
and RIN2 allowing accurate programming of the hysteresis of the line monitoring circuit. When LINEUV is
detected, PWM follows VSS capacitor discharge and soft stop function is provided. The soft−start capacitor
starts discharging when the soft−start capacitor voltage reaches 2.5 V. Both OUT and AUX stop switcing while
soft−start capacitor continues discharging until its voltage reaches 0.5 V when the soft start is resumed on the
assumption of all other soft start conditions are met.
For more information on how to program the line monitoring function refer to the Setup Guide of this datasheet.
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DETAILED PIN DESCRIPTIONS (continued)
VIN
The UCC2897A controller is equipped with a high voltage, P-channel JFET start up device to initiate operation
from the input power source of the converter in applications where the input voltage does not exceed the 110-V
maximum rating of the start up transistor. In these applications, the VIN pin can be connected directly to the
positive terminal of the input power source. The internal JFET start up transistor provides approximately 15-mA
charge current for the energy storage capacitor (CBIAS) connected across the VDD (pin 14) and PGND (pin 11)
terminals. Note that the start up device is turned off immediately when the voltage on the VDD pin exceeds
approximately 12.7 V, the controller’s undervoltage lockout threshold for turn-on. The JFET is also disabled at
all times when the high-current gate drivers are switching to protect against excessive power dissipation and
current through the device. For dependable startup, VDD must not be loaded by more than 4 mA.
For more information on biasing the UCC2897A, refer to the Setup Guide and Additional Application Information
Sections of this datasheet.
LINEOV
This input monitors the incoming power source to provide an accurate overvoltage protection with user
programmable hysteresis for the power supply controlled by the controller. The circuit implementation of the
overvoltage protection function is identical to the technique used for monitoring the input power rail for
undervoltage lockout. This allows implementing an accurate threshold and hysteresis using only one pin. The
input voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltage protection
comparator by an external resistor divider (RIN3, RIN4 in Figure 7). Once the line monitor’s input threshold is
exceeded, an internal current source gets connected to the LINEOV pin. The current generator is programmed
by the RDEL resistor connected to pin 1 of the controller. The actual current level is given as:
I HYST +
V REF
2
1
R DEL
0.05
(9)
As this current flows through RIN4 of the input divider, the overvoltage protection hysteresis is a function of IHYST
and RIN4 allowing accurate programming of the hysteresis of the line monitoring circuit.
For more information on how to program the overvoltage protection, refer to the Setup Guide of this datasheet.
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FUNCTIONAL DESCRIPTION
JFET Control and UVLO
The UCC2897A controller includes a high voltage JFET start up transistor. The steady state power consumption
of the of the control circuit which also includes the gate drive power loss of the two power switches of an active
clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should only be used
for initial start up of the control circuitry and to provide keep-alive power during stand-by mode when the gate
drive outputs are not switching. Accordingly, the start-up device is managed by its own control algorithm
implemented on board the UCC2897A. The following timing diagram illustrates the operation of the JFET start
up device.
V ON
V IN
12.7V
10.0V
8V <VDD < 10V
8.0V
Bootstrap bias
V DD
OFF
JFET
OFF
OFF
ENABLE
(See diagram on p.6)
SS/SD
OUTPUTs
OFF
OFF
SWITCHING
SWITCHING
OFF
UDG−03148
Figure 2. JFET Control Startup and Shutdown
Note: Values are typical in the drawing.
During initial power up the JFET is on and charges the CBIAS and CHF capacitors connected to the VDD pin.
The VDD pin is monitored by the controller’s undervoltage lockout circuit to ensure proper biasing before the
operation is enabled. When the VDD voltage reaches approximately 12.7 V (UVLO turn-on threshold) the UVLO
circuit enables the rest of the controller. At that time, the JFET is turned off and 5 V appears on the VREF
terminal. Switching waveforms might not appear at the gate drive outputs unless all other conditions of proper
operation are met. These conditions are:
D the voltage on the CS pin is below the current limit threshold
D the control voltage is above the zero duty cycle boundary (VFB > 2.5 V)
D the input voltage is in the valid operating range (VVON<VVIN<VVOFF) i.e. the line under or overvoltage
protections are not activated.
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FUNCTIONAL DESCRIPTION
As the controller starts operation it draws its bias power from the CBIAS capacitor until the bootstrap winding
takes over (refering to Figure 10 and Figure 11). During this time VDD voltage is falling rapidly as the JFET is
already off but the bootstrap voltage is still not sufficient to power the control circuits. It is imperative to store
enough energy in CBIAS to prevent the bias voltage to dip below the turn off threshold of the UVLO circuit during
the start up time interval. Otherwise the power supply goes through several cycles of retry attempts before
steady state operation might be established.
During normal operation the bias voltage is determined by the bootstrap bias design. The UCC2897A can
tolerate a wide range of bias voltages between the minimum operating voltage (UVLO turn-off threshold) and
the absolute maximum operating voltage as defined in the datasheet (16.5 V).
In applications where the power supply must be able to go to stand by in response to an external command,
the bias voltage of the controller must be kept alive to be able to react intelligently to the control signal. In stand
by mode, switching action is suspended for an undefined period of time and the bootstrap power is unavailable
to bias the controller. Without an alternate power source the bias voltage would collapse and the controller would
initiate a re-start sequence. To avoid this situation, the on board JFET of the UCC2897A controller can keep
the VDD bias alive as long as the gate drive outputs remain inactive. As shown in the timing diagram in Figure
2, the JFET is turned on when VDD = 10 V and charges the CBIAS capacitor to approximately 12.7 V. At that
time the JFET turns off and VDD gradually decreases to 10 V then the procedure is repeated. When the power
supply is enabled again, the controller is fully biased and ready to initiate its soft start sequence. As soon as
the gate drive pulses appear the JFET are turned off and bias must be provided by the bootstrap bias generator.
During power down the situation is different as switching action might continue until the VDD bias voltage drops
below the controller’s own UVLO turn-off threshold (approximately 8 V). At that time the UCC2897A shuts down
completely turning off its 5 V bias rail and returning to start up state when the JFET device is turned on and the
CBIAS capacitor starts charging again. In case the converter’s input voltage is re-established, the UCC2897A
attempts to restart the converter.
Line Undervoltage Protection
As shown in Figure 3, when the input power source is removed the power supply is turned off by the line
undervoltage protection because the bootstrap winding keeps the VDD bias up as long as switching takes place
in the power stage. As the power supply’s input voltage gradually decreases towards the line cut off voltage the
converter’s operating duty cycle must compensate for the lower input voltage. At minimum input voltage the duty
cycle nears its maximum value (DMAX). Under these conditions the voltage across the clamp capacitor
approaches its highest value since the transformer must be reset in a relatively short time. The timing diagram
in Figure 3 highlights that in the instance when the converter stops switching the clamp capacitor voltage might
be at its maximum level. Since the clamp capacitor’s only load is the power transformer, this high voltage could
linger across the clamp capacitor for a long time when the converter is off. With this high voltage present across
the clamp capacitor a soft start would be very dangerous, due to the narrow duty cycle of the main switch and
the long on-time of the clamp switch. This could cause the power transformer to saturate during the next
soft-start cycle.
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SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
FUNCTIONAL DESCRIPTION
VOFF
VIN
V CLAMP, MAX
VCLAMP
VSS
TSW
OUT
AUX
Figure 3. Line Undervoltage Shutdown Waveforms
To eliminate this potential hazard the UCC2897A controller safely discharge the clamp capacitor during power
down. The OUT and the AUX output continues switching while the soft-start capacitor CSS is being slowly
discharged. Notice that the AUX pulse width gradually increases as the clamp voltage decreases never applying
the high voltage across the transformer for extended period of time. From this, the function of soft stop is
achieved.
Line Overvoltage Protection
When the line overvoltage protection is triggered in the UCC2897A controller, the gate drive signals are
immediately disabled. At the same time, the slow discharge of CSS is initiated. While the soft-start capacitor is
discharging the gate drive signals remains disabled. Once VSS = 0.5 V and the overvoltage disappears from
the input of the power supply, operation resumes through a regular soft-start of the converter as it is
demonstrated in Figure 4. The pulses of OUT and AUX stop if one of three conditions is met:
1. VDD reaches UVLO off,
2. VSS reaches below 2.5 V,
3. or FB voltage is below 2.5 V.
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FUNCTIONAL DESCRIPTION
VOVP
VOVH
VIN
VSS
OUT
AUX
Figure 4. Line Overvoltage Sequence
Pulse Skipping
During output load current transients or light load conditions most PWM controllers needs to be able to skip
some number of PWM pulses. In an active clamp topology where the clamp switch is driven complementarily
to the main switch, this would apply the clamp voltage across the transformer continuously. Since operating
conditions might require skipping several switching cycles on the main transistor, saturating the transformer is
very likely if the AUX output stays on.
D = 0 Boundary
2.5 V
FB
TSW
OUT
AUX
Figure 5. Pulse Skipping Operation
To overcome this problem, the UCC2897A family incorporates pulse skipping for both outputs in the controller.
As can be seen above, when a pulse is skipped at the main output (OUT) because the feedback signal demands
zero duty ratio, the corresponding output pulse on the AUX output is omitted as well. This operation allows to
prevent reverse saturation of the power transformer and to preserve the clamp capacitor voltage level during
pulse skipping operation.
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FUNCTIONAL DESCRIPTION
Synchronization
The UCC2897A has a bi-directional synchronization pin. In the stand-alone operation the SYNC pin is driven
by the internal oscillator of the UCC2897A which provides an approximately 5-V amplitude square wave output.
This signal can be used to synchronize other PWM controllers or circuits needing a constant frequency time
base. The synchronization output of the UCC2897A is generated when the internal timing capacitor reaches
its peak value. Therefore, the synchronization waveform does not coincide with the turn on of the main gate
driver output as it is usually implemented in PWM controllers.
The operation of the oscillator and relevant other waveforms in free running and synchronized mode are shown
in Figure 6.
SYNC
C
D
T
MAX
OUT
AUX
Figure 6. ASynchronization Waveform for SYNC Input
The most critical and unique feature of the oscillator is to limit the maximum operating duty cycle of the converter.
It is achieved by accurately controlling the charge and discharge intervals of the on board timing capacitor. The
maximum on-time of OUT pin, which is also the maximum duty cycle of the active clamp converter is limited
by the charging interval of the timing capacitor. While the capacitor is being reset to its initial voltage level OUT
is guaranteed to be off.
When synchronization is used, the rising edge of the signal terminates the charging period and initiate the
discharge of the timing capacitor. Once the timing capacitor voltage reaches the predefined valley voltage, a
new charge period starts automatically. This method of synchronization leaves the charge and discharge slopes
of the timing waveform unaffected thus maintains the maximum duty cycle of the converter, independent of the
mode of operation.
Although the synchronization circuit is level sensitive, the actual synchronization event occurs at the rising edge
of the waveform. This allows the synchronizing pulse width to vary significantly but certain limitations must be
observed. The minimum pulse width should be sufficient to guarantee reliable triggering of the internal oscillator
circuitry, therefore it should be greater than approximately 50 nanoseconds. The other limiting factor is to keep
it shorter than ǒ1 * D MAXǓ T SYNC where TSYNC is the period of the synchronization frequency.
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FUNCTIONAL DESCRIPTION
When a wider than ǒ1 * D MAXǓ T SYNC pulse is connected to the SYNC input, the oscillator is not able to
maintain the maximum duty cycle, originally set by the timing resistor ratio (RON, ROFF). Furthermore, the timing
capacitor waveform has a flat portion as highlighted by the vertical marker in the timing diagram. During this
flat portion of the waveform both outputs is off which state is not compatible with the operation of active clamp
power converters. Therefore, this operating mode is not recommended .
Note that both outputs of the UCC2897A controller are off if the synchronization signal stays continuously high.
When two UCC2897A’s are synchronized by tying their SYNC pins together, they will operate in−phase. It is
possible to set different maximum duty cycle limits for the two UCC2897’s and still synchronize them by a simple
connection between their respective SYNC terminals.
APPLICATION INFORMATION: SETUP GUIDE
RIN2
RIN1
+VIN
RIN3
RIN4
UCC2897A
1
VIN
N/C
20
2
N/C
LINEOV 19
3
RDEL
LINEUV 18
CBIAS
RDEL
VDD
17
4
RON
5
ROFF
PVDD
16
6
VREF
OUT
15
7
SYNC
AUX
14
8
GND
PGND
13
9
CS
SS/SD
12
FB
11
POWER STAGE
CHF
RON
ROFF
CVREF
−VIN
CF
RSLOPE
10
RSLOPE
CSS
RF
RVREF
ISOLATED FEEDBACK
Figure 7. UCC2897A Typical Setup
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APPLICATION INFORMATION: SETUP GUIDE
The UCC2897A family offers a highly integrated feature set and excellent accuracy to control an active clamp
forward or active clamp flyback power converter. In order to take advantage of all the benefits integrated in these
controllers, the following procedure can simplify the setup and avoid unnecessary iterations in the design
procedure. Refer to Figure 7 setup diagrams for component names.
Before the controller design begins, the power stage design must be completed. From the power stage design
the following operating parameters are needed to complete the setup procedure of the controller:
D
D
D
D
D
D
D
D
D
D
D
Switching frequency (fSW)
Maximum operating duty cycle (DMAX)
Soft start duration (tSS)
Gate drive power requirements of the external power MOSFETs (QG(main), QG(aux))
Bias method and voltage for steady state operation (bootstrap or bias supply)
Gate drive turn-on delay (tDEL)
Turn−on input voltage threshold (VON)
Minimum operating input voltage (VOFF) where VIN (off) < VIN(on)
Maximum operating input voltage (VOVP)
overvoltage protection hysteresis (VOVH)
The down slope of the output inductor current waveform reflected across the primary side current sense
resistor ǒdV LńdtǓ
Step 1. Oscillator
The two timing elements of the oscillator can be calculated from fSW and DMAX by the following two equations:
R ON +
t ON
37.33
R OFF +
10 *12
t OFF
16
10 *12
ǒWs Ǔ + f
ǒWs Ǔ + f
D MAX
SW
37.33
10 *12
1 * D MAX
SW
16
10 *12
ǒWs Ǔ
ǒWs Ǔ
(10)
(11)
where DMAX is a dimensionless number between 0 and 1.
Step 2. Soft Start
Once RON is defined, the charge current of the soft-start capacitor can be calculated as:
I SS + 0.43
V REF
2
1
R ON
(12)
During soft start, CSS is being charged from 0 V to 5 V by the calculated ISS current. The actual control range
of the soft-start capacitor voltage is between 2.5 V and 4.5 V. Therefore, the soft-start capacitor value must be
based on this narrower control range and the required start up time (tSS) according to:
C SS +
20
I SS t SS
4.5 V * 2.5 V
(13)
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APPLICATION INFORMATION: SETUP GUIDE
Note, that tSS defines a time interval to reach the maximum current capability of the converter and not the time
required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme
does not allow accurate control over the ramp up time of the output voltage. In addition to the ISS and CSS values,
the time required to reach the nominal output voltage of the converter is a function of the maximum output
current (current limit), the output capacitance of the converter and the actual load conditions. If it is critical to
implement a tightly controlled ramp-up time at the output of the converter, the soft-start must be implemented
using a closed loop technique. Closed loop soft-start can be implemented with the error amplifier of the voltage
regulation loop when its voltage reference is ramped from 0 V to its final steady state value during the required
tSS start up time interval.
Step 3. VDD Bypass Requirements
First, the high-frequency filter capacitor is calculated based on the gate charge parameters of the external
MOSFETs. Assuming that the basic switching frequency ripple should be kept below 0.1-V across CHF, its value
can be approximated as:
C HF +
Q G(main) ) Q G(aux)
(14)
0.1 V
The energy storage requirements are defined primarily by the start up time (tSS) and turn-on (approximately
12.7 V) and turn-off (approximately 8 V) thresholds of the controller’s undervoltage lockout circuit monitoring
the VDD pin. In addition, the bias current consumption of the entire primary side control circuit (IDD + IEXT) must
be known. This power consumption can be estimated as:
ƪ
ǒ
P BIAS + I DD ) I EXT ) Q G(main) ) Q G(aux)
Ǔƫ
f SW
V DD
(15)
During start up (tSS) this power is provided by CBIAS while its voltage must remain above the UVLO turn-off
threshold. This relationship can be expressed as:
P BIAS
t SS t 1
2
C BIAS
ǒ13.5 2 * 8 2Ǔ
(16)
Rearranging the equation yields the minimum value for CBIAS:
C BIAS u
2
P BIAS
t SS
2
2
ǒ13.5 * 8 Ǔ
(17)
Equation 17 may yeild a big capacitance value that may not be feasible in some applications. In such cases,
an additional energy storage circuit. A smaller footprint may be designed to ease the space demand. Refer to
the Application Note for such a design.
Step 4. Delay Programming
From the power stage design, the required turn-on delay (tDEL) of the gate drive signals is defined. The
corresponding RDEL resistor value to implement this delay is given by:
R DEL + ǒt DEL1 * 70
10 *9Ǔ
0.91
10 11
ǒWs Ǔ
(18)
R DEL + ǒt DEL2 * 50
10 *9Ǔ
0.91
10 11
ǒWs Ǔ
(19)
or
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APPLICATION INFORMATION: SETUP GUIDE
Step 5. Input Voltage Monitoring
The input voltage monitoring functions is governed by the following two expressions of the voltage at the
LINEUV pin:
V LINEUV + V ON
R IN2
at turn on, and
R IN1 ) R IN2
R IN2
) I HYST
R IN1 ) R IN2
V LINEUV + V OFF
R IN1 R IN2
at turn off.
R IN1 ) R IN2
(20)
(21)
Since VON and VOFF are given by the power supply specification, VLINEUV equals the 1.27-V threshold of the
line monitor and IHYST is already defined as:
I HYST +
V REF
2
1
R DEL
0.05
(22)
the two unknown, RIN1 and RIN2 are fully determined.
Step 6. Current Sense and Slope Compensation
The UCC2897A offers onboard, user programmable slope compensation. The programming of the right amount
of slope compensation is accomplished by the appropriate selection of two external resistors, RF and RSLOPE.
First, the current sense filter resistor value (RF) must be calculated based on the desired filtering of the current
sense signal. The filter consists of two components, CF and RF. The CF filter capacitor is connected between
the CS pin and the GND pin. While the value of CF can be freely selected as the first step of the filter design,
it should be minimized to avoid filtering the slope compensation current exiting the CS pin. The recommended
range for the filter capacitance is between 50 pF and 270 pF. The value of the filter resistor can be calculated
from the filter capacitance and the desired filter corner frequency fF.
RF +
2p
1
fF
CF
(23)
After RF is defined RSLOPE can be calculated. The amount of slope compensation is defined by the stability
requirements of the inner peak current loop of the control algorithm and is measured by the number m. When
the slope of the applied compensation ramp equals the down slope of the output inductor current waveform
reflected across the primary side current sense resistor ǒdV LńdtǓ, m equals 1. The minimum value of m is 0.5
to prevent current loop instability. Best current mode performance can be achieved around m=1. The further
increase of m moves the control closer to voltage mode control operation.
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APPLICATION INFORMATION: SETUP GUIDE
In the UCC2897A controllers, slope compensation is implemented by sourcing a linearly increasing current at
the CS pin. When this current passes through the current sense filter resistor (RF), it is converted to a slope
compensation ramp which can be characterized by its ǒdV SńdtǓ. The ǒdV SńdtǓ of the slope compensation
current is defined by RSLOPE according to:
dI S
5 2V
+
t ON R SLOPE
dt
(24)
where
D 2V is the peak−to−peak ramp amplitude of the internal oscillator waveform
D 5 is the multiplication factor of the internal current mirror
The voltage equivalent of the compensation ramp ǒdV SńdtǓ can be easily obtained by multiplying with RF. After
introducing the application specific m and ǒdV LńdtǓ values, the equation can be rearranged for RSLOPE:
5
R SLOPE +
2V
t ON
m
RF
ǒ Ǔ
dV L
dt
(25)
+VIN
Load
Bootstrap
Bias
CCLAMP
VIN
VDD
AUX
UCC2897A
QAUX
Drive
Connection
CIN
Synchronous
Rectifier
Control
QMAIN
OUT
CBIAS
CS
RCS
GND
FB
Secondary−Side
Error Amplifier
and Isolation
−VIN
Figure 8. Active Clamp Forward Converter
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ADDITIONAL APPLICATION INFORMATION
Gate Drive Connection
The low side P-channel gate drive circuit involves a level shifter using a capacitor and a diode which ensures
that the gate drive amplitude of the auxiliary switch is independent of the actual duty cycle of the converter.
Detailed analysis and design examples of these and many similar gate drive solutions are given in reference [6].
+VIN
CCLAMP
QAUX
QMAIN
AUX
P
Figure 9. Low-Side P-Channel
Bootstrap Biasing
Many converters use a bootstrap circuit to generate its own bias power during steady state operation. The
popularity of this solutions is justified by the simplicity and high efficiency of the circuit. Usually, bias power is
derived from the main transformer by adding a dedicated, additional winding to the structure. Using a flyback
converter as shown in Figure 10, a bootstrap winding provides a quasi-regulated bias voltage for the primary
side control circuits. The voltage on the VDD pin is equal to the output voltage times the turns ratio between
the output and the bootstrap windings in the transformer. Since the output is regulated, the bias rail is regulated
as well.
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ADDITIONAL APPLICATION INFORMATION
While the same arrangement can be used in a forward type converter, the bootstrap winding off the main power
transformer would not be able to provide a quasi-regulated voltage. In the forward converter, the voltage across
the bootstrap winding equals the input voltage times the turns ratio. Accordingly the bias voltage would vary with
the input voltage and most likely would exceed the maximum operating voltage of the control circuits at high
line. A linear regulator can be used to limit and regulate the bias voltage if the power dissipation is acceptable.
Another possible solution for the forward converter is to generate the bias voltage from the output inductor as
shown in Figure 11.
Bootstrap Bias 1
+VIN
LOAD
VIN
VDD
CIN
UCC2897A
CBIAS
GND
Synchronous
Rectifier
Control
QMAIN
−VIN
Figure 10. Bootstrap Bias 1, Flyback Example
This solution uses the regulated output voltage across the output inductor during the freewheeling period to
generate a quasi-regulated bias for the control circuits.
Bootstrap Bias 2
+VIN
LOAD
VIN
VDD
UCC2897A
GND
CIN
CBIAS
Synchronous
Rectifier
Control
QMAIN
−VIN
Figure 11. Bootstrap Bias 2, Forward Example
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ADDITIONAL APPLICATION INFORMATION
This solution uses the regulated output voltage across the output inductor during the freewheeling period to
generate a quasi-regulated bias for the control circuits.
Both of the illustrated solution provides reliable bias power during normal operation. Note that in both cases,
the bias voltages are proportional to the output voltage. This nature of the bootstrap bias supply causes the
converter to operate in a hiccup mode under significant overload or under short-circuit conditions as the
bootstrap winding is not able to hold the bias rail above the undervoltage lockout threshold of the controller.
Another biasing solution, based on the active circuit shown on the previous page with components Q10, C18,
R19, D10 and D12. Such a circuit may be used in the applications where the allowed biasing capacitor size is
limited to optimize the board spaceutilization.
References and Additional Development Tools
1. Evaluation Module: UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset.
2. User’s Guide: Using the UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset,
(SLUU178)
3. Application Note: Designing for High Efficiency with the UCC2891 Active Clamp PWM Controller, Steve
Mappus (SLUA303)
4. Power Supply Design Seminar Topic: Design Considerations for Active Clamp and Reset Technique, D.
Dalal, SEM1100−Topic3 (SLUP112)
5. Power Supply Design Seminar Topic: Active Clamp and Reset Technique Enhances Forward Converter
Performance, B. Andreycak, SEM1000−Topic 3. (SLUP108)
6. Power Supply Design Seminar Topic: Design and Application Guide for High Speed MOSFET Gate Drive
Circuits, L. Balogh, SEM1400−Topic 2 (SLUP169)
7. Datasheet: UCC3580, Single Ended Active-Clamp/Reset PWM Controller, (SLUS292)
8. Evaluation Module: UCC3580EVM, Flyback Converters, Active Clamp vs. Hard−Switched.
9. Reference Designs: Highly Efficient 100W Isolated Power Supply Reference Design Using UCC3580−1.
Texas Instruments Hardware Reference Design Number PMP206.
10. Reference Designs: Active Clamp Forward Reference Design using UCC3580−1. Texas Instruments
Hardware Reference Design Number PMP368
26
www.ti.com
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
+
+
ADDITIONAL APPLICATION INFORMATION
www.ti.com
27
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
TYPICAL CHARACTERISTICS
UVLO VOLTAGE THRESHOLDS
vs
JUNCTION TEMPERATURE
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
2.5
12
UVLO On
IDD − Supply Current − mA
VUVLO − UVLO Voltage Thresholds − V
14
10
8
UVLO Off
6
UVLO Hysteresis
4
2.0
1.5
1.0
0.5
2
0
−50
0
−25
0
25
50
75
100
125
0
4
2
TJ − Junction Temperature − °C
6
8
10
12
VDD − Supply Voltage − V
Figure 12
14
16
Figure 13
TYPICAL STARTUP CURRENT AVAILABLE FROM VDD
vs
TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10
20
VIN = 36 V
External VDD Current − mA
IDD − Supply Current − mA
0
−10
−20
−30
JFET Source Current
15
10
5
−40
0
−50
0
2
4
6
8
10
12
VDD − Supply Voltage − V
14
16
Figure 14
28
−50
−25
0
25
50
TJ − Junction Temperature − °C
Figure 15
www.ti.com
75
100
125
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
TYPICAL CHARACTERISTICS
VTH − Line Thresholds − V
1.28
1.26
1.24
1.22
1.20
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
15
Softstart Discharge Current
10
5
0
−5
−10
−15
−20
−50
125
Softstart Charge Current
−25
0
25
50
75
100
125
TJ − Junction Temperature − °C
Figure 17
Figure 16
SOFTSTART/SHUTDOWN THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SWITCHING FREQUENCY
vs
PROGRAMMING RESISTANCE
10 M
0.60
0.58
0.56
fSW − Switching Frequency − Hz
VTH − Softstart/Shutdown Threshold Voltage − V
SOFTSTART CURRENTS
vs
TEMPERATURE
20
ISS(DIS)/ISS(CHG)− Softstart Currents−µA
1.30
LINE UV/OV VOLTAGE THRESHOLD
vs
JUNCTION TEMPERATURE
0.54
0.52
0.50
0.48
0.46
0.44
1M
100 K
10 K
0.42
0.40
−50
−25
0
25
50
75
100
125
TJ − Junction Temperature − °C
1K
10
100
RON = ROFF − Timing Resistance − kΩ
1000
Figure 19
Figure 18
www.ti.com
29
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
74
275
RON = ROFF = 75 kΩ
RON = ROFF = 75 kΩ
73
265
DMAX− Maximum Duty Cycle − %
fSW − Switching Frequency − kHz
270
260
255
250
245
240
235
71
70
69
68
67
230
225
−50
72
−25
0
25
50
75
100
TJ − Junction Temperature − °C
66
−50
125
−25
0
25
50
75
100
125
TJ − Junction Temperature − °C
Figure 20
Figure 21
CURRENT SENSE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
SYNCHRONIZATION THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
1.4
VSYNC − Synchronization Threshold Voltage − V
VCS − Current Sense Threshold Voltage − V
2.50
1.2
1.0
0.8
Hiccup Mode
0.6
0.4
Cycle-by-Cycle Current Limit
0.2
0
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
125
2.40
2.35
2.30
2.25
2.20
2.15
2.10
−50
−25
0
25
50
75
100
TJ − Junction Temperature − °C
Figure 22
30
2.45
Figure 23
www.ti.com
125
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
TYPICAL CHARACTERISTICS
DELAY TIME
vs
DELAY RESISTANCE
OUT AND AUX RISE AND FALL TIME
vs
JUNCTION TEMPERATURE
700
25
CLOAD = 2 nF
600
500
15
tDEL− Delay Time − ns
tR/tF − Rise and Fall Times − ns
Rise Time
20
Fall Time
10
400
300
200
5
100
0
−50
0
−25
0
25
50
75
100
TJ − Junction Temperature − °C
10
0
125
20
30
40
RDEL − Delay Resistance − kΩ
50
Figure 25
Figure 24
DELAY TIME
vs
JUNCTION TEMPERATURE
DELAY TIME
vs
JUNCTION TEMPERATURE
250
800
RDEL = 10 kΩ
RDEL = 50 kΩ
700
200
tDEL− Delay Time − µs
tDEL− Delay Time − ns
600
OUT to AUX
150
100
500
AUX to OUT
OUT to AUX
400
300
200
AUX to OUT
50
100
0
−50
−25
0
25
50
75
100
125
0
−50
−25
0
25
50
75
100
125
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 26
Figure 27
www.ti.com
31
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
REFERENCE VOLTAGE
vs
TEMPERATURE
5.3
No Load
10 mA Load
VREF − Reference Voltage − V
5.2
5.1
5.0
4.9
4.8
4.7
−50
−25
0
25
50
75
100
125
TJ − Junction Temperature − °C
Figure 28
32
www.ti.com
SLUS829B − AUGUST 2008 − REVISED DECEMBER 2008
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
www.ti.com
33
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UCC2897APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
UCC2897ARGPR
QFN
RGP
20
3000
330.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
UCC2897ARGPT
QFN
RGP
20
250
180.0
12.4
4.3
4.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC2897APWR
TSSOP
PW
20
2000
346.0
346.0
33.0
UCC2897ARGPR
QFN
RGP
20
3000
346.0
346.0
29.0
UCC2897ARGPT
QFN
RGP
20
250
190.5
212.7
31.8
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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