CHERRY CS5165HGDW16

CS5165H
CS5165H
Fast, Precise 5-Bit Synchronous Buck Controller
for the Next Generation Low Voltage Pentium® II Processors
Features
Description
The CS5165H protects the processor during potentially catastrophic events like
overvoltage (OVP) and short circuit. The
OVP feature is part of the V2™ architecture and does not require any additional
components. During short circuit, the
controller pulses the MOSFETs in a “hiccup” mode (3% duty cycle) until the fault
is removed. With this method, the
MOSFETs do not overheat or self
destruct.
The CS5165H is designed for use in both
single processor desktop and multiprocessor workstation and server applications. The IC can be powered from either
single or dual 5V, 12V power supplies.
The CS5165H’s current sharing capability
allows the designer to build multiple parallel and redundant power solutions for
multiprocessor systems.
The CS5165H contains other control and
protection features such as Power Good,
ENABLE, and adaptive voltage positioning. It is available in a 16 lead SOIC wide
body package.
The CS5165H synchronous 5-bit NFET
buck controller is optimized to manage
the power of the next generation
Pentium®II processors. It’s V2™ control
architecture delivers the fastest transient
response (100ns), and best overall voltage
regulation in the industry today. It’s feature rich design gives end users the maximum flexibility to implement the best
price/performance solutions for their end
products.
The CS5165H has been carefully crafted
to maximize performance and protect the
processor during operation. It has a 5-bit
DAC on board that holds a ±1% tolerance
over temperature. Its on board programmable soft start insures a control
start up, and the FET nonoverlap circuitry ensures that both FETs do not conduct
simultaneously.
The on board oscillator can be programmed up to 1MHz to give the designer maximum flexibility in choosing external components and setting systems
costs.
5V to 2.8V @ 14.2A for 300MHz Pentium®II
5V
1200µF/10V x 3
1µF
VCC
SS
0.1µF
0.1 µF
330pF
COMP
1200µF
10V x 5
GATE(L)
CS5165H
VID3
PGnd
VID2
LGnd
VID1
VFB
VID0
PCB
1.2µH trace 6mΩ
■
■
■
■
■
■
■
■
Package Options
VSS
16 Lead SO WIDE
PWRGD
ENABLE
IRL3103
1000pF
VFB
VID1
VID2
VID2
LGnd
VID3
PWRGD
SS
GATE(L)
VID3
PWRGD
ENABLE
Pentium® II
System
VID0
VID1
VID0
3.3K
V2™ Control Topology
Dual N Channel Design
100ns Controller Transient
Response
Excess of 1Mhz Operation
5 Bit DAC with 1% Tolerance
Power Good Output With
Internal Delay
Enable Input Provides
Micropower Shutdown Mode
Complete Pentium® II System
Requires 18 Components
5V and 12V Operation Using
Either Dual or Single Supplies
Adaptive Voltage Positioning
Remote Sense Capability
Current Sharing Capability
VCC Monitor
Hiccup Mode Short Circuit
Protection
Overvoltage Protection (OVP)
Programmable Soft Start
150ns PWM Blanking
65ns FET Non-Overlap
40ns Gate Rise and Fall Times
(3.3nF load)
VCC
GATE(H)
COFF
VID4
IRL3103
■
■
■
■
■
■
■
■
Application Diagram
12V
■
■
■
VID4
1
COMP
VID4
PGnd
GATE(H)
COFF
VCC
ENABLE
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 12/24/98
1
A
®
Company
CS5165H
Absolute Maximum Ratings
Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 150°C
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Sec max. above 183°C, 230°C Peak
Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Pin Symbol
VMAX
Pin Name
VMIN
ISOURCE
ISINK
VCC
IC Power Input
20V
-0.3V
N/A
SS
Soft Start Capacitor
6V
-0.3V
200µA
1.5A Peak
200mA DC
10µA
COMP
Compensation Capacitor
6V
-0.3V
10mA
1mA
VFB
Voltage Feedback Input
6V
-0.3V
10µA
10µA
COFF
Off-Time Capacitor
6V
-0.3V
1mA
50mA
VID0-4
Voltage ID DAC Inputs
6V
-0.3V
1mA
10µA
GATE(H)
High-Side FET Driver
20V
-0.3V
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
GATE(L)
Low-Side FET Driver
20V
-0.3V
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
ENABLE
Enable Input
6V
-0.3V
100µA
1mA
PWRGD
Power-Good Output
6V
-0.3V
10µA
30mA
PGnd
Power Ground
0V
0V
1.5A Peak
200mA DC
N/A
LGnd
Logic Ground
0V
0V
100mA
N/A
Package Pin Description
PACKAGE PIN #
1,2,3,4,6
PIN SYMBOL
FUNCTION
VID0 -VID4
Voltage ID DAC inputs. These pins are internally pulled up to 5V if left open.
VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.14V to 3.54V with 100mV increments. When VID4 is low (logic
zero), the Error amp reference voltage is 1.34V to 2.09V with 50mV increments.
5
SS
Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and fault
timing.
7
COFF
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the normal and extended off time.
8
ENABLE
Output Enable Input. This pin is internally pulled up to 1.8V. A logic Low
( < 0.8V) on this pin disables operation and places the CS5165H into a low
current sleep mode.
9
VCC
Input Power Supply Pin.
10
GATE(H)
High Side Switch FET driver pin.
11
PGnd
High Current ground for the GATE(H) and GATE(L) pins.
12
GATE(L)
Low Side Synchronous FET driver pin.
13
PWRGD
Power Good Output. Open collector output drives low when VFB is out of
regulation. Active when ENABLE input is low
14
LGnd
Reference ground. All control circuits are referenced to this pin.
15
COMP
Error Amp output. PWM Comparator reference input. A capacitor to LGnd
provides Error Amp compensation.
16
VFB
Error Amp, PWM Comparator, and Low VFB Comparator feedback input.
2
CS5165H
Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 20V; 2.8V DAC Code (VID4=VID2=VID1=VID0=1, VID3= 0),
CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
PARAMETER
■ VCC Supply Current
Operating
Sleep Mode
TEST CONDITIONS
MIN
TYP
MAX
12
20
mA
300
600
µA
3.95
3.87
80
4.15
4.05
V
V
mV
15
0.85
0.1
30
1.0
1.0
60
1.15
µA
µA
V
0.4
1.0
1.6
mA
180
50
0.5
60
400
60
2
85
800
µA
dB
MHz
dB
1.2
1.0
2.0
1.5
V
V
40
80
ns
40
80
ns
30
65
100
ns
30
20
65
50
100
115
ns
kΩ
1.6
25
1.0
0.50
0.9
3.3
100
3.3
0.95
1.0
5.0
200
6.0
1.10
1.1
ms
ms
%
V
V
100
150
ns
1V < VFB < VDAC (max on-time)
No Loads on Gate(H) and Gate(L)
ENABLE = 0V, 8V< VCC <14V
UNIT
■ VCC Monitor
Start Threshold
Stop Threshold
Hysteresis
■ Error Amplifier
VFB Bias Current
COMP Source Current
COMP CLAMP Voltage
GATE(H) Switching
GATE(H) not switching
Start - Stop
3.75
3.65
COMP Clamp Current
COMP Sink Current
VFB = 0V
COMP = 1.2V to 3.6V; VFB = 2.7V
VFB = 2.7V, Adjust COMP voltage for
Comp current = 50µA
COMP = 0V
VCOMP =1.2V; VFB = 3V; VSS > 2.5V
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1kHZ
Note 1
Note 1
Note 1
■ GATE(H) and GATE(L)
High Voltage at 100mA
Low Voltage at 100mA
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE pull-down
■ Fault Protection
SS Charge Time
SS Pulse Period
SS Duty Cycle
SS Comp Clamp Voltage
VFB Low Comparator
■ PWM Comparator
Transient Response
Measure VCC-GATE
Measure GATE
1.6V < GATE < (VCC- 2.5V),
8V < VCC < 14V
(VCC - 2.5V) > GATE > 1.6V,
8V < VCC < 14V
GATE(H) < 2V, GATE(L) > 2V,
8V < VCC < 14V
GATE(L) < 2V, GATE(H) > 2V,
8V < VCC < 14V
Resistance to PGnd (note 1)
VFB = 0V
VFB = 0V
(Charge Time/Period) × 100
VFB = 2.7V, VSS = 0V
Increase VFB till no SS
pulsing and normal Off-time.
VFB = 1.2 to 5V 500ns after
GATE(H) (after Blanking time) to
GATE(H) = (VCC - 1V) to 1V,
8V < VCC < 14V
3
CS5165H
Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 20V; 2.8V DAC Code (VID4=VID2=VID1=VID0=1, VID3= 0),
CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
150
250
ns
VFB = 2.7V
VSS = VFB = 0V
1.0
5.0
1.6
8.0
2.3
12.0
µs
µs
VFB = 2.7V, Measure
GATE(H ) Pulse Width
VFB = 0V
10
30
50
µs
30
50
70
%
0.8
1.30
3
1.30
1.15
3
7
1.8
15
3
V
µs
µA
V
10
20
50
kΩ
+1
%
3.575
3.474
3.373
3.272
3.171
3.070
2.969
2.868
2.767
2.666
2.565
2.464
2.363
2.262
2.161
2.111
2.060
2.010
1.959
1.909
1.858
1.808
1.757
1.707
1.656
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
■ PWM Comparator: continued
Minimum Pulse Width
Drive VFB 1.2 to 5V upon
(Blanking Time)
GATE(H) rising edge (> VCC -1V),
measure GATE(H ) pulse width,
8V < VCC < 14V
■ COFF
Normal Off-Time
Extended Off-Time
■ Time-Out Timer
Time-Out Time
Fault Duty Cycle
■ Enable Input
ENABLE Threshold
Shutdown delay (Note 1)
Pull-up Current
Pull-up Voltage
Input Resistance
■ Voltage Identification DAC
Accuracy (all codes except 11111)
VID4 VID3 VID2 VID1 VID0
1 0
0
0
0
1 0
0
0
1
1 0
0
1
0
1 0
0
1
1
1 0
1
0
0
1 0
1
0
1
1 0
1
1
0
1 0
1
1
1
1 1
0
0
0
1 1
0
0
1
1 1
0
1
0
1 1
0
1
1
1 1
1
0
0
1 1
1
0
1
1 1
1
1
0
0 0
0
0
0
0 0
0
0
1
0 0
0
1
0
0 0
0
1
1
0 0
1
0
0
0 0
1
0
1
0 0
1
1
0
0 0
1
1
1
0 1
0
0
0
0 1
0
0
1
GATE(H) Switching
ENABLE-to-GATE(H) < 2V
ENABLE = 0V
No load on ENABLE pin
ENABLE = 5V,
R = (5V-VPULLUP)/IENABLE
Measure VFB = COMP (COFF = 0V)
25˚C ≤ TJ ≤ 125˚C; VCC = 12V
-1
3.505
3.406
3.307
3.208
3.109
3.010
2.911
2.812
2.713
2.614
2.515
2.416
2.317
2.218
2.119
2.069
2.020
1.970
1.921
1.871
1.822
1.772
1.723
1.673
1.624
4
3.540
3.440
3.340
3.240
3.140
3.040
2.940
2.840
2.740
2.640
2.540
2.440
2.340
2.240
2.140
2.090
2.040
1.990
1.940
1.890
1.840
1.790
1.740
1.690
1.640
PARAMETER
VID4 VID3 VID2 VID1 VID0
0 1
0
1
0
0 1
0
1
1
0 1
1
0
0
0 1
1
0
1
0 1
1
1
0
0 1
1
1
1
1 1
1
1
1
Input Threshold
Input Pull-up Resistance
Input Pull-up Voltage
■ Power Good Output
Low to High Delay
High to Low Delay
Output Low Voltage
Sink Current Limit
THRESHOLD ACCURACY
% of Nominal DAC Output
TEST CONDITIONS
MIN
VID4, VID3, VID2, VID1, VID0
VID4, VID3, VID2, VID1, VID0
VFB = (0.8 × VDAC) to VDAC
VFB = VDAC to (0.8 × VDAC)
VFB = 2.4V, IPWRGD = 500µA
VFB = 2.4V, PWRGD = 1V
TYP
MAX
UNIT
1.574
1.525
1.475
1.426
1.376
1.327
1.223
1.000
25
4.85
1.590
1.540
1.490
1.440
1.390
1.340
1.247
1.250
50
5.00
1.606
1.555
1.505
1.455
1.405
1.353
1.273
2.400
100
5.15
V
V
V
V
V
V
V
V
kΩ
V
30
30
65
75
0.2
4.0
110
120
0.3
15.0
µs
µs
V
mA
MAX
UNIT
0.5
LOWER THRESHOLD
UPPER THRESHOLD
MIN
TYP
MAX
MIN
TYP
-12
-8.5
-5
5
8.5
12
%
3.115
3.027
2.939
2.851
2.763
2.675
2.587
2.499
2.411
2.323
2.235
2.147
2.059
1.971
1.883
1.839
1.795
1.751
1.707
1.663
1.619
1.575
1.531
3.239
3.148
3.056
2.965
2.873
2.782
2.690
2.599
2.507
2.416
2.324
2.233
2.141
2.050
1.958
1.912
1.867
1.821
1.775
1.729
1.684
1.638
1.592
3.363
3.268
3.173
3.078
2.983
2.888
2.793
2.698
2.603
2.508
2.413
2.318
2.223
2.128
2.033
1.986
1.938
1.810
1.843
1.796
1.748
1.701
1.653
3.717
3.612
3.507
3.402
3.297
3.192
3.087
2.982
2.877
2.772
2.667
2.562
2.457
2.352
2.250
2.195
2.142
2.090
2.037
1.985
1.932
1.880
1.827
3.841
3.732
3.624
3.515
3.407
3.298
3.190
3.081
2.973
2.864
2.756
2.647
2.539
2.430
2.322
2.268
2.213
2.159
2.105
2.051
1.996
1.942
1.888
3.965
3.853
3.741
3.629
3.517
3.405
3.293
3.181
3.069
2.957
2.845
2.733
2.621
2.509
2.397
2.341
2.285
2.229
2.173
2.117
2.061
2.005
1.949
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
■ DAC CODE
VID4 VID3 VID2 VID1 VID0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
5
CS5165H
Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 20V; 2.8V DAC Code (VID4=VID2=VID1=VID0=1, VID3= 0),
CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
LOWER THRESHOLD
THRESHOLD ACCURACY
% of Nominal DAC Output
UPPER THRESHOLD
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
-12
-8.5
-5
5
8.5
12
%
1.487
1.443
1.399
1.355
1.311
1.267
1.223
1.179
1.097
1.546
1.501
1.455
1.409
1.363
1.318
1.272
1.226
1.141
1.606
1.558
1.511
1.463
1.416
1.368
1.321
1.273
1.185
1.775
1.722
1.670
1.617
1.565
1.512
1.460
1.407
1.309
1.834
1.779
1.725
1.671
1.617
1.562
1.508
1.454
1.353
1.893
1.837
1.781
1.724
1.669
1.613
1.557
1.501
1.397
V
V
V
V
V
V
V
V
V
■ DAC CODE
VID4 VID3 VID2 VID1 VID0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
Note 1: Guaranteed by design, not 100% tested in production.
Block Diagram
VCC
-
7µA
VCC
VCC Monitor
20k
+
CS5165H
Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 20V; 2.8V DAC Code (VID4=VID2=VID1=VID0=1, VID3= 0),
CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
ENABLE
-
3.95V
3.87V
Circuit Bias
VGATE(H)
+
Enable
Comparator
1.25V
5V
-
SS Low
Comparator
R
Q
S
Q
FAULT
+
60µA
0.7V
SS
+
2µA
PGnd
FAULT
FAULT
Latch
SS High
Comparator
VCC
-
VGATE(L)
2.5V
COMP
VID0
Error Amplifier
VID1
PGnd
+
5 BIT
DAC
VID2
-
-
PWM Comp
+
Blanking
VID3
VID4
-8.5%
PWM
Comparator
+8.5%
-
R
S
Extended
Off-Time
Timeout
Q
Off-Time
Timeout
GATE(H) = ON
GATE(H) = OFF
Q
PWM
Latch
Normal
Off-Time
+
+
-
Maximum
On-Time
Timeout
COFF
One Shot
S
PWRGD
65µs
Delay
VFB
Time Out
Timer
(30µs)
+
LGnd
1V
VFB Low
Comparator
6
COFF
R
Edge Triggered
Q
improved, since the error amplifier bandwidth can be
rolled off at a low frequency. Enhanced noise immunity
improves remote sensing of the output voltage, since the
noise associated with long feedback traces can be effectively filtered.
Theory Of Operation
V2™ Control Method
The V2™ method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains fixed error signal under
deviation in the line voltage, since the slope of the ramp
signal changes, but still relies on a change in the error signal for a deviation in load. The V2™ method of control
maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.
PWM
Comparator
+
GATE(H)
C
GATE(L)
–
Constant Off-Time
Ramp Signal
To maximize transient response, the CS5165H uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
COFF capacitor. To maintain regulation, the V2™ Control
Loop varies switch On-Time. The PWM comparator monitors the output voltage ramp, and terminates the switch
On-Time.
Output
Voltage
Feedback
Error
Amplifier
–
COMP
Error
Signal
E
+
Reference
Voltage
Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient conditions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients. PWM Slope Compensation to
avoid sub-harmonic oscillations at high duty cycles is
avoided.
Figure 1: V2™ Control Diagram
The V2™ control method is illustrated in Figure 1. The output voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
Switch On-Time is limited by an internal 30µs (typical)
timer, minimizing stress to the Power Components.
Programmable Output
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V2™
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2™ control scheme has the
same advantages in line transient response.
The CS5165H is designed to provide two methods for programming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.
The first range is 2.14V to 3.54V in 100mV steps, the second
is 1.34V to 2.09V in 50mV steps, depending on the digital
input code. If all five bits are left open, the CS5165H enters
adjust mode. In adjust mode, the designer can choose any
output voltage by using resistor divider feedback to the
VFB pin, as in traditional controllers. The CS5165H is
specifically designed to meet or exceed Intel’s Pentium® II
specifications.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
Start-up
Until the voltage on the VCC Supply pin exceeds the 3.95V
monitor threshold, the Soft Start and Gate pins are held
low. The Fault latch is Reset (no Fault condition). The output of the Error Amp (COMP) is pulled up to 1V by the
Comp Clamp. When the VCC pin exceeds the monitor
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal
loop. The main purpose of this “slow”feedback loop is to
provide DC accuracy. Noise immunity is significantly
7
CS5165H
Application Information
CS5165H
Application Information: continued
threshold, the GateH output is activated, and the Soft Start
Capacitor begins charging. The GateH output will remain
on, enabling the NFET switch, until terminated by either
the PWM Comparator, or the Maximum On-Time Timer.
If the Maximum On-Time is exceeded before the regulator
output voltage achieves the 1V level, the pulse is terminated. The GateH pin drives low, and the GateL pin drives
high for the duration of the Extended Off-Time. This time
is set by the Time-out Timer and is approximately equal to
the Maximum On-Time, resulting in a 50% Duty Cycle. The
GateL Pin will then drive low, the GateH pin will drive
high, and the cycle repeats.
When regulator output voltage achieves the 1V level present at the Comp pin, regulation has been achieved and
normal Off-Time will ensue. The PWM comparator terminates the switch On-Time, with Off-Time set by the COFF
Capacitor. The V2™ control loop will adjust switch Duty
Cycle as required to ensure the regulator output voltage
tracks the output of the Error Amp.
Trace 1 Soft Start pin (2V/div)
Trace 2 COMP pin (error amplifier output) (1V/div)
Trace 4 Regulator output voltage (1V/div)
Figure 3: Demonstration board start up waveforms.
The Soft Start and Comp capacitors will charge to their
final levels, providing a controlled turn-on of the regulator
output. Regulator turn-on time is determined by the Comp
capacitor charging to its final value. Its voltage is limited
by the Soft Start Comp clamp and the voltage on the Soft
start pin.
Power Supply Sequencing
The CS5165H offers inherent protection from undefined
start-up conditions, regardless of the 12V and 5V supply
power-up sequencing. The turn-on slew rates of the 12V
and 5V power supplies can be varied over wide ranges
without affecting the output voltage or causing detrimental
effects to the buck regulator.
Trace 1 - Regulator Output Voltage (1V/div.)
Trace 2 - Inductor Switching Node (5V/div.)
Figure 4: Demonstration board enable start up waveforms.
Normal Operation
During Normal operation, Switch Off-Time is constant and
set by the COFF capacitor. Switch On-Time is adjusted by
the V2™ Control loop to maintain regulation. This results
in changes in regulator switching frequency, duty cycle,
and output ripple in response to changes in load and line.
Output voltage ripple will be determined by inductor ripple current and the ESR of the output capacitors (see figures 5 & 6 ).
Trace 1 - Regulator Output Voltage (1V/div.)
Trace 2 - Inductor Switching Node (2V/div.)
Trace 3 - 12V input (VCC) (5V/div.)
Trace 4 - 5V Input (1V/div.)
Figure 2: Demonstration board start up in response to increasing 12V
and 5V input voltages. Extended off time is followed by normal off
time operation when output voltage achieves regulation to the error
amplifier output.
8
Holding tolerance to 1% allows the error amplifiers reference voltage to be targeted +40mV high without compromising DC accuracy. A “Droop Resistor”, implemented
through a PC board trace, connects the Error Amps feedback pin (VFB) to the output capacitors and load and carries
the output current. With no load, there is no DC drop
across this resistor, producing an output voltage tracking
the Error amps, including the +40mV offset. When the full
load current is delivered, an 80mV drop is developed
across this resistor. This results in output voltage being offset -40mV low.
The result of Adaptive Voltage Positioning is that additional margin is provided for a load transient before reaching
the output voltage specification limits. When load current
suddenly increases from its minimum level, the output
capacitor is pre-positioned +40mV. Conversely, when load
current suddenly decreases from its maximum level, the
output capacitor is pre-positioned -40mV (see figures 7, 8,
and 9). For best Transient Response, a combination of a
number of high frequency and bulk output capacitors are
usually used.
Trace 1 GATE (H) (10V/div)
Trace 2 Inductor Switching Node (5V/div)
Trace 3 Output Inductor Ripple Current (2A/div)
Trace 4 VOUT ripple (20mV/div)
Figure 5: Normal Operation showing Output Inductor Ripple Current
and Output Voltage Ripple, 0.5A Load, VOUT = +2.84V (DAC = 10111)
If the Maximum On-Time is exceeded while responding to
a sudden increase in Load current, a normal off-time
occurs to prevent saturation of the output inductor.
Trace 1 - GATE(H) (10/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 - Output Inductor Ripple Current (2A/div)
Trace 4 - VOUT ripple (20mV/div)
Trace 3 -Load Current (5A/10mV/div)
Trace 4 - VOUT (100mV/div)
Figure 6: Normal Operation showing Output Inductor Ripple Current
and Output Voltage Ripple, ILOAD = 14A, VOUT = +2.84V (DAC = 10111)
Figure 7: Output Voltage Transient Response to a 14A load pulse,
VOUT= +2.84V (DAC = 10111).
Transient Response
The CS5165H V2™ Control Loop’s 100ns reaction time provides unprecedented transient response to changes in
input voltage or output current. Pulse-by-pulse adjustment
of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot
be changed instantaneously, regulation is maintained by
the output capacitor(s) during the time required to slew the
inductor current.
Overall load transient response is further improved
through a feature called “Adaptive Voltage Positioning”.
This technique pre-positions the output capacitors voltage
to reduce total output voltage excursions during changes in
load.
9
CS5165H
Application Information: continued
CS5165H
Application Information: continued
threshold. If this happens the cycle will repeat itself until
the short is removed. The Soft Start charge/discharge current ratio sets the duty cycle for the pulses (2µA/60µA =
3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%).
This protection feature results in less stress to the regulator
components, input power supply, and PC board traces
than occurs with constant current limit protection (see
Figures 10 and 11).
If the short circuit condition is removed, output voltage
will rise above the 1V level, preventing the FAULT latch
from being set, allowing normal operation to resume.
Trace 1 - GATE(H) (10V/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 -Load Current (5A/div)
Trace 4 - VOUT (100mV/div)
Figure 8: Output Voltage Transient Response to a 14A load step, VOUT =
+2.84V(DAC = 10111).
Trace 4 - 5V Supply Voltage (2V/div.)
Trace 3 - Soft Start Timing Capacitor (1V/div.)
Trace 2 - Inductor Switching Node (2V/div.)
Figure 10: Demonstration board hiccup mode short circuit protection.
Gate pulses are delivered while the Soft Start capacitor charges, and
cease during discharge.
Trace 1 - GATE(H) (10V/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 -Load Current (5A/div)
Trace 4 - VOUT(100mV/div)
Figure 9: Output Voltage Transient Response to a 14A load turn-off,
VOUT = +2.84V (DAC = 10111).
Protection and Monitoring Features
Short Circuit Protection
A lossless hiccup mode short circuit protection feature is
provided, requiring only the Soft Start capacitor to implement. If a short circuit condition occurs the VFB low comparator sets the FAULT latch. This causes the top FET to
shut off, disconnecting the regulator from its input voltage.
The Soft Start capacitor is then slowly discharged by a 2µA
current source until it reaches its lower 0.7V threshold. The
regulator will then attempt to restart normally, operating
in its extended off time mode with a 50% duty cycle, while
the Soft Start capacitor is charged with a 60µA charge current.
Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 2 = Inductor Switching Node (2V/div.)
Figure 11: Demonstration board Start up with regulator output shorted
to ground.
If the short circuit condition persists, the regulator output
will not achieve the 1V low VFB comparator threshold
before the Soft Start capacitor is charged to its upper 2.5V
10
CS5165H
Application Information: continued
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V2™ control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 100ns, causing
the top MOSFET to shut off, disconnecting the regulator
from its input voltage. The bottom MOSFET is then activated, resulting in a “crowbar” action to clamp the output
voltage and prevent damage to the load (see Figures 12
and 13). The regulator will remain in this state until the
overvoltage condition ceases or the input voltage is pulled
low. The bottom FET and board trace must be properly
designed to implement the OVP function. If a dedicated
OVP output is required, it can be implemented using the
circuit in figure 14. In this figure the OVP signal will go
high (overvoltage condition), if the output voltage (VCORE)
exceeds 20% of the voltage set by the particular DAC code
and provided that PWRGD is low. It is also required that
the overvoltage condition be present for at least the
PWRGD delay time for the OVP signal to be activated. The
resistor values shown in figure 14 are for VDAC = +2.8V
(DAC = 10111). The VOVP (overvoltage trip-point) can be
set using the following equation:
Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)
Figure 13: OVP response to an input-to-output short circuit by pulling
the input voltage to ground.
VCORE
15K
VOVP = VBEQ3
(
1+
R2
R1
)
R1
Q3
2N3906
+5V
56K
R2
5K
OVP
20K
+5V
Q2
10K
2N3904
CS5165H
10K
10K
Q1
PWRGD
2N3906
Figure 14: Circuit to implement a dedicated OVP output using the
CS5165H.
Output Enable Circuit
The Enable pin (pin 8) is used to enable or disable the regulator output voltage, and is consistent with TTL DC specifications. It is internally pulled-up. If pulled low (below
0.8V), the output voltage is disabled. At the same time the
Power Good and Soft Start pins are pulled low, so that
when normal operation resumes power-up of the CS5165H
goes through the Soft Start sequence. Upon pulling the
Enable pin low, the internal IC bias is completely shut off,
resulting in total shutdown of the Controller IC.
Trace 4 = 5V from PC Power Supply (5V/div.)
Trace1 = Regulator Output Voltage (1V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
Figure 12: OVP response to an input-to-output short circuit by immediately providing 0% duty cycle, crow-barring the input voltage to
ground.
Power Good Circuit
The Power Good pin (pin 13) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled -up, and is pulled low (below 0.3V) when the regulator output voltage typically exceeds ± 8.5% of the nominal output voltage. Maximum output voltage deviation
before Power Good is pulled low is ± 12%.
11
CS5165H
Application Information: continued
Trace 2 - PWRGD (2V/div)
Trace 4 - VOUT (1V/div)
Trace 1 PWRGD (2V/div)
Trace 4 VFB (1V/div)
Figure 15: PWRGD signal becomes logic high as VOUT enters -8.5% of
lower PWRGD threshold, VOUT = +2.84V (DAC = 10111)
Figure 17: Power Good is insensitive to out of regulation conditions
that are present for a duration less than the built in delay.
Selecting External Components
The CS5165H buck regulator can be used with a wide
range of external power components to optimize the cost
and performance of a particular design. The following
information can be used as general guidelines to assist in
their selection.
NFET Power Transistors
Both logic level and standard FETs can be used. The reference designs derive gate drive from the 12V supply which
is generally available in most computer systems and utilize
logic level FETs. A charge pump may be easily implemented to permit use of standard FET’s or support 5V or 12V
only systems (maximum of 20V). Multiple FET’s may be
paralleled to reduce losses and improve efficiency and
thermal management.
Trace 1 PWRGD (2V/div)
Trace 4 VFB (1V/div)
Figure 16: Power Good response to an out of regulation condition.
Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail to rail due to overshoot caused by the capacitive
load they present to the controller IC. For the typical application where VCC = 12V and 5V is used as the source for
the regulator output current, the following gate drive is
provided:
Figure 16 shows the relationship between the regulated
output voltage VFB and the Power Good signal. To prevent
Power Good from interrupting the CPU unnecessarily, the
CS5165H has a built-in delay to prevent noise at the VFB
pin from toggling Power Good. The internal time delay is
designed to take about 75µs for Power Good to go low and
65µs for it to recover. This allows the Power Good signal to
be completely insensitive to out of regulation conditions
that are present for a duration less than the built in delay
(see figure 17).
VGS (TOP) = 12V - 5V = 7V, VGS(BOTTOM) = 12V (see Figure 18).
It is therefore required that the output voltage attains an
out of regulation or in regulation level for at least the builtin delay time duration before the Power Good signal can
change state.
12
Synchronous MOSFET:
Power = ILOAD2 × RDSON × (1 - duty cycle)
Duty Cycle =
VOUT + (ILOAD × RDSON OF SYNCH FET)
VIN + (ILOAD × RDSON OF SYNCH FET) - (ILOAD × RDSON OF SWITCH FET)
Off Time Capacitor (COFF)
The COFF timing capacitor sets the regulator off time:
TOFF = COFF × 4848.5
Trace 3 = GATE(H) (10V/div.)
Trace 1= GATE(H) - 5VIN
Trace 4 = GATE(L) (10V/div.)
Trace 2 = Inductor Switching Node (5V/div.)
Figure 18: Gate drive waveforms depicting rail to rail swing.
The preceding equation for Duty Cycle can also be used to
calculate the regulator switching frequency and select the
COFF timing capacitor:
COFF =
Period × (1-Duty Cycle)
4848.5
where
period =
Trace 1 - GATE(H) (5V/div)
Trace 2 - GATE(L) (5V/div)
Figure 19: Normal Operation showing the guaranteed Non-Overlap
time between the High and Low - Side MOSFET Gate Drives, ILOAD =
14A.
The CS5165H provides adaptive control of the external
NFET conduction times by guaranteeing a typical 65ns
non-overlap between the upper and lower MOSFET gate
drive pulses. This feature eliminates the potentially catastrophic effect of “shoot-through current”, a condition during which both FETs conduct causing them to overheat,
self-destruct, and possibly inflict irreversible damage to the
processor.
The most important aspect of FET performance is RDSON,
which effects regulator efficiency and FET thermal management requirements.
The power dissipated by the MOSFETs may be estimated
as follows:
1
switching frequency
Schottky Diode for Synchronous FET
For synchronous operation, A Schottky diode may be
placed in parallel with the synchronous FET to conduct the
inductor current upon turn off of the switching FET to
improve efficiency. The CS5165H reference circuit does not
use this device due to its excellent design. Instead, the
body diode of the synchronous FET is utilized to reduce
cost and conducts the inductor current. For a design operating at 200kHz or so, the low non-overlap time combined
with Schottky forward recovery time may make the benefits of this device not worth the additional expense. The
power dissipation in the synchronous MOSFET due to
body diode conduction can be estimated by the following
equation:
Power = Vbd × ILOAD × conduction time × switching frequency
Where Vbd = the forward drop of the MOSFET body diode.
For the CS5165H demonstration board:
Power = 1.6V × 14.2A × 100ns × 200kHz = 0.45W
This is only 1.1% of the 40W being delivered to the load.
Switching MOSFET:
Power = ILOAD2 × RDSON × duty cycle
13
CS5165H
Application Information: continued
CS5165H
Application Information: continued
“Droop” Resistor for Adaptive Voltage Positioning
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage full
load is above the minimum DC tolerance spec.
Adaptive voltage positioning is used to help keep the output voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the full
load current and should be chosen so that both DC and AC
tolerance limits are met. An embedded PC trace resistor
has the distinct advantage of near zero cost implementation. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation causes the thickness of the PCB layer to vary. 2) the mismatch of L/W, and
3) temperature variation.
1)
VDROOP(TYP) =
Sheet Resistivity
VDROOP(TYP)=
[VDAC(MIN)-VDC PENTIUM®II(MIN)]
1+RDROOP(TOLERANCE)
Mismatch due to L/W
Thermal Considerations
Due to I2 × R power losses the surface temperature of
the droop resistor will increase causing the resistance
to increase. Also, the ambient temperature variation
will contribute to the increase of the resistance,
according to the formula:
R = R20 [1+ α20(Τ−20)]
where:
R20 = resistance at 20˚C
α=
=
2.812V-2.74V
1.3
= 56mV
With the CS5165H DAC accuracy being 1%, the internal
error amplifier’s reference voltage is trimmed so that the
output voltage will be 40mV high at no load. With no load,
there is no DC drop across the resistor, producing an output voltage tracking the error amplifier output voltage,
including the offset. When the full load current is delivered, a drop of -56mV is developed across the resistor.
Therefore, the regulator output is pre-positioned at 40mV
above the nominal output voltage before a load turn-on.
The total voltage drop due to a load step is ∆V-40mV and
the deviation from the nominal output voltage is 40mV
smaller than it would be if there was no droop resistor.
Similarly at full load the regulator output is pre-positioned
at 16mV below the nominal voltage before a load turn-off.
the total voltage increase due to a load turn-off is ∆V-16mV
and the deviation from the nominal output voltage is 16mV
smaller than it would be if there was no droop resistor.
This is because the output capacitors are pre-charged to
value that is either 40mV above the nominal output voltage
before a load turn-on or, 16mV below the nominal output
voltage before a load turn-off (see figure 7).
The variation in L/W is governed by variations due to
the PCB manufacturing process that affect the
geometry and the power dissipation capability of the
droop resistor. The error due to L/W mismatch is
typically 1%
3)
1+RDROOP(TOLERANCE)
Example: for a 300MHz Pentium®II, the DC accuracy spec
is 2.74 < VCC(CORE) < 2.9V, and the AC accuracy spec is
2.67V < VCC(CORE) <2.93V. The CS5165H DAC output voltage is +2.812V < VDAC < +2.868V. In order not to exceed
the DC accuracy spec, the voltage drop developed across
the resistor must be calculated as follows:
for one ounce copper, the thickness variation is
typically 1.15 mil to 1.35 mil. Therefore the error due to
sheet resistivity is:
1.35 - 1.15
= 16%
1.25
2)
[VDAC(MIN)-VDC(MIN)]
0.00393
˚C
Obviously, the larger the voltage drop across the droop
resistor ( the larger the resistance), the worse the DC and
load regulation, but the better the AC transient response.
T= operating temperature
R = desired droop resistor value
For temperature T = 50˚C,
the % R change = 12%
Design Rules for Using a Droop Resistor
Droop Resistor Tolerance
The basic equation for laying an embedded resistor is:
Tolerance due to sheet resistivity variation
16%
Tolerance due to L/W error
1%
Tolerance due to temperature variation
12%
Total tolerance for droop resistor
29%
RAR = ρ ×
where:
14
L
A
or
R=ρ×
L
(W × t)
CS5165H
Application Information: continued
A= W × t = cross-sectional area
Inductor Ripple Current
ρ= the copper resistivity (µΩ - mil)
Ripple current =
L= length (mils)
W = width (mils)
For most PCBs the copper thickness, t, is 35µm (1.37 mils)
for one ounce copper. ρ = 717.86µΩ-mil
Ripple current =
For a Pentium®II load of 14.2A the resistance needed to create a 56mV drop at full load is:
RDROOP = I
OUT
(Switching Frequency
× L × VIN)
Example: VIN = +5V, VOUT = +2.8V, ILOAD = 14.2A, L = 1.2µH,
Freq = 200KHz
t = thickness (mils)
56mV
[(VIN - VOUT) × VOUT]
[(5V-2.8V)x 2.8V]
[200KHz × 1.2µH × 5V]
= 5.1A
Output Ripple Voltage
56mV
VRIPPLE = Inductor Ripple Current × Output Capacitor ESR
= 14.2A = 3.9mΩ
Example:
VIN = +5V, VOUT = +2.8V, ILOAD = 14.2A, L = 1.2µH,
Switching Frequency = 200KHz
Output Ripple Voltage = 5.1A × Output Capacitor ESR
(from manufacturer’s specs)
ESR of Output Capacitors to limit Output Voltage Spikes
The resistivity of the copper will drift with the temperature
according to the following guidelines:
∆R = 12% @ TA = +50˚C
∆R = 34% @TA = +100˚C
∆ VOUT
ESR =
Droop Resistor Width Calculations
The droop resistor must have the ability to handle the load
current and therefore requires a minimum width which is
calculated as follows (assume one ounce copper thickness):
W=
This applies for current spikes that are faster than regulator
response time. Printed Circuit Board resistance will add to
the ESR of the output capacitors.
In order to limit spikes to 100mV for a 14.2A Load Step,
ESR = 0.1/14.2 = 0.007Ω
ILOAD
0.05
where:
Inductor Peak Current
Peak Current = Maximum Load Current +
W = minimum width (in mils) required for proper power
dissipation, and ILOAD Load Current Amps.
The Pentium®II maximum load current is 14.2A.
W=
0.05
(
Ripple
Current
2
)
Example: VIN = +5V, VOUT = +2.8V, ILOAD = 14.2A, L = 1.2µH,
Freq = 200KHz
Therefore:
14.2A
∆ IOUT
Peak Current = 14.2A + (5.1/2) = 16.75A
A key consideration is that the inductor must be able to
deliver the Peak Current at the switching frequency without
saturating.
= 284 mils = 0.7213cm
Droop Resistor Length Calculation
Response Time to Load Increase
(limited by Inductor value unless Maximum On-Time is
exceeded)
RDROOP × W × t 0.0039 × 284 × 1.37
L=
=
= 2113 mil = 5.36cm
717.86
ρ
L × ∆ IOUT
Response Time =
Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade
transient response.
(VIN-VOUT)
Example: VIN = +5V, VOUT = +2.8V, L = 1.2µH, 14.2A
change in Load Current
Response Time =
15
1.2µH × 14.2A
(5V-2.8V)
= 7.7µs
CS5165H
Application Information: continued
Response Time to Load Decrease
(limited by Inductor value)
Layout Guidelines
When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to
ensure proper operation of the CS5165H.
L × Change in IOUT
Response Time =
VOUT
1) Rapid changes in voltage across parasitic capacitors and
abrupt changes in current in parasitic inductors are major
concerns for a good layout.
Example: VOUT=+2.8V, 14.2A change in Load Current,
L = 1.2µH
Response Time =
1.2µH × 14.2A
2.8V
2) Keep high currents out of logic grounds.
3) Avoid ground loops as they pick up noise. Use star or
single point grounding. The source of the lower (synchronous FET) is an ideal point where the input and output GND planes can be connected.
= 6.1µs
Input and Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors
are their ripple rating, while ESR is important for output
capacitors. For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
Thermal Management
Thermal Considerations for Power MOSFETs and Diodes
In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a
maximum of 150°C or lower. The thermal impedance
(junction to ambient) required to meet this requirement can
be calculated as follows:
Thermal Impedance =
TJ(MAX) - TA
Power
4) For double-sided PCBs a single large ground plane is not
recommended, since there is little control of where currents
flow and the large surface area can act as an antenna.
5) Even though double sided PCBs are usually sufficient
for a good layout, four-layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the two
internal layers as the +5V and GND planes, and the top
and bottom layers for the vias.
6) Keep the inductor switching node small by placing the
output inductor, switching and synchronous FETs close
together.
7) The FET gate traces to the IC must be as short, straight,
and wide as possible. Ideally, the IC has to be placed right
next to the FETs.
8) Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy
copper to keep the parasitic resistance low.
9) Place the switching FET as close to the +5V input capacitors as possible.
A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal vias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.
10) Place the output capacitors as close to the load
as possible.
11) Place the VFB filter resistor in series with the
VFB pin (pin 16) right at the pin.
EMI Management
12) Place the VFB filter capacitor right at the VFB pin (pin
16).
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing
for compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions.
These components are not required for regulator operation
and experimental results may allow them to be eliminated.
The input filter inductor may not be required because bulk
filter and bypass capacitors, as well as other loads located
on the board will tend to reduce regulator di/dt effects on
the circuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
13) The “Droop” Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.
14) Place the VCC bypass capacitor as close as possible to
the VCC pin.
16
CS5165H
200
180
160
140
120
100
80
60
40
20
0
VCC=12V
TA=25C˚
0
2000
4000
6000 8000 10000 12000 14000 16000
Load Capacitance (pF)
200
180
160
140
120
100
80
60
40
20
0
4000
2000
4000
6000 8000 10000 12000 14000 16000
Load Capacitance (pF)
Figure 21: GATE(H) Risetime vs. Load Capacitance
VCC=12V
TA=25C˚
2000
VCC=12V
TA=25C˚
0
DAC Output Voltage Deviation (%)
Falltime (ns)
Figure 20: GATE(L) Risetime vs. Load Capacitance
0
200
180
160
140
120
100
80
60
40
20
0
Risetime (ns)
Risetime (ns)
Typical Performance Characteristics
6000 8000 10000 12000 14000 16000
Load Capacitance (pF)
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
20
40
60
80
100
120
Junction Temperature (˚C)
Figure 22: GATE(H) &GATE(L) Falltime vs. Load Capacitance
Figure 23: DAC Output Voltage vs Temperature, DAC Code = 10111,
VCC = 12V
0.04
0.05
Output Error (%)
Output Error (%)
0.02
0
-0.02
-0.04
-0.06
0
-0.05
-0.1
-0.15
-0.2
-0.08
-0.1
1.34 1.39 1.44 1.49 1.54 1.59 1.64 1.69 1.74 1.79 1.84 1.89 1.94 1.99 2.04 2.09
-0.25
2.14 2.24 2.34 2.44 2.54 2.64 2.74 2.84 2.94 3.04 3.14 3.24 3.34 3.44 3.54
DAC Output Voltage Setting (V)
DAC Output Voltage Setting (V)
Figure 24: Percent Output Error vs DAC Voltage Setting,
Figure 25: Percent Output Error vs. DAC Output Voltage Setting
VCC = 12V, TA = 25˚C, VID4 = 0
VCC = 12V, TA = 25˚C, VID4 = 1
17
CS5165H
Additional Application Circuits
+12V
+12V
1N5818
1200µF/10V
0.1µF
1N5818
x3
18Ω
1µF
18V 1N4746
1000pf
COFF VCC
SS
0.1µF
IRL3103
1.2µH
GATEH
CS5165H
COMP
0.1µF
VID0
VID1
VID2
VID3
VID4
Droop Resistor
(Embedded PCB trace)
6mΩ
VCC
3.3K
VFB
1200µF/10V
x5
1000pF
VSS
IRL3103
GATEL
PWRGD
PGND
ENABLE
LGND
ENABL PWRGD
PENTIUM® II
SYSTEM
VID4
VID3
VID2
VID1
VID0
Figure 26: +12V to +2.8V @ 14.2A for 300 MHz Pentium® II
+5V
MBRS120
1µF
MBRS120
1200uF/10V
x3
MBRS120
1µF
VCC
VID0
VGATEH
Si4410DY
VID1
VID2
Si9410DY
1200µF/10V
x5
VGATEL
PGND
COFF
ENABLE
PWRGD
SS
3.3K
VFB
COMP
0.1µF
Vcc
CS5165H
VID3
VID4
330pF
Droop Resistor
(Embedded PCB trace)
6mΩ
1.2µH
LGND
Vss
ENABLE
PWRGD
PENTIUM® II
SYSTEM
1000pF
0.1µF
VID4
VID3
VID2
VID1
VID0
Figure 27: +5V to +2.8V @ 14.2A for 300 MHz Pentium® II
18
CS5165H
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
D
Lead Count
Metric
Max
Min
10.50
10.10
16L SO Wide
Thermal Data
English
Max Min
.413 .398
RΘJC
RΘJA
16L
SO Wide
23
105
typ
typ
˚C/W
˚C/W
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
1.27 (.050)
0.40 (.016)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
D
REF: JEDEC MS-013
0.30 (.012)
0.10 (.004)
Ordering Information
Part Number
CS5165HGDW16
CS5165HGDWR16
Rev. 12/24/98
Description
16L SO Wide
16L SO Wide (tape & reel)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
19
© 1999 Cherry Semiconductor Corporation
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