CS7054 CS7054 Low Side PWM FET Controller Features Description The CS7054 is a monolithic integrated circuit designed primarily to control the rotor speed of permanent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or IGBT with a user-adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) signal. The CS7054 can also be used to control other loads such as incandescent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. The CS7054 accepts a DC level input signal of 0 to 5V to control the pulse width of the output signal. This signal can be generated by a potentiometer referenced to the onchip 5V linear regulator, or a filtered 0% to 100% PWM signal also referenced to the 5V regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5V. In this mode everything on the chip is shut down except for the on-chip regulator and the overall current draw is less than 275 µA. There are a number of on-chip diagnostics that look for potential failure modes and can disable the external power MOSFET. ■ 200 mA Peak PWM Gate Drive Output ■ Patented Voltage Compensation Circuit ■ 100% Duty Cycle Capability ■ 5V, ± 3% Linear Reg. ■ Low Current Sleep Mode ■ Overvoltage Protection ■ Over Current Protection of External MOSFET / IGBT ■ Output Inhibit Application Diagram Package Options MOT+ 14 Lead PDIP VBAT 42.5mH RGATE 6 RS 51 MOT- .01mF 10mF 1000mF 1000mF CFLT .25mF COSC 390pF FLT COSC ROSC 105K 1M OUTPUT VCC Gnd PGnd ROSC CTL NC INH IADJ RCS1 ISENSE+ CCS 51 .022mF ISENSE- VREG RSENSE 4mW OUTPUT 1 14 VCC Gnd 2 13 PGnd FLT 3 12 INH COSC 4 11 IADJ ROSC 5 10 ISENSE+ CTL 6 9 ISENSE- NC 7 8 VREG RCS2 51 Input 10K 10K 10K P1 10K 100K N1 10K 10mF Consult factory for 16 lead SO wide package. 10K Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 4/21/99 1 A ¨ Company CS7054 Absolute Maximum Ratings Storage Temperature ................................................................................................................................................-65ûC to 150ûC VCC ................................................................................................................................................................................-0.3V to 30V Supply Voltage Range (load dump = 26Vw/series 51½ resistor) VCC Peak Transient Voltage.....................................40V Input Voltage Range (at any input) ...........................................................................................................................-0.3V to 10V Maximum Junction Temperature ..........................................................................................................................................150ûC ESD Capability (Human Body Model) ....................................................................................................................................2kV Lead Temperature Soldering: Wave Solder (through hole styles only)..........................................10 sec. max, 260¡C peak Electrical Characteristics: 8V < VCC < 16V, -40ûC < TA < 125¡C, (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5 10 mA 170 275 µA ■ VCC Supply Operating Current Supply Quiescent Current VCC = 12V Overvoltage Shutdown 18 19.5 21 V Overvoltage Hysteresis 150 325 500 mV -2 0.1 2 µA Sleep Mode Threshold 8% 10% 12% VREG Sleep Mode Hysteresis 50 100 150 mV 79.5 mV ■ Control (CTL) Control Input Current CTL = 0V to 5V ■ Current Sense Differential Voltage Sense IADJ =51.2% VREG and RCS1= 51½ IADJ Input Current IADJ = 0V to 5V 60.5 -5 0.3 2 µA 4.85 5.00 5.15 V Inhibit Threshold 40% 50% 60% VREG Inhibit Hysteresis 150 325 500 mV 20 23 kHz 38.5 81.5 % % ■ Linear Regulator VREG Output Voltage VCC = 13.2V ■ Inhibit ■ External Drive (OUTPUT) Output Frequency ROSC = 105k½, COSC = 390pF 17 Voltage to Duty Cycle Conversion VCC = 13V, CTL = 30% VREG VCC = 13V, CTL = 70% VREG 26.3 69.5 Output Rise Time VCC = 13V, RGATE = 6½, CGATE = 5nF .25 1 µs Output Fall Time VCC = 13V, RGATE = 6½, CGATE = 5nF .30 1 µs Output Sink Current VCC = 13V, RGATE = 6½, CGATE = 5nF 400 mA Output Source Current VCC = 13V, RGATE = 6½, CGATE = 5nF 400 mA Output High Voltage IOUT = 1mA Output Low Voltage IOUT = -1mA VCC - 1.7 V 1.3 2 V PACKAGE LEAD # LEAD SYMBOL CS7054 Package Lead Description FUNCTION 14 Lead PDIP 1 OUTPUT MOSFET Gate Drive 2 Gnd Ground 3 FLT Fault time out capacitor 4 COSC Oscillator capacitor 5 ROSC Oscillator resistor 6 CTL Pulse width control input 7 NC No connection 8 VREG 5V linear regulator 9 ISENSE- Current sense minus 10 ISENSE+ Current sense plus 11 IADJ Current limit adjust 12 INH Output Inhibit 13 PGnd Power ground for on chip clamp 14 VCC Positive power supply input Application Information IROSC is multiplied by two (2) internally and transferred to the COSC lead. Therefore: Theory Of Operation Oscillator The IC sets up a constant frequency triangle wave at the COSC lead whose frequency is determined by the external components ROSC and COSC by the following equation: Frequency = ICOSC = ± VCC ROSC The period of the oscillator is: 0.83 ROSC ´ COSC T = 2COSC ´ The peak and valley of the triangle wave are proportional to VCC by the following: VVALLEY = 0.2 ´ VCC ICOSC The ROSC and COSC components can be varied to create frequencies over the range of 15Hz to 25kHz. With the suggested values of 105k½ and 390pF for ROSC and COSC respectively, the nominal frequency will be approximately 20 kHz. IROSC, at VCC = 14V, will be 66.7 µA. IROSC should not change over a more than 2:1 ratio and therefore COSC should be changed to adjust the oscillator frequency. VPEAK = 0.8 ´ VCC This is required to make the voltage compensation function properly. In order to keep the frequency of the oscillator constant the current that charges COSC must also vary with supply. ROSC sets up the current which charges COSC. The voltage across ROSC is 50% of VCC and therefore: IROSC = 0.5 ´ (VPEAK - VVALLEY) Voltage Duty Cycle Conversion The IC translates an input voltage at the CTL lead into a duty cycle at the OUTPUT lead. The transfer function incorporates Cherry SemiconductorÕs patented Voltage Compensation method to keep the average voltage and current across the load constant regardless of fluctuations VCC ROSC 3 in the supply voltage. The duty cycle is varied based upon the input voltage and supply voltage by the following equation: Duty Cycle = 100% ´ tial voltage across these two leads is amplified internally and compared to the voltage at the IADJ lead. The gain, AV, is set internally and externally by the following equation: 2.8 ´ VCTL AV = VCC VDC = (1.683 ´ VCTL) + (VVALLEY) is compared to the oscillator voltage to produce the compensated duty cycle. The transfer is set up so that at VCC = 14V the duty will equal VCTL divided by VREG. For example at VCC = 14V, VREG = 5V and VCTL = 2.5V, the duty cycle would be 50% at the output. This would place a 7V average voltage across the load. If VCC then drops to 10V, the IC would change the duty cycle to 70% and hence keep the average load voltage at 7V. VCC = 8V 80% VCC = 14V VCC = 16V 40% 20% 0% 40% 50% 60% 70% 80% 90% (1000 + RCS) 37000 ´ VI(ADJ) RSENSE When the current through the external MOSFET exceeds ILIM, an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscillator cycle (fault mode). At the start of the next cycle, the latch is reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC Òtimes outÓ and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the CFLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from CFLT. If enough faults occur together, eventually CFLT will charge up to 2.4V and the fault latch will be set. The fault latch will not be reset until the CFLT discharges to 0.6V. This action will continue indefinitely if the fault persists. 60% 30% 37000 1000 + RCS The RCS resistors and CCS components form a differential low pass filter which filters out high frequency noise generated by the switching of the external MOSFET and the associated lead noise. RCS also forms an error term in the gain of the ILIM equation because the ISENSE+ and ISENSEleads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50µA while the chip is in run mode. RCS should be much less than 1000 ½ to minimize error in the ILIM equation. IADJ should be biased between 1V and 4V. 100% 20% = ISENSE+ - ISENSE- ILIM = 120% 10% VI(ADJ) The current limit (ILIM) is set by the external current sense resistor (RSENSE) placed across the ISENSE+ and ISENSE- terminals and the voltage at the IADJ lead. An internal DC voltage equal to: Duty Cycle( %) CS7054 Application Information: continued 100% CTL Voltage (% of VREG) Figure 1: Voltage Compensation 5V Linear Regulator There is a 5V, 5mA linear regulator available at the VREG lead for external use. This voltage acts as a reference for many internal and external functions. It has a drop out of approximately 1.5V at room temperature and does not require an external capacitor for stability. The off time and on time are set by the following: Off Time = CFLT ´ Current Sense and Timer The IC differentially monitors the load current on a cycle by cycle basis at the ISENSE+ and ISENSE- leads. The differen4 2.4V - 0.6V 4.5µA Overvoltage Shutdown On Time = CFLT ´ The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom. 2.4V - 0.6V IAVG where: IAVG = ( 295.5µA ´ DC) - [4.5µA ´ (1 - DC)] Reverse Battery IAVG = (300µA ´ DC) - 4.5µA The CS7054 will not survive a reverse battery condition. Therefore, a series diode is required between the battery and the VCC lead. DC = PWM Duty Cycle Sleep State This device will enter into a low current mode (<275µA) when CTL lead is brought to less than 0.5V. All functions are disabled in this mode, except for the regulator. Load Dump VCC is internally clamped to 30V. It is recommended that a 51½ resistor, (RS) is placed in series with VCC to limit the current flow into the IC in the event of a 40V peak transient condition. Inhibit When the inhibit voltage is greater than 2.5V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle. 5 CS7054 Application Information: continued CS7054 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Thermal Data D Lead Count Metric Max Min 19.69 18.67 14L PDIP English Max Min .775 .735 RQJC RQJA typ typ 14L PDIP 48 85 ûC/W ûC/W Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 8.26 (.325) 7.62 (.300) 1.77 (.070) 1.14 (.045) 2.54 (.100) BSC 3.68 (.145) 2.92 (.115) .356 (.014) .203 (.008) 0.39 (.015) MIN. .558 (.022) .356 (.014) REF: JEDEC MS-001 D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. Ordering Information Part Number CS7054YN14 Rev. 4/21/99 Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Description 14 Lead PDIP 6 © 1999 Cherry Semiconductor Corporation