CS4124 High Side PWM FET Controller Features Description The CS4124 is a monolithic integrated circuit designed primarily to control the rotor speed of permanent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or IGBT with a user-adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) signal. The CS4124 can also be used to control other loads such as incandescent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. The CS4124 accepts a DC level input signal of 0 to 5V to control the pulse width of the output signal. This signal can be generated by a potentiometer referenced to the onchip 5V linear regulator, or a filtered 0% to 100% PWM signal also referenced to the 5V regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5V. In this mode everything on the chip is shutdown except for the on-chip regulator and the overall current draw is less than 275µA. There are a number of on-chip diagnostics that look for potential failure modes and can disable the external power MOSFET. ■ 150mA Peak PWM Gate Drive Output ■ Patented Voltage Compensation Circuit ■ 100% Duty Cycle Capability ■ 5V, ± 3% Linear Regulator ■ Low Current Sleep Mode ■ Overvoltage Protection ■ Boost Mode Power Supply ■ Output Inhibit Applications Diagram Package Option VBAT 42.5µH 16 Lead PDIP 1000µF 1000µF RS 10 470µH 10K CFLT 1.5µF .25µF ROSC 93.1K ROSC COSC 470pF 10nF OUTPUT BOOST FLT ROSC OUTPUT Gnd BOOST INH FLT IADJ COSC CTL PGnd VCC RCS1 ISENSE+ ISENSEPMP SNI VREG CCS 51 .022µF RSNI 4 RSENSE 4m RCS2 51 .01µF 100µF 10K 10K Input RGATE 6 Gnd 1 INH IADJ ISENSE+ COSC ISENSE- CTL PGnd PMP SNI VCC VREG 1µF P1 10K 100K 10K 1M MOT+ N1 10K 10µF 10K MOT- Consult Factory for 16 Lead SOIC Wide package. Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: [email protected] Web Site: www.cherry-semi.com Rev. 4/26/99 1195 A ® Company CS4124 Preliminary CS4124 Absolute Maximum Ratings Storage Temperature ................................................................................................................................................-65˚C to 150˚C VCC .................................................................................................................................................................................-0.3V to 30V VCC Peak Transient Voltage (load dump = 26V w/series 10Ω resistor) ...........................................................................40V Input Voltage Range (at any input) ...........................................................................................................................-0.3V to 10V Maximum Junction Temperature ..........................................................................................................................................150˚C Lead Temperature Soldering Wave Solder (through hole styles only) ......................................................................................10 sec. max, 260°C peak ESD Capability (Human Body Model) ....................................................................................................................................2kV Electrical Characteristics: 4V ≤ VCC ≤ 26V, -40˚C < TA < 125°C, (unless otherwise specified) PARAMETER ■ VCC Supply Operating Current Supply Quiescent Current TEST CONDITIONS ■ Current Sense Differential Voltage Sense ■ Linear Regulator Output Voltage, VREG ■ Inhibit Inhibit Threshold Inhibit Hysteresis ■ External Drive (OUTPUT) Output Frequency MAX UNIT 5 10 15 mA mA 170 275 29 µA V 0.1 10% 100 2 12% 150 150 µA VREG mV mV 18 104 34 125 mV mV 15 39 mV 15 102 39 130 mV mV 2 µA 5.15 5.20 V V V 60% 500 500 VREG mV mV 25 kHz 26.5 CTL = 0V to 5V -2 8% 50 10 7V ≤ VCC ≤ 26V 4V ≤ VCC < 7V 7V ≤ VCC ≤ 18V IADJ = 1V and RCS1 = 51Ω IADJ = 4V and RCS1 = 51Ω 4V ≤ VCC < 7V IADJ =1V and RCS1 = 51Ω 18V < VCC ≤ 26V IADJ = 1V and RCS1 = 51Ω IADJ = 4V and RCS1 = 51Ω IADJ Input Current TYP 7V ≤ VCC ≤ 18V 4V ≤ VCC < 7V, 18V < VCC ≤ 26V VCC = 12V Overvoltage Shutdown ■ Control (CTL) Control Input Current Sleep Mode Threshold Sleep Mode Hysteresis MIN 4V ≤ VCC ≤ 26V IADJ = 0V to 5V -2 VCC = 4V VCC = 13.2V VCC = 26V 2.0 4.85 4.85 4V ≤ VCC ≤ 7V 7V ≤ VCC ≤ 26V 40% 100 150 4V ≤ VCC < 7V ROSC = 93.1kΩ, COSC = 470pF 7V ≤ VCC ≤ 18V, ROSC = 93.1kΩ, COSC = 470pF 18V < VCC ≤ 26V ROSC = 93.1kΩ, COSC = 470pF 1196 0.3 50% 325 10 17 20 23 kHz 17 20 25 kHz PARAMETER TEST CONDITIONS ■ External Drive (OUTPUT): continued Voltage to Duty Cycle 4V ≤ VCC < 7V Conversion VCC = 13V, CTL = 1V VCC = 13V, CTL = 2V 7V ≤ VCC ≤ 18V VCC = 13V, CTL = 30% VREG VCC = 13V, CTL = 55.8% VREG 18V < VCC ≤ 26V VCC = 13V, CTL = 1. 5V VCC = 13V, CTL = 3. 5V Output Rise Time 4V ≤ VCC ≤ 26V RGATE = 6Ω, CGATE = 5nF Output Fall Time 4V ≤ VCC ≤ 26V RGATE = 6Ω, CGATE = 5nF Output Sink Current 4V ≤ VCC < 7V RGATE = 6Ω, CGATE = 5nF 7V ≤ VCC ≤ 26V RGATE = 6Ω, CGATE = 5nF Output Source Current 4V ≤ VCC < 7V RGATE = 6Ω, CGATE = 5nF 7V ≤ VCC ≤ 26V RGATE = 6Ω, CGATE = 5nF Output High Voltage IOUT = 1mA Output Low Voltage IOUT = -1mA MIN TYP 75 % % 28.3 56.0 36.3 64.0 % % 11.8 34.2 .25 21.8 44.2 1 % % µs .30 1 µs 150 mA 300 mA 150 mA 300 mA 1.3 VCC + 6.4 Package Lead Description LEAD SYMBOL FUNCTION 16 Lead PDIP 1 OUTPUT MOSFET gate drive 2 BOOST Boost voltage 3 FLT Fault time out capacitor 4 ROSC Oscillator resistor 5 COSC Oscillator capacitor 6 CTL Pulse width control input 7 PGnd Power ground for on chip clamp 8 VCC Positive power supply input 9 VREG 5V linear regulator 10 SNI Sense inductor current 11 PMP Collector of boost power transistor 12 ISENSE- Current sense minus 13 ISENSE+ Current sense plus 14 IADJ Current limit adjust 15 INH Output Inhibit 16 Gnd Ground 1197 UNIT 65 100 VBOOST - 1.7 ■ Charge Pump (DRV) Boost Voltage PACKAGE LEAD # MAX V V V CS4124 Electrical Characteristics: 4V ≤ VCC ≤ 26V, -40˚C < TA = 125°C, (unless otherwise specified) pensated duty cycle. The transfer is set up so that when VCC = 14V the duty cycle will equal VCTL divided by VREG. For example at VCC = 14V, VREG = 5V and VCTL = 2.5V, the duty cycle would be 50% at the output. This would place a 7V average voltage across the load. If VCC then drops to 10V, the IC would change the duty cycle to 70% and hence keep the average load voltage at 7V. Theory Of Operation Oscillator The IC sets up a constant frequency triangle wave at the COSC lead whose frequency is related to the external components ROSC and COSC, by the following equation: Frequency = 0.83 ROSC × COSC 120% The peak and valley of the triangle wave are proportional to VCC by the following: VCC = 8V 100% VVALLEY = 0.1 × VCC 80% Duty Cycle( %) CS4124 Application Information VPEAK = 0.7 × VCC This is required to make the voltage compensation function properly. In order to keep the frequency of the oscillator constant the current that charges COSC must also vary with supply. ROSC sets up the current which charges COSC. The voltage across ROSC is 50% of VCC and therefore: 0% 10% VPEAK - VVALLEY ICOSC The ROSC and COSC components can be varied to create frequencies over the range of 15Hz to 25kHz. With the suggested values of 93.1kΩ and 470pF for ROSC and COSC , the nominal frequency will be approximately 20 kHz. IROSC, at VCC = 14V, will be 66.7 µA. IROSC should not change over a more than 2:1 ratio and therefore COSC should be changed to adjust the oscillator frequency. VDC = (1.683 × VCTL) + VVALLEY is compared to the oscillator voltage to produce the com- 40% 50% 60% 70% 80% 90% 100% 5V Linear Regulator There is a 5V, 5mA linear regulator available at the VREG lead for external use. This voltage acts as a reference for many internal and external functions. It has a drop out of approximately 1.5V at room temperature. ROSC An internal DC voltage equal to: 30% Figure 1: Voltage Compensation VCC Voltage Duty Cycle Conversion The IC translates an input voltage at the CTL lead into a duty cycle at the OUTPUT lead. The transfer function incorporates Cherry Semiconductor’s patented Voltage Compensation method to keep the average voltage and current across the load constant regardless of fluctuations in the supply voltage. The duty cycle is varied based upon the input voltage and supply voltage by the following equation: 2.8 × VCTL Duty Cycle = 100% × VCC 20% CTL Voltage (% of VREG) The period of the oscillator is: T = 2COSC × VCC = 16V 20% ROSC IROSC is multiplied by (2) internally and transferred to the COSC lead. Therefore: ICOSC = ± 60% 40% VCC IROSC = 0.5 × VCC = 14V Current Sense and Timer The IC differentially monitors the load current on a cycle by cycle basis at the ISENSE+ and ISENSE- leads. The differential voltage across these two leads is amplified internally and compared to the voltage at the IADJ lead. The gain, AV is set internally and externally by the following equation: AV = VI(ADJ) ISENSE+ - ISENSE- = 37000 1000 + RCS The current limit (ILIM) is set by the external current sense resistor (RSENSE) placed across the ISENSE+ and ISENSE- terminals and the voltage at the IADJ lead. ILIM = 1000 + RCS 37000 × VI(ADJ) RSENSE The RCS resistors and CCS components form a differential low pass filter which filters out high frequency noise generated by the switching of the external MOSFET and the associated lead noise. RCS also forms and error term in the gain of the ILIM equation because the ISENSE+ and ISENSEleads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50µA while the chip is in run mode. IADJ should be biased between 1V and 4V. When the current through the external MOSFET 1198 exceeds ILIM, an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscillator cycle (fault mode). At the start of the next cycle, the latch is reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC “times out” and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the CFLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from CFLT. If enough faults occur together, eventually CFLT will charge up to 2.4V and the fault latch will be set. The fault latch will not be reset until CFLT discharges to 0.6V. This action will continue indefinitely if the fault persists. The off time and on time are set by the following: Off Time = CFLT × On Time = CFLT × 2.4V - 0.6V 4.5µA 2.4V - 0.6V IAVG Sleep State This device will enter into a low current mode (< 275µA) when CTL lead is brought to less than 0.5V. All functions are disabled in this mode, except for the regulator. Inhibit When the inhibit is greater than 2.5V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle. Overvoltage Shutdown The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is 325mV (typical) of hysteresis on the overvoltage function. There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom. Reverse Battery The CS4124 will not survive a reverse battery condition. A series diode is required between the battery and the VCC lead for reverse battery. where: IAVG = (295.5µA × DC ) - [4.5µA × (1 - DC )] IAVG = (300µA × DC ) - 4.5µA Load Dump A 10Ω resistor, (RS) is placed in series with VCC to limit the current into the IC during 40V peak transient conditions. DC = PWM Duty Cycle Boost Switch Mode Power Supply The CS4124 has an integrated boost mode power supply which charges the gate of the external high-side MOSFET to greater than 5V above VCC. Three leads are used for voltage boost. They are Boost, PMP and SNI. The PMP lead is the collector of a darlington tied NPN power transistor. This device charges the inductor during its on time. The boost lead is the input to chip from the external reservoir capacitor. The SNI lead is the emitter of the power NPN and is connected externally to the RSNI resistor. The power supply is controlled by the oscillator. At the start of a cycle an R-S flip flop is set the internal power NPN transistor is turned on and energy begins to build up in the inductor. The RSNI resistor sets the peak current of the inductor by tripping a comparator when the voltage across the resistor is 450mV. The flip flop is reset and the inductor delivers its stored energy to the load. The ripple voltage (VRIPPLE) at the Boost lead is controlled by CBOOST. A snubber circuit, made up of a series resistor and capacitor, is required to dampen the ringing of the inductor. A value of 4Ω is recommended for RSNI. A zener diode is needed between the boost output voltage and the battery. This will clamp the boost lead to a specified value above the battery to prevent damage to the IC. A 9 volt zener diode is recommended. 1199 CS4124 Application Information: continued CS4124 Package Specification PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA Thermal Data D Lead Count Metric Max Min 19.69 18.67 16L PDIP English Max Min .775 .735 RΘJC RΘJA typ typ 16 Lead PDIP 42 80 ˚C/W ˚C/W Plastic DIP (N); 300 mil wide 7.11 (.280) 6.10 (.240) 8.26 (.325) 7.62 (.300) 1.77 (.070) 1.14 (.045) 2.54 (.100) BSC 3.68 (.145) 2.92 (.115) .356 (.014) .203 (.008) 0.39 (.015) MIN. .558 (.022) .356 (.014) REF: JEDEC MS-001 D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. Ordering Information Part Number CS4124YN16 Rev. 4/26/99 Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Description 16L PDIP 1200 © 1999 Cherry Semiconductor Corporation