CS7054 Low Side PWM FET Controller The CS7054 is a monolithic integrated circuit designed primarily to control the rotor speed of permanent magnet, direct current (DC) brush motors. It drives the gate of an N channel power MOSFET or IGBT with a user–adjustable, fixed frequency, variable duty cycle, pulse width modulated (PWM) signal. The CS7054 can also be used to control other loads such as incandescent bulbs and solenoids. Inductive current from the motor or solenoid is recirculated through an external diode. The CS7054 accepts a DC level input signal of 0 to 5.0 V to control the pulse width of the output signal. This signal can be generated by a potentiometer referenced to the on–chip 5.0 V linear regulator, or a filtered 0% to 100% PWM signal also referenced to the 5.0 V regulator. The IC is placed in a sleep state by pulling the CTL lead below 0.5 V. In this mode everything on the chip is shut down except for the on–chip regulator and the overall current draw is less than 275 µA. There are a number of on–chip diagnostics that look for potential failure modes and can disable the external power MOSFET. DIP–14 N SUFFIX CASE 646 14 1 SO–16L DW SUFFIX CASE 751G 16 1 PIN CONNECTIONS AND MARKING DIAGRAMS 1 OUTPUT GND FLT COSC ROSC CTL CS7054 AWLYYWW Features 200 mA Peak PWM Gate Drive Output Patented Voltage Compensation Circuit 100% Duty Cycle Capability 5.0 V, ± 3.0% Linear Regulator Low Current Sleep Mode Overvoltage Protection Overcurrent Protection of External MOSFET/IGBT Output Inhibit • • • • • • • • http://onsemi.com 14 VCC PGND INH IADJ ISENSE+ ISENSE– NC VREG DIP–14 1 CS7054 AWLYYWW OUTPUT GND FLT COSC ROSC CTL NC NC 16 VCC NC PGND INH IADJ ISENSE+ ISENSE– VREG SO–16L A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2001 January, 2001 – Rev. 12 1 Package Shipping CS7054YN14 DIP–14 25 Units/Rail CS7054YDW16 SO–16L 46 Units/Rail CS7054YDWR16 SO–16L 1000 Tape & Reel Publication Order Number: CS7054/D CS7054 MOT+ VBAT 42.5 µH RGATE 6 RS MOT– 51 10 µF 1000 µF 1000 µF 0.25 µF CFLT 390 pF COSC ROSC VCC PGND 1.0 M INH FLT CS7054 COSC ROSC CTL NC 105 k PWM Input OUTPUT GND 0.01 µF IADJ ISENSE+ ISENSE– VREG RCS1 CCS 51 Ω 0.022 µF RCS2 RSENSE 4.0 mΩ 51 Ω 10 k 10 k 10 k 10 k N1 P1 100 k 10 k 10 µF 10 k 10 k Figure 1. Application Diagram ABSOLUTE MAXIMUM RATINGS* Rating Value Unit Storage Temperature –65 to 150 °C VCC –0.3 to 30 V 40 V –0.3 to 10 V Maximum Junction Temperature 150 °C ESD Susceptibility (Human Body Model) 2.0 kV 260 peak 230 peak °C °C Supply Voltage Range (Load Dump = 26 V w/Series 51 Ω Resistor) VCC Peak Transient Voltage Input Voltage Range (at any input) Lead Temperature Soldering Wave Solder (through hole styles only) Note 1. Reflow (SMD styles only) Note 2. 1. 10 seconds max. 2. 60 seconds max above 183°C *The maximum package power dissipation must be observed. http://onsemi.com 2 CS7054 ELECTRICAL CHARACTERISTICS (8.0 V < VCC < 16 V; –40°C < TA < 125°C; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit – – 5.0 10 mA – 170 275 µA VCC Supply Operating Current Supply Quiescent Current VCC = 12 V Overvoltage Shutdown – 18 19.5 21 V Overvoltage Hysteresis – 150 325 500 mV –2.0 0.1 2.0 µA Control (CTL) Control Input Current CTL = 0 V to 5.0 V Sleep Mode Threshold – 8.0 10 12 % VREG Sleep Mode Hysteresis – 50 100 150 mV Current Sense Differential Voltage Sense IADJ = 51.2% VREG and RCS1 = 51 Ω 60.5 – 79.5 mV IADJ Input Current IADJ = 0 V to 5.0 V –5.0 0.3 2.0 µA VCC = 13.2 V 4.85 5.00 5.15 V Linear Regulator Output Voltage Inhibit Inhibit Threshold – 40 50 60 % VREG Inhibit Hysteresis – 150 325 575 mV 17 20 23 kHz 26.3 69.5 – – 38.5 81.5 % % External Drive (OUTPUT) Output Frequency ROSC = 105 kΩ, COSC = 390 pF Voltage to Duty Cycle Conversion VCC = 13 V, CTL = 30% VREG VCC = 13 V, CTL = 70% VREG Output Rise Time VCC = 13 V, RGATE = 6.0 Ω, CGATE = 5.0 nF – 0.25 1.0 µs Output Fall Time VCC = 13 V, RGATE = 6.0 Ω, CGATE = 5.0 nF – 0.3 1.0 µs Output Sink Current VCC = 13 V, RGATE = 6.0 Ω, CGATE = 5.0 nF – 400 – mA Output Source Current VCC = 13 V, RGATE = 6.0 Ω, CGATE = 5.0 nF – 400 – mA Output High Voltage IOUT = 1.0 mA VCC – 1.7 – – V Output Low Voltage IOUT = –1.0 mA – – 1.3 V http://onsemi.com 3 CS7054 PACKAGE PIN DESCRIPTION PACKAGE PIN # DIP–14 SO–16L PIN SYMBOL 1 1 OUTPUT 2 2 GND Ground. 3 3 FLT Fault time out capacitor. 4 4 COSC Oscillator capacitor. 5 5 ROSC Oscillator resistor. 6 6 CTL Pulse width control input. 7 7, 8, 15 NC No connection. 8 9 VREG 5.0 V linear regulator. 9 10 ISENSE– Current sense minus. 10 11 ISENSE+ Current sense plus. 11 12 IADJ Current limit adjust. 12 13 INH Output Inhibit. 13 14 PGND 14 16 VCC FUNCTION MOSFET Gate Drive. Power ground for on chip clamp. Positive power supply input. GND VREG VCC 5.0 V Regulator Overvoltage Clamp VCC OUTPUT + _ PGND + _ CTL + _ + _ INH Q S R Reset Current Sense Triangle Oscillator ISENSE+ ISENSE– Timer Out In FLT COSC ROSC Figure 2. Block Diagram http://onsemi.com 4 + _ IADJ CS7054 TYPICAL PERFORMANCE CHARACTERISTICS 5.04 5.04 2.0 mA 5.02 100 µA 5.02 100 µA 2.0 mA VREG 5.00 VREG 5.00 4.98 5.0 mA 4.98 5.0 mA 4.96 4.96 4.94 –50 0 50 4.94 –50 150 100 0 Temperature 50 100 150 Temperature Figure 3. VREG vs. Temperature @ VCC = 8.0 V Figure 4. VREG vs. Temperature @ VCC = 12 V 1.7 5.04 2.0 mA 100 µA 1.6 5.02 1.5 OUTPUT VREG 5.00 5.0 mA 4.98 I = 2.0 mA 1.4 1.3 1.2 4.96 1.1 0 50 1.0 –50 150 100 0 50 100 150 Temperature Temperature Figure 5. VREG vs. Temperature @ VCC = 16 V Figure 6. OUTPUT Saturation Voltage (Sourcing Current) vs Temperature 1.3 I = 2.0 mA OUTPUT 4.94 –50 1.2 1.1 –50 0 50 100 Temperature Figure 7. OUTPUT Voltage (Sinking Current) vs Temperature http://onsemi.com 5 150 CS7054 APPLICATIONS INFORMATION THEORY OF OPERATION is compared to the oscillator voltage to produce the compensated duty cycle. The transfer is set up so that at VCC = 14 V the duty will equal VCTL divided by VREG. For example at VCC = 14 V, VREG = 5.0 V and VCTL = 2.5 V, the duty cycle would be 50% at the output. This would place a 7.0 V average voltage across the load. If VCC then drops to 10 V, the IC would change the duty cycle to 70% and hence keep the average load voltage at 7.0 V. Oscillator The IC sets up a constant frequency triangle wave at the COSC lead whose frequency is determined by the external components ROSC and COSC by the following equation: Frequency 0.83 ROSC COSC 120 VVALLEY 0.2 VCC 100 VPEAK 0.8 VCC 80 Duty Cycle (%) The peak and valley of the triangle wave are proportional to VCC by the following: This is required to make the voltage compensation function properly. In order to keep the frequency of the oscillator constant the current that charges COSC must also vary with supply. ROSC sets up the current which charges COSC. The voltage across ROSC is 50% of VCC and therefore: VCC = 8.0 V VCC = 14 V 60 VCC = 16 V 40 20 0 10 V IROSC 0.5 CC ROSC 20 IROSC is multiplied by two (2) internally and transferred to the COSC lead. Therefore: 50 40 60 70 80 CTL Voltage (% of VREG) 90 100 Figure 8. Voltage Compensation 5.0 V Linear Regulator V ICOSC CC ROSC There is a 5.0 V, 5.0 mA linear regulator available at the VREG lead for external use. This voltage acts as a reference for many internal and external functions. It has a drop out of approximately 1.5 V at room temperature and does not require an external capacitor for stability. The period of the oscillator is: V VVALLEY T 2COSC PEAK ICOSC The ROSC and COSC components can be varied to create frequencies over the range of 15 Hz to 25 kHz. With the suggested values of 105 kΩ and 390 pF for ROSC and COSC respectively, the nominal frequency will be approximately 20 kHz. IROSC, at VCC = 14 V, will be 66.7 µA. IROSC should not change over a more than 2:1 ratio and therefore COSC should be changed to adjust the oscillator frequency. Current Sense and Timer The IC differentially monitors the load current on a cycle by cycle basis at the ISENSE+ and ISENSE– leads. The differential voltage across these two leads is amplified internally and compared to the voltage at the IADJ lead. The gain, AV, is set internally and externally by the following equation: Voltage Duty Cycle Conversion AV The IC translates an input voltage at the CTL lead into a duty cycle at the OUTPUT lead. The transfer function incorporates ON Semiconductor’s patented Voltage Compensation method to keep the average voltage and current across the load constant regardless of fluctuations in the supply voltage. The duty cycle is varied based upon the input voltage and supply voltage by the following equation: Duty Cycle 100% 30 VI(ADJ) ISENSE ISENSE 37000 1000 RCS The current limit (ILIM) is set by the external current sense resistor (RSENSE) placed across the ISENSE+ and ISENSE– terminals and the voltage at the IADJ lead. ILIM 2.8 VCTL VCC 1000 RCS V I(ADJ) 37000 RSENSE The RCS resistors and CCS components form a differential low pass filter which filters out high frequency noise generated by the switching of the external MOSFET and the associated lead noise. RCS also forms an error term in the gain of the ILIM equation because the ISENSE+ and ISENSE– An internal DC voltage equal to: VDC (1.683 VCTL) VVALLEY http://onsemi.com 6 CS7054 Overvoltage Shutdown leads are low impedance inputs thereby creating a good current sensing amplifier. Both leads source 50 µA while the chip is in run mode. RCS should be much less than 1000 Ω to minimize error in the ILIM equation. IADJ should be biased between 1.0 V and 4.0 V. When the current through the external MOSFET exceeds ILIM, an internal latch is set and the output pulls the gate of the MOSFET low for the remainder of the oscillator cycle (fault mode). At the start of the next cycle, the latch is reset and the IC reverts back to run mode until another fault occurs. If a number of faults occur in a given period of time, the IC “times out” and disables the MOSFET for a long period of time to let it cool off. This is accomplished by charging the CFLT capacitor each time an over current condition occurs. If a cycle goes by with no overcurrent fault occurring, an even smaller amount of charge will be removed from CFLT. If enough faults occur together, eventually CFLT will charge up to 2.4 V and the fault latch will be set. The fault latch will not be reset until the CFLT discharges to 0.6 V. This action will continue indefinitely if the fault persists. The off time and on time are set by the following: Off Time CFLT 2.4 V 0.6 V 4.5 A On Time CFLT 2.4 V 0.6 V IAVG The IC will disable the output during an overvoltage event. This is a real time fault event and does not set the internal latch and therefore is independent of the oscillator timing (i.e. asynchronous). There is no undervoltage lockout. The device will shutdown gracefully once it runs out of headroom. This happens at the point when VREG falls out of regulation. Reverse Battery The CS7054 will not survive a reverse battery condition. Therefore, a series diode is required between the battery and the VCC lead. Load Dump VCC is internally clamped to 30 V. It is recommended that a 51 Ω resistor, (RS) is placed in series with VCC to limit the current flow into the IC in the event of a 40 V peak transient condition. Using the CS7054 as a Frequency Converter Figure 9 shows the CS7054 configured for use as a frequency converter. In the setup shown, a 150 Hz square wave from a microprocessor is converted to a 10 kHz square wave. The duty cycle of each waveform is identical. The amplitude of the input waveform is 5.0 V, but does not need to be. The input amplitude requirement just needs to be high enough to switch the external bipolar transistor. The 10 kHz oscillator frequency is setup per the oscillator section of this data sheet. The external resistor divider composed of the 3.6 k and 6.2 k resistors supplies 5.0 V to the CTL pin when the input duty cycle is at 100%. This also makes the output waveform 100%. The RC filter (1.0 MΩ and 0.1 µF) sets up a pole at 1.6 Hz: where: IAVG (295.5 A DC) [4.5 A (1 DC)] IAVG (300 A DC) 4.5 A DC PWM Duty Cycle f Sleep State This device will enter into a low current mode (< 275 µA) when CTL lead is brought to less than 0.5 V. All functions are disabled in this mode, except for the regulator. 1 2RC 1 2 1 M 6.2 k3.6 k (0.1 F) (6.2 k)(3.6 k) 1.6 Hz In this case, the pole is 2 orders of magnitude below the input waveform. Care must be taken to provide the appropriate DC level on the control pin in addition to providing the required response time. *Note the current limit feature of the CS7054 has been defeated by grounding the ISENSE+ and the ISENSE– pins and connecting the IADJ lead to VREG. Inhibit When the inhibit voltage is greater than 2.5 V the internal latch is set and the external MOSFET will be turned off for the remainder of the oscillator cycle. The latch is then reset at the start of the next cycle. http://onsemi.com 7 CS7054 10 Ω VBAT 10 µF VCC 0 f = 10 kHz VCC OUTPUT GND PGND INH FLT 820 pF 100 kΩ 150 Hz 5.0 V 0 CS7054 COSC IADJ ROSC ISENSE+ CTL ISENSE– NC VREG MCU 100 k 100 k 6.2 k 1.0 MΩ Q2 Q1 3.6 k 100 k Figure 9. Frequency Converter http://onsemi.com 8 0.1 µF CS7054 PACKAGE DIMENSIONS DIP–14 N SUFFIX CASE 646–04 ISSUE M 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. 8 B 1 7 A F DIM A B C D F G H J K L M N L N C –T– SEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.740 0.240 0.260 0.160 0.180 0.015 0.020 0.040 0.060 0.100 BSC 0.052 0.072 0.008 0.012 0.115 0.135 0.290 0.310 --10 0.020 0.040 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 4.06 4.57 0.38 0.51 1.02 1.52 2.54 BSC 1.32 1.83 0.20 0.30 2.92 3.43 7.37 7.87 --10 0.51 1.02 M SO–16L DW SUFFIX CASE 751G–03 ISSUE B A D 9 1 8 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. 16X M T A S B h X 45 DIM A A1 B C D E e H h L S 14X e L A 0.25 B B A1 H E 0.25 8X M B M 16 SEATING PLANE C T MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 PACKAGE THERMAL DATA DIP–14 SO–16L Unit RΘJC Typical 48 23 °C/W RΘJA Typical 85 105 °C/W Parameter http://onsemi.com 9 CS7054 Notes http://onsemi.com 10 CS7054 Notes http://onsemi.com 11 CS7054 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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