SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 D Available in the Texas Instruments D 3.6-V I/O Tolerant to Support Mixed-Mode NanoStar and NanoFree Packages Low Static-Power Consumption; ICC = 0.9 µA Max Low Dynamic-Power Consumption; Cpd = 4.4 pF Typ at 3.3 V Low Input Capacitance; Ci = 1.5 pF Typ Low Noise − Overshoot and Undershoot <10% of VCC Ioff Supports Partial-Power-Down Mode Operation Includes Schmitt-Trigger Inputs Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation D D D D D D D D 1 5 NC VCC A A 3 D 1 5 DRL PACKAGE (TOP VIEW) VCC NC 1 A 2 GND 2 GND D DCK PACKAGE (TOP VIEW) DBV PACKAGE (TOP VIEW) NC D D D Signal Operation tpd = 5.1 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) ESD Protection Exceeds ±5000 V With Human-Body Model GND 4 3 4 YEP OR YZP PACKAGE (BOTTOM VIEW) VCC 5 2 A 3 DNU Y 4 Y 3 4 GND Y 2 1 5 VCC DNU – Do not use Y See mechanical drawings for dimensions. description /ordering information The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2). Static-Power Consumption (µA) 100% 80% 60% 3.3-V Logic† 3.3-V Logic LVC † 40% AUP 0% 2.5 Input 2 Output 1.5 1 0.5 20% 20% 0% Voltage − V 40% 3.5 3 80% 60% Switching Characteristics at 25 MHz† Dynamic-Power Consumption (pF) 100% AUP † Single, dual, and triple gates 0 −0.5 0 5 10 15 20 25 30 Time − ns 35 40 45 † AUP1G08 data at CL = 15 pF Figure 1. AUP−The Lowest-Power Family Figure 2. Excellent Signal Integrity Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2005, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 description/ordering information (continued) This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP SN74AUP1G17YEPR NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) −40°C to 85°C TOP-SIDE MARKING‡ SOT (SOT-23) − DBV SOT (SC-70) − DCK SOT (SOT-553) − DRL Reel of 3000 _ _ _H7_ SN74AUP1G17YZPR Reel of 3000 SN74AUP1G17DBVR Reel of 250 SN74AUP1G17DBVT Reel of 3000 SN74AUP1G17DCKR Reel of 250 SN74AUP1G17DCKT Reel of 4000 SN74AUP1G17DRLR † H17_ H7_ H7_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUT A OUTPUT Y H H L L logic diagram (positive logic) 2 4 A 2 POST OFFICE BOX 655303 Y • DALLAS, TEXAS 75265 SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Output voltage range in the high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC VI Supply voltage 0.8 3.6 V Input voltage 0 3.6 V VO Output voltage 0 VCC −20 V VCC = 0.8 V VCC = 1.1 V IOH‡ High-level output current VCC = 1.4 V VCC = 1.65 −1.7 VCC = 2.3 V VCC = 3 V −3.1 VCC = 0.8 V VCC = 1.1 V IOL‡ Low-level output current µA −1.1 −1.9 mA −4 20 µA 1.1 VCC = 1.4 V VCC = 1.65 V 1.7 VCC = 2.3 V VCC = 3 V 3.1 1.9 mA 4 TA Operating free-air temperature −40 85 °C ‡ Defined by the signal-integrity requirements and design-goal priorities NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT− Negative-going input threshold voltage ∆V VT Hysteresis (VT+ − VT−) VCC 0.3 0.6 0.3 1.1 V 0.53 0.9 0.53 0.9 1.4 V 0.74 1.11 0.74 1.11 1.65 V 0.91 1.29 0.91 1.29 2.3 V 1.37 1.77 1.37 1.77 3V 1.88 2.29 1.88 2.29 0.1 0.6 0.1 0.6 1.1 V 0.26 0.65 0.26 0.65 1.4 V 0.39 0.75 0.39 0.75 1.65 V 0.47 0.84 0.47 0.84 2.3 V 0.69 1.04 0.69 1.04 1.24 3V 0.88 1.24 0.88 0.8 V 0.07 0.5 0.07 0.5 1.1 V 0.08 0.46 0.08 0.46 1.4 V 0.18 0.56 0.18 0.56 1.65 V 0.27 0.66 0.27 0.66 2.3 V 0.53 0.92 0.53 0.92 0.79 1.31 0.79 1.31 VOH 1.03 1.3 2.05 1.97 1.9 1.85 2.72 2.67 2.6 0.8 V to 3.6 V IOL = 1.7 mA IOL = 1.9 mA IOL = 2.3 mA IOL = 3.1 mA VI = GND to 3.6 V VI or VO = 0 V to 3.6 V ∆Ioff ICC VI or VO = 0 V to 3.6 V VI = GND or (VCC to 3.6 V), IO = 0 ∆ICC VI = VCC − 0.6 V, IO = 0 V V 2.55 0.1 1.1 V 0.3 × VCC 0.3 × VCC 1.4 V 0.31 0.37 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 3V V V 0.1 2.3 V IOL = 2.7 mA IOL = 4 mA 4 1.11 1.32 3V IOL = 20 µA IOL = 1.1 mA A input 1.4 V 1.65 V 2.3 V IOH = −2.7 mA IOH = −4 mA II Ioff VCC − 0.1 0.7 × VCC 1.1 V IOH = −2.3 mA IOH = −3.1 mA VOL VCC − 0.1 0.75 × VCC UNIT 0.6 0.8 V 0.8 V to 3.6 V IOH = −1.7 mA IOH = −1.9 mA TA = −40°C TO 85°C MIN MAX 0.8 V 3V IOH = −20 µA IOH = −1.1 mA TA = 25°C MIN MAX V 0.44 0.45 0 V to 3.6 V 0.1 0.5 µA 0V 0.2 0.6 µA 0 V to 0.2 V 0.2 0.6 µA 0.8 V to 3.6 V 0.5 0.9 µA 3.3 V 40 50 µA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Ci VI = VCC or GND Co VO = GND VCC 0V TYP 3.6 V 1.5 0V 2.5 UNIT 1.5 pF pF switching characteristics over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V tpd A Y TA = −40°C TO 85°C TA = 25°C TYP UNIT MAX MIN MAX 22.7 1.2 V ± 0.1 V 6.3 8 12.8 3.9 14.6 1.5 V ± 0.1 V 4.6 5.8 8.4 2.8 10 1.8 V ± 0.15 V 3.9 4.8 7.2 2.4 8.1 2.5 V ± 0.2 V 3.1 3.6 5.1 2 6.1 3.3 V ± 0.3 V 2.7 3 4.4 1.9 5.1 ns switching characteristics over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A Y TA = −40°C TO 85°C TA = 25°C VCC TYP UNIT MAX MIN MAX 25.1 1.2 V ± 0.1 V 7.1 9.1 13.8 4.7 15.6 1.5 V ± 0.1 V 5.2 6.5 9.4 3.4 11 1.8 V ± 0.15 V 4.5 5.4 8 2.9 9 2.5 V ± 0.2 V 3.5 4.2 5.7 2.4 6.8 3.3 V ± 0.3 V 3.1 3.5 4.9 2.2 5.7 ns switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A Y POST OFFICE BOX 655303 TA = −40°C TO 85°C TA = 25°C VCC TYP MAX MIN MAX 27.6 1.2 V ± 0.1 V 7.8 10.1 14.8 5.3 16.7 1.5 V ± 0.1 V 5.8 7.4 10.3 3.9 12 1.8 V ± 0.15 V 5 6.1 8.8 3.4 10 2.5 V ± 0.2 V 4 4.7 6.4 2.8 7.5 3.3 V ± 0.3 V 3.5 4.1 5.4 2.6 6.2 • DALLAS, TEXAS 75265 UNIT ns 5 SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 switching characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A Y TA = −40°C TO 85°C TA = 25°C VCC TYP UNIT MAX MIN MAX 35.1 1.2 V ± 0.1 V 10 13.1 18.1 7.5 19.8 1.5 V ± 0.1 V 7.4 9.6 12.9 5.6 14.9 1.8 V ± 0.15 V 6.4 7.9 11 4.8 12.4 2.5 V ± 0.2 V 5.2 6.1 7.9 4 9.3 3.3 V ± 0.3 V 4.6 5.3 6.7 3.6 7.7 ns operating characteristics, TA = 25°C PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance f = 10 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC 0.8 V TYP UNIT 4 1.2 V ± 0.1 V 4 1.5 V ± 0.1 V 4 1.8 V ± 0.15 V 4 2.5 V ± 0.2 V 4.2 3.3 V ± 0.3 V 4.4 pF SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Width) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPHL tPLH VOH VM Output VM VOL tPHL VCC Timing Input 0V tPLH tsu VOH VM Output th VCC VM VOL Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCES579C – JUNE 2004 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 × VCC 5 kΩ From Output Under Test CL (see Note A) S1 GND 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 VCC/2 0V tPLZ tPZL VCC VCC/2 VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AUP1G17DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DRLR ACTIVE SOP DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17DRLRG4 ACTIVE SOP DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G17YEPR NRND WCSP YEP 5 3000 TBD SNPB Level-1-260C-UNLIM SN74AUP1G17YZPR ACTIVE WCSP YZP 5 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2006 information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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